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Mon, 18 May 2026 00:15:00 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 1/8] net/mlx5: Use helper to parse host PF info Date: Mon, 18 May 2026 10:13:49 +0300 Message-ID: <20260518071356.345723-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|MN2PR12MB4064:EE_ X-MS-Office365-Filtering-Correlation-Id: 9407d770-14dd-4674-c9b8-08deb4ad3a8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700016|1800799024|3023799003|11063799003|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: BDOpx5K3EXclyx7puify2ep3zVi0S8krGV58N5jhNpIgZOL8qgk152OADXhWLD/tRFABNYPXXkYE/K2tYFfs16bqfg8QFYk9l7dr6kQH6CbCklMb7+Zep2Nx0wX1KFqMkUdYo+xCD+vfrcjk1TD+oCUF4MVAL0W7lUXD4J1XzWl4zUOjINLqM8vyuUb+EC3OwL6uAXb710EdpqtihIQsOdT48hNEYbBjySBDK4uC4BVgx1r1H8kHOV8Tmlfsxs6zOebiyHBWTIQSoXjjBUl+uGXnnH5TALNrPbcTo8oKcXJGmNDn3ObDE1oaDD2+vad0B/4FO5v1jIivNqftHOt/9RIQLu1r8pGqe+uImOgJZI6HZdS7PktOwpY1P6rC7eLB0uq2ZCd/PZIYNZRmUVZdLos3Cj2iXMccThoGf5iBpcp1U09ucIaUJNbpv9aAPUctU3b91vWaYRP+cKZ2zsrQsUDRBak9wwHFDypc7iSu9YQx5wtzi7xkIbe4zSPKy/urlACDhEYIjjzdpz6iScwUDFvUZ9ktiAql5k5k5zi871r2YjMn2aOvAO3WX+5CnghkEEyG5gKCEZhnrwRfF8USJzWY+/CoI9v2UlaI5KQqeqpwSxHOiNWlUeAOLO0v2wKWiJHiA1rPYQ9Bz/uzEmmGYCTB+zZWJklkYjawRb+bkhpm9vMUYdhXN8bUB6UVGDXWp2eTYvZfPwgsyKuHwrNK9cGKzRKxok9/ovtUf8WGUYs= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700016)(1800799024)(3023799003)(11063799003)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qkIbfv9C0+8hBFKAhiYua9dFMNFl1qHvxA/CcbZj9mcCmxVsWVhk810FK1WAmeTQ2nHDBmFacSAOxZh02JxJiyCBfK/+UMy3dQSy7Mkziro80Mog2KQmFACrva00yZWpOAnw+GC2O7sa8Nx8uewlO31JpzWx0JmPxqkyZDfW+ryFnNDb4VaCAnyPIKDUqc1DbQPmQv2WsMhdpbEin5dtw3Wob/9KhaZVaxr0QzkBQKIEXmoUQrweztDUWEq7myHiOKZ4i+em//FtyQC5ClkcSKMx9TovHLYBu5MrlVJ8+dH4s5LttfPeicVrXE3GzC+RjzMe9dglpgvZk/kLjXu5lKduzBd+sQMfVuDQ53bXtq97IdYGdWqDHXa3zbOortddltmSMCIJwBHfBdBn8q2iRfoDthSEqs/ruIsAUWRa/Qa2Ih9rhNhWupNpcoyhkrd4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:23.6552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9407d770-14dd-4674-c9b8-08deb4ad3a8f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4064 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add a helper mlx5_esw_get_host_pf_info() to retrieve host PF data from the query_esw_functions command output, so callers no longer need to parse the layout to obtain the required information. Convert all callers of mlx5_esw_query_functions() to use the new helper, preparing for upcoming support of the new op_mod that returns data in the network_function_params layout. Signed-off-by: Moshe Shemesh Reviewed-by: Simon Horman Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 43 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 15 +++++++ .../mellanox/mlx5/core/eswitch_offloads.c | 34 ++++++--------- .../net/ethernet/mellanox/mlx5/core/sriov.c | 8 ++-- 4 files changed, 62 insertions(+), 38 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 43c40353b2d8..861e79ddb489 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1083,10 +1083,36 @@ const u32 *mlx5_esw_query_functions(struct mlx5_cor= e_dev *dev) return ERR_PTR(err); } =20 +static struct mlx5_esw_pf_info +mlx5_esw_host_pf_from_host_params(const void *entry) +{ + return (struct mlx5_esw_pf_info) { + .pf_not_exist =3D MLX5_GET(host_params_context, entry, + host_pf_not_exist), + .pf_disabled =3D MLX5_GET(host_params_context, entry, + host_pf_disabled), + .num_of_vfs =3D MLX5_GET(host_params_context, entry, + host_num_of_vfs), + .total_vfs =3D MLX5_GET(host_params_context, entry, + host_total_vfs), + .host_number =3D MLX5_GET(host_params_context, entry, + host_number), + }; +} + +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out) +{ + const void *entry; + + entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); + + return mlx5_esw_host_pf_from_host_params(entry); +} + static int mlx5_esw_host_functions_enabled_query(struct mlx5_eswitch *esw) { + struct mlx5_esw_pf_info host_pf_info; const u32 *query_host_out; - void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -1095,11 +1121,8 @@ static int mlx5_esw_host_functions_enabled_query(str= uct mlx5_eswitch *esw) if (IS_ERR(query_host_out)) return PTR_ERR(query_host_out); =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, - query_host_out, net_function_params); - esw->esw_funcs.host_funcs_disabled =3D - MLX5_GET(host_params_context, host_params, - host_pf_not_exist); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + esw->esw_funcs.host_funcs_disabled =3D host_pf_info.pf_not_exist; =20 kvfree(query_host_out); return 0; @@ -1523,7 +1546,7 @@ static void mlx5_eswitch_get_devlink_param(struct mlx= 5_eswitch *esw) static void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, int num_vfs) { - void *host_params; + struct mlx5_esw_pf_info host_pf_info; const u32 *out; =20 if (num_vfs < 0) @@ -1538,10 +1561,8 @@ mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *= esw, int num_vfs) if (IS_ERR(out)) return; =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - esw->esw_funcs.num_vfs =3D MLX5_GET(host_params_context, host_params, - host_num_of_vfs); + host_pf_info =3D mlx5_esw_get_host_pf_info(out); + esw->esw_funcs.num_vfs =3D host_pf_info.num_of_vfs; if (mlx5_core_ec_sriov_enabled(esw->dev)) esw->esw_funcs.num_ec_vfs =3D num_vfs; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 291271afa96c..cfaae59a6e7c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -71,6 +71,14 @@ struct mlx5_mapped_obj { }; }; =20 +struct mlx5_esw_pf_info { + bool pf_not_exist; + bool pf_disabled; + u16 num_of_vfs; + u16 total_vfs; + u16 host_number; +}; + #ifdef CONFIG_MLX5_ESWITCH =20 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 @@ -649,6 +657,7 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *de= v0, struct mlx5_core_dev *dev1); =20 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out); int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 @@ -976,6 +985,12 @@ static inline const u32 *mlx5_esw_query_functions(stru= ct mlx5_core_dev *dev) return ERR_PTR(-EOPNOTSUPP); } =20 +static inline struct mlx5_esw_pf_info +mlx5_esw_get_host_pf_info(const u32 *out) +{ + return (struct mlx5_esw_pf_info) {}; +} + static inline struct mlx5_flow_handle * esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index d95af87a4f5f..217c2fe6b690 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3708,8 +3708,7 @@ static void esw_offloads_steering_cleanup(struct mlx5= _eswitch *esw) =20 static void esw_vfs_changed_event_handler(struct mlx5_eswitch *esw) { - bool host_pf_disabled; - void *host_params; + struct mlx5_esw_pf_info host_pf_info; u16 new_num_vfs; const u32 *out; =20 @@ -3717,14 +3716,10 @@ static void esw_vfs_changed_event_handler(struct ml= x5_eswitch *esw) if (IS_ERR(out)) return; =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - new_num_vfs =3D MLX5_GET(host_params_context, host_params, - host_num_of_vfs); - host_pf_disabled =3D MLX5_GET(host_params_context, host_params, - host_pf_disabled); + host_pf_info =3D mlx5_esw_get_host_pf_info(out); + new_num_vfs =3D host_pf_info.num_of_vfs; =20 - if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_disabled) + if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_info.pf_disabled) goto free; =20 mlx5_esw_reps_block(esw); @@ -3826,8 +3821,8 @@ int mlx5_esw_funcs_changed_handler(struct notifier_bl= ock *nb, =20 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) { + struct mlx5_esw_pf_info host_pf_info; const u32 *query_host_out; - void *host_params; =20 if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) return 0; @@ -3837,10 +3832,8 @@ static int mlx5_esw_host_number_init(struct mlx5_esw= itch *esw) return PTR_ERR(query_host_out); =20 /* Mark non local controller with non zero controller number. */ - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, - query_host_out, net_function_params); - esw->offloads.host_number =3D MLX5_GET(host_params_context, - host_params, host_number); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + esw->offloads.host_number =3D host_pf_info.host_number; kvfree(query_host_out); return 0; } @@ -4980,9 +4973,8 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); + struct mlx5_esw_pf_info host_pf_info; const u32 *query_out; - void *host_params; - bool pf_disabled; =20 if (vport->vport !=3D MLX5_VPORT_HOST_PF) { NL_SET_ERR_MSG_MOD(extack, "State get is not supported for VF"); @@ -4996,13 +4988,11 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlin= k_port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, query_out, - net_function_params); - pf_disabled =3D MLX5_GET(host_params_context, host_params, - host_pf_disabled); + host_pf_info =3D mlx5_esw_get_host_pf_info(query_out); =20 - *opstate =3D pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : - DEVLINK_PORT_FN_OPSTATE_ATTACHED; + *opstate =3D host_pf_info.pf_disabled ? + DEVLINK_PORT_FN_OPSTATE_DETACHED : + DEVLINK_PORT_FN_OPSTATE_ATTACHED; =20 kvfree(query_out); return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c b/drivers/net/= ethernet/mellanox/mlx5/core/sriov.c index 6eb6026eadd6..79f76c456d72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sriov.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sriov.c @@ -273,8 +273,8 @@ void mlx5_sriov_detach(struct mlx5_core_dev *dev) =20 static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) { + struct mlx5_esw_pf_info host_pf_info; u16 host_total_vfs; - void *host_params; const u32 *out; =20 if (mlx5_core_is_ecpf_esw_manager(dev)) { @@ -285,10 +285,8 @@ static u16 mlx5_get_max_vfs(struct mlx5_core_dev *dev) */ if (IS_ERR(out)) goto done; - host_params =3D MLX5_ADDR_OF(query_esw_functions_out, out, - net_function_params); - host_total_vfs =3D MLX5_GET(host_params_context, host_params, - host_total_vfs); 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Mon, 18 May 2026 00:15:05 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 2/8] net/mlx5: Use v1 response layout for query_esw_functions Date: Mon, 18 May 2026 10:13:50 +0300 Message-ID: <20260518071356.345723-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|DS5PPFC9877909A:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d249a17-381c-4e71-414d-08deb4ad3c1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|1800799024|376014|11063799003|22082099003|56012099003|18002099003|3023799003; X-Microsoft-Antispam-Message-Info: Dq2o6LiCDYnquVtKogOe/exd5crjkCgjZ6k0LyKS3MOQqdhmefUG20+mLxk5S9rB6kMawVfaGPhbDyyyinMM+omJDP4SCHtigNW05URQ94toVLJ+csniY4i4laTHvwOv77neH1+cpU7ZVUp+cqu/obTpGHufaKyTctxhyKrjFAa5AtrVXy31/hGG8Ll9oX1UDMAXQCMRfi0xlBDupV0IEcbvyHMNr6VIBq8z/u0dN/EgftrmLy4BzgDHwUsPhWXpEK0mq7jf6yaNNA+y8QOcODC7239Q5Lqe9lucgtwpSnUEgMmBcAVzGaj2wvnVDELKmsW1G7L3Gp3+yBvc+2HsEGomq76RfcX8PyRqzoZs/I7/MII7YSLdIB/B1hbqVlRYSaDNnaChOE0IA/kCUds/CVtLrtva9tcg+hRBFP6k2ec93LsdViuenogx3FwX5tNWuq/b/uSE6NDoGuMQfjWOK8AaF/bEx4Mvl68R7dL6JQpJ6Upgat28og8N4cEYVqi3/xJLcbarf/H/r+Nq6nGqRpj8b6PqXbFv1qKxOCqFUe0EIbKmT+sFpQcaGNRy6QgB4vRUhA7DCNcsDVr6L2429uCma/uQf0diGnaJ+10x01yl/kYxytp5VqwKGqVZlEhm8NqMALszAzgy+o9MYIAqJgKVBcsQZUmyiCL0wGqir1MetQdbEmHE+/Rpx0aQja3uSOQInynUVeo0Hut4W2dKGCCafUjweY8abMtdkfTAUOI= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(1800799024)(376014)(11063799003)(22082099003)(56012099003)(18002099003)(3023799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: As6DuOO62LI4k+YIdae2gvLnYlkJV/NXYVDNIEunyEPAx3hfkcmDfLkmFyvlLacU33P25mz448P5xs1gZXkQbZ+eFWhjm0B6btUF/LdT/JtqYnp9zal/wUgtLizdtmxfGFwu/c1H22IUBB/ci4GmfCUv+MpQxAPkRliSa8Q+pjT3ui/562LBKvkPtBBJpLg4HTYg4V4+bUQA7iwpLd3+2Mjf9jMqWI2AdgmsKwQiLO5vVTdkicqBZ31byAUpWsOqUxSz8/WNZPCDXR9Z6lIcf234TMVGErElO+JITe8Cc1wb64tUeCcpfIXePSfsVHMjnW1ve696tOK1XcevdcONlxvh6lB2pqgOGYlIAakVS3TgEaTqD2svyxr6CfpP4EXISy8AN/gONKOiq9XmwVJu82BLhr278cFl3AyFNHNfg1pofVnK985RAiyv0ZI+UDtf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:26.2458 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d249a17-381c-4e71-414d-08deb4ad3c1a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFC9877909A Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use the v1 response layout for the query_esw_functions command when supported by the device. When query_host_net_function_v1 capability is set, use MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1 to retrieve parameters for multiple network functions, allocating the output buffer according to query_host_net_function_num_max. Validate that firmware does not return more entries than the allocated buffer. The v1 layout reports vhca_state instead of the legacy host_pf_disabled bit. PFs transition through ALLOCATED, ACTIVE, and IN_USE states (they do not use TEARDOWN_REQUEST as SFs do). When the ECPF calls disable_hca, firmware resets the PF and moves it to ALLOCATED. When the ECPF calls enable_hca, the PF moves to ACTIVE, and once the PF driver enables it, it reaches IN_USE. The PF is only fully operational in IN_USE, so pf_disabled is derived as vhca_state !=3D IN_USE, equivalent to the legacy host_pf_disabled bit. The mlx5_esw_get_host_pf_info() helper abstracts parsing the command output in both legacy and new formats, so callers do not need to handle the different layouts. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 88 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 5 +- .../mellanox/mlx5/core/eswitch_offloads.c | 6 +- .../net/ethernet/mellanox/mlx5/core/sriov.c | 2 +- 4 files changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 861e79ddb489..8b62dde7eb70 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1063,11 +1063,28 @@ static int eswitch_vport_event(struct notifier_bloc= k *nb, */ const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) { - int outlen =3D MLX5_ST_SZ_BYTES(query_esw_functions_out); + bool net_func_v1 =3D MLX5_CAP_GEN(dev, query_host_net_function_v1); u32 in[MLX5_ST_SZ_DW(query_esw_functions_in)] =3D {}; + int alloc_entries; + int outlen; u32 *out; int err; =20 + if (net_func_v1) { + alloc_entries =3D MLX5_CAP_GEN(dev, + query_host_net_function_num_max); + alloc_entries =3D max(alloc_entries, 1); + MLX5_SET(query_esw_functions_in, in, op_mod, + MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1); + outlen =3D MLX5_BYTE_OFF(query_esw_functions_out, + net_function_params) + + alloc_entries * MLX5_UN_SZ_BYTES(net_function_params); + outlen =3D max_t(int, outlen, + MLX5_ST_SZ_BYTES(query_esw_functions_out)); + } else { + outlen =3D MLX5_ST_SZ_BYTES(query_esw_functions_out); + } + out =3D kvzalloc(outlen, GFP_KERNEL); if (!out) return ERR_PTR(-ENOMEM); @@ -1076,9 +1093,25 @@ const u32 *mlx5_esw_query_functions(struct mlx5_core= _dev *dev) MLX5_CMD_OP_QUERY_ESW_FUNCTIONS); =20 err =3D mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); - if (!err) - return out; + if (err) + goto free; + + if (net_func_v1) { + int num_entries; + + num_entries =3D MLX5_GET(query_esw_functions_out, out, + net_function_num); + if (num_entries > alloc_entries) { + mlx5_core_warn(dev, "Got %d entries, max expected %d\n", + num_entries, alloc_entries); + err =3D -EINVAL; + goto free; + } + } + + return out; =20 +free: kvfree(out); return ERR_PTR(err); } @@ -1100,12 +1133,55 @@ mlx5_esw_host_pf_from_host_params(const void *entry) }; } =20 -struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out) +static struct mlx5_esw_pf_info +mlx5_esw_host_pf_from_net_func_params(const u8 *entry, int num_entries) +{ + int i; + + for (i =3D 0; i < num_entries; i++) { + int pf_type, state; + + pf_type =3D MLX5_GET(network_function_params, entry, pci_pf_type); + if (pf_type !=3D MLX5_PCI_PF_TYPE_EXTERNAL_HOST_PF) { + entry +=3D MLX5_UN_SZ_BYTES(net_function_params); + continue; + } + + state =3D MLX5_GET(network_function_params, entry, vhca_state); + + return (struct mlx5_esw_pf_info) { + .pf_disabled =3D state !=3D MLX5_VHCA_STATE_IN_USE, + .num_of_vfs =3D MLX5_GET(network_function_params, + entry, pci_num_vfs), + .total_vfs =3D MLX5_GET(network_function_params, + entry, pci_total_vfs), + .host_number =3D MLX5_GET(network_function_params, + entry, host_number), + }; + } + + /* No external host PF entry found */ + return (struct mlx5_esw_pf_info) { + .pf_not_exist =3D true, + .pf_disabled =3D true, + }; +} + +struct mlx5_esw_pf_info +mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) { const void *entry; =20 entry =3D MLX5_ADDR_OF(query_esw_functions_out, out, net_function_params); =20 + if (MLX5_CAP_GEN(dev, query_host_net_function_v1)) { + int num_entries =3D MLX5_GET(query_esw_functions_out, out, + net_function_num); + + return mlx5_esw_host_pf_from_net_func_params(entry, + num_entries); + } + return mlx5_esw_host_pf_from_host_params(entry); } =20 @@ -1121,7 +1197,7 @@ static int mlx5_esw_host_functions_enabled_query(stru= ct mlx5_eswitch *esw) if (IS_ERR(query_host_out)) return PTR_ERR(query_host_out); =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); esw->esw_funcs.host_funcs_disabled =3D host_pf_info.pf_not_exist; =20 kvfree(query_host_out); @@ -1561,7 +1637,7 @@ mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *e= sw, int num_vfs) if (IS_ERR(out)) return; =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, out); esw->esw_funcs.num_vfs =3D host_pf_info.num_of_vfs; if (mlx5_core_ec_sriov_enabled(esw->dev)) esw->esw_funcs.num_ec_vfs =3D num_vfs; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index cfaae59a6e7c..a5f832ed2251 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -657,7 +657,8 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *de= v0, struct mlx5_core_dev *dev1); =20 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); -struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(const u32 *out); +struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *de= v, + const u32 *out); int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 @@ -986,7 +987,7 @@ static inline const u32 *mlx5_esw_query_functions(struc= t mlx5_core_dev *dev) } =20 static inline struct mlx5_esw_pf_info -mlx5_esw_get_host_pf_info(const u32 *out) +mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) { return (struct mlx5_esw_pf_info) {}; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 217c2fe6b690..acbc37b05308 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3716,7 +3716,7 @@ static void esw_vfs_changed_event_handler(struct mlx5= _eswitch *esw) if (IS_ERR(out)) return; =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, out); new_num_vfs =3D host_pf_info.num_of_vfs; =20 if (new_num_vfs =3D=3D esw->esw_funcs.num_vfs || host_pf_info.pf_disabled) @@ -3832,7 +3832,7 @@ static int mlx5_esw_host_number_init(struct mlx5_eswi= tch *esw) return PTR_ERR(query_host_out); =20 /* Mark non local controller with non zero controller number. */ - host_pf_info =3D mlx5_esw_get_host_pf_info(query_host_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(esw->dev, query_host_out); esw->offloads.host_number =3D host_pf_info.host_number; kvfree(query_host_out); return 0; @@ -4988,7 +4988,7 @@ int mlx5_devlink_pf_port_fn_state_get(struct devlink_= port *port, if (IS_ERR(query_out)) return PTR_ERR(query_out); =20 - host_pf_info =3D mlx5_esw_get_host_pf_info(query_out); + host_pf_info =3D mlx5_esw_get_host_pf_info(vport->dev, query_out); =20 *opstate =3D host_pf_info.pf_disabled ? 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 3/8] net/mlx5: Use mlx5_eswitch_is_vf_vport() for IPsec VF checks Date: Mon, 18 May 2026 10:13:51 +0300 Message-ID: <20260518071356.345723-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36E:EE_|MW4PR12MB5602:EE_ X-MS-Office365-Filtering-Correlation-Id: a8339bb8-05e8-496a-62ff-08deb4ad3bdb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|1800799024|82310400026|18002099003|22082099003|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: puuQal2tYK9s35Xp0ZiH4i9U6r97JjbtW3zaWiCY0E/l4XuYBkGh2ZIsChiiLMCICpggnWo3Xj4toOkBuoNwlfIHjQig+Jz/6UpjliX3Tjpa74jjJmp1gR2vC3vNeQnqTcQGmUL7gnA6spDj3MA9K/ZTwVFj9l4Z8ty97NJNii7aL9BgrTy/8f0QgCA04X38r+9YX1DsQ98hS1wu17MtpJb5aRFndYduW0+Gxg5/1r498OiL6vS2aHTTd2imck4arYrKwdkL7xQi2CfK/df1r02ZFLHC5rwP5SIwyYVoAZByEtiEVDMdW7eG8cMz98CIGVys/1TZxcxKHoQMtizL2aDkgN4wCWPwwAZjKQiH0XdYGlPEMa2wZ2ifEmIJ+++ZXNjg4nt/R0qD7MfY6MS9hzR7/LvJESdF3tNalJhkAAcmQ5+5YyolEgzDBkgWnjcXFYsEDq6VEWT5nZAIaBL6y84aDfK1DxSHvwJ2ILesip3KniROUeyyUlOJedg5PkzuJnvu4qpL5qsX8cGoJd7hK06f0p4LeOSbl/1jDM4aifFxeRTs3uJt518f8OZjiAm3HhVztG0Azy0a0yUoPIfbmf3B0PiQQ/jIb1JQCiMIPORLkFna4Ce7fEjQJndlnvHfNp6vzKgYeNIjIOZOaqzli8fayOv6mPabJQURDq0WcaVNwyvbSd/nRGBMzgSLQV+XT7+Bv8TKzOnaVAw36Q+bBocBfpZbRWW9Wi1PRCVs3EU= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(1800799024)(82310400026)(18002099003)(22082099003)(56012099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AP9axiEydR+c2w4W0fD4wKO2MLij82xtZ6lH+Ai0fZv5coIiTsqC7JFH7cPtIegcuzfPwfp05TT3kAJXsHoAtOeQSjBfA9ysKUGyQXf7Un+5FeXXwPKThPNHI9e0F33zGIxv5UowtBKzH8Idc8DdoDZi1bjxqPwwg3PW1TPbiOHP3adTnQYtSz6iO1fj3Ia7M72g4fFv+meeoJYA3YMOyfEeNyGnveo71//4PmiDCaUWToTsOJbRVAHgxIIxyZ+aUAztoXOZqae16LFeXQPEzdaxOyVATtS6fV0+Gep282Y+bQmIUrNBjD43XwdnfObSQtAtIsV1J43D4Y17bsoAy4znIaPt6gmaIGSnl2ujXcBAsDTXUEJKF6dMVZfciS2ncyz1KuDOCVsDH2Dofk+6iVKS1OVuK4mpwh3PscoiOxpt6YQ9FWVZemEBTWnVuHTZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:25.7770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8339bb8-05e8-496a-62ff-08deb4ad3bdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5602 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh IPsec eswitch offload operations and the enabled_ipsec_vf_count counter are intended for VF vports only. Replace the MLX5_VPORT_HOST_PF checks with mlx5_eswitch_is_vf_vport() to properly identify VF vports, as preparation for adding another type of PF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c b/drivers/= net/ethernet/mellanox/mlx5/core/esw/ipsec.c index 4811b60ea430..b830ccd91e62 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c @@ -209,7 +209,7 @@ static int esw_ipsec_vf_offload_set_bytype(struct mlx5_= eswitch *esw, struct mlx5 struct mlx5_core_dev *dev =3D esw->dev; int err; =20 - if (vport->vport =3D=3D MLX5_VPORT_HOST_PF) + if (!mlx5_eswitch_is_vf_vport(esw, vport->vport)) return -EOPNOTSUPP; =20 if (type =3D=3D MLX5_ESW_VPORT_IPSEC_CRYPTO_OFFLOAD) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 8b62dde7eb70..9a7de7c9a667 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -958,7 +958,7 @@ int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, str= uct mlx5_vport *vport, /* Sync with current vport context */ vport->enabled_events =3D enabled_events; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 4/8] net/mlx5: Switch vport HCA cap helpers to kvzalloc Date: Mon, 18 May 2026 10:13:52 +0300 Message-ID: <20260518071356.345723-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B373:EE_|CY8PR12MB7363:EE_ X-MS-Office365-Filtering-Correlation-Id: f0dc51c7-a728-4ecb-0b77-08deb4ad3e8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700016|1800799024|56012099003|11063799003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: Bo/H3lW+hg2ey5n+kuAHcyg0VNh9HGvlzpRX5vOdJdTQepNpjBufk02JOIDpEgmZsXcwFQLLTvS+SnY5+6tGIeF0bxSAg8ONAnsU1LBYVu93U6pOjDmnSRR/dAhz2dbCZsNqQszfWFxG/dhVxQ3xFjfWxdezOJkIeMxhtXDmTKybaI2vge7tNZ9pnNTKAFpKYs1Ug653TeKoOAtRKzTrjOBiCEnghGPJOR61EkCiRqYqEtQVhaPbPL9V8mQwGgnr2mMS0cs0OO8WiLAvB1pF4n6LddSo3zaaAeXo0srKjaMeTU633okIg0NqicXisaFzFaQIz3V+K5RKDl7PTG75kQnDky/mM3XLXaZyCOASQpOgIMOXjxUjZTdtvo3a1ky7cKiEiEWKUxRPMQIbu3BsgBBy7XG4k4g4UiQbJp3smhqRWPLaMBA5YmvsMGdGZevNINnAMedePj2oZjFxHjrTRI1IxMf3kjtKMD5uP7I3I6ZActozteIGlhDH0gPqi/l6dDryCdrzfP8j88b0EIZpyKWvuGKj8G+pLkBFezjHVSVQyswRoCSmsGNhjTkiCz3tehVds9uAwaD7RWDHu2g6Dsy8S2YMX4uavTnuFiE1uMIVVBIO07Yb1gmJ2UJAAGi+cvWoP3ftzY+9cGy9CHi9fdJ6CkconSiKffGmQoPYlBik3MhPIBLKud1qjicsMnYA2qgiB/qXQt/ZBNTKSgaR9ZAykgsRzEBRrM1UcEphlEc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700016)(1800799024)(56012099003)(11063799003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: H92rQlT2KEltwA/QvBzVSpDEojJ+IVLBnDrSRHY+ps1gr28qhACVDKV3kQmZh2Ujp/2qiMfaF3HW9aM7BxhNpD8t2RiuwEwlFmaRPdkNkcaEGYzhOkPcV/fcTCqUvtoAPQl7EDgFbzyTF51LpanZ7n99fmE273ORKIh4JXqW2yQUUAqwhc+n07CI83hr5ao143Tk3oo+nFF741S0OnABsnAqYljWjY2TRR3rhAgVVCbq5K0q+r5vvl/dcHAVBex5r5cFm5Xqg2jNlNdHnR7Pg2A/s85wNf9Sr6VRKWIeA/brxOmuq9mDGRviBP00hz4aTb3sHkDaRCthF3p+dh/zL6blMkPbSEutUi8732vsCg9xO2JvrIhMK4c38vSOXBjvFyCEX/aAAdBsjyHKPZjL5BhOR7YuR1RfkRr5Xm98lgCcFgQprTzJ1epNxc7SKF1B X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:30.3042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0dc51c7-a728-4ecb-0b77-08deb4ad3e8f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B373.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7363 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh mlx5_vport_set_other_func_cap() and mlx5_vport_get_vhca_id() allocate command buffers that embed the HCA capability union, exceeding 4KiB. Use kvzalloc/kvfree so the allocation can fall back to vmalloc when contiguous memory is scarce. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/vport.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index 4effe37fd455..f8e6b1ab7c5c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1336,7 +1336,7 @@ int mlx5_vport_get_vhca_id(struct mlx5_core_dev *dev,= u16 vport, u16 *vhca_id) if (mlx5_esw_vport_vhca_id(dev->priv.eswitch, vport, vhca_id)) return 0; =20 - query_ctx =3D kzalloc(query_out_sz, GFP_KERNEL); + query_ctx =3D kvzalloc(query_out_sz, GFP_KERNEL); if (!query_ctx) return -ENOMEM; =20 @@ -1348,7 +1348,7 @@ int mlx5_vport_get_vhca_id(struct mlx5_core_dev *dev,= u16 vport, u16 *vhca_id) *vhca_id =3D MLX5_GET(cmd_hca_cap, hca_caps, vhca_id); =20 out_free: - kfree(query_ctx); + kvfree(query_ctx); return err; } EXPORT_SYMBOL_GPL(mlx5_vport_get_vhca_id); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 5/8] net/mlx5: Add mlx5_vport_set_other_func_general_cap macro Date: Mon, 18 May 2026 10:13:53 +0300 Message-ID: <20260518071356.345723-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36E:EE_|CY5PR12MB6381:EE_ X-MS-Office365-Filtering-Correlation-Id: f280ef1e-e0ec-4283-df74-08deb4ad4168 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|56012099003|22082099003|18002099003|11063799003; X-Microsoft-Antispam-Message-Info: 5CaToMrto6DPIu22Gbkchzkf3OQ/feZ2bYMM9RUM3ZTz11MH6kl0cNiGhhkV1oeRLnwar0xUaAOAs/PrSBInzZmjNCznN3ml45YoFp/u0Xpqw7fVv+Mk00e7PMYKOg+j9iLPAOYw/lCTcvg5gderA5Z0G0lqP+SZn/8i7xEt0bJNnebulmr1CcQXKNR9oHyYq+rgfYAXcOIcepF9EYmBVyVqvvfDUqD31GLgwsRnoFL2LWRsDKGnUM3wu3LB6BGVvc2GJzWw5p999NpCm724R1OuSV7ZeMVxXH6xSb1FI81VYViAerM2leyjtwlMCCbB1kdTz3YoDMHytymbzScO2dB0YzylFNpDZTvLOlFAIXp93MTqknLsWWoHmFM3jqjuCOQ2pJCbN5nefkub681QH3UnoBT72126n65o26A9F5Xcva799aWCUtyAPjFcAaoUw4fBHoTWMXEnhhQL/r0Mtkf3WiXsvo89QM6a8ZhB22FeXmuEZeV/XuOTdD5tVbADRGhF3Zp1MSv5zMnMBD2/7psL3aKkSkQO8YFK9r6BbFmYoQb+0UkGAWHXHntpAcb1fGCK4P7Tc30dxRy9DA4FIwEUXSiTp86TQizP0Il4f89/45OpRkNLUQpssTXwF9ACkuzFztiUG20M3ipKP7XBMp3MQ+tDK46mo1/RF6qWdeIVZ9S/5A5QmWf78vjzWfWjVFUI0fAakuP4xLtelbIEadh+5DVMuL9irYvO1dpOxYY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(56012099003)(22082099003)(18002099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Tqb5l355O6VuQLVpnQgjETat4ZKoSdW+YQR1KYpJB6Gdq1lddiRzT4V8S4BDaLr4CahPrvw0f/H1N6C6mjNcX1T+BD1KIu7/XmRK89JcuLKOEHGQdivp0JVUVNuwFBq1JBViV/M1XrcDC6EedfwqQiKHmuCzSPRpIT8u6++h/h+0swEEmn8A3NieDguZTO0kyNCvUvsHQoah96hTvPHa05WqfL0M42VOID1eWt3XzPDtY9hlGpCf8peVC58GSr/DwCXYVyHvKiThup1JBt+08j8HfdR0nyvGGdYtImoqog/jWjCv2fT/ze0NUO0oAsJNT3pxrvIuqm39NtGKqLSmYTD+2kTqRTUhPgJnBQHR5RKY08r3yeb32hP4YMypPSlzQxaGC1Us9lechBoPkcNR566DsIVe+cv/9fk+KqxmZud60fsg6z26YV0nprDykXea X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:35.0681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f280ef1e-e0ec-4283-df74-08deb4ad4168 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6381 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add mlx5_vport_set_other_func_general_cap() convenience macro, symmetric to the existing mlx5_vport_get_other_func_general_cap(), and use it in mlx5_devlink_port_fn_roce_set(). No functional change in this patch. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index acbc37b05308..b06b10d443bd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4951,8 +4951,8 @@ int mlx5_devlink_port_fn_roce_set(struct devlink_port= *port, bool enable, hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); MLX5_SET(cmd_hca_cap, hca_caps, roce, enable); =20 - err =3D mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); + err =3D mlx5_vport_set_other_func_general_cap(esw->dev, hca_caps, + vport_num); if (err) { NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap"); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 6/8] net/mlx5: Refactor mlx5_set_msix_vec_count() SET_HCA_CAP Date: Mon, 18 May 2026 10:13:54 +0300 Message-ID: <20260518071356.345723-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B373:EE_|CY3PR12MB9679:EE_ X-MS-Office365-Filtering-Correlation-Id: 88c4b4a0-cbce-4c94-efa3-08deb4ad44c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|56012099003|18002099003|22082099003|11063799003; X-Microsoft-Antispam-Message-Info: 18k/7Ek5Lle1IrIuXEFITxmUJeSzcQHvJI2G5E2HxM9Pca5O64n8djBc1qNLEAYjsp6YGhmC7aovSrEeBbt5hemJjQ6lnjaoPcBmLsq7wzfjrV+cZbTIDZCefRi8BGsjLn9quIntH1AlS3tccuyWX2DslCM7PzPmhjs0fF47WfAeUrnxFxuedeQWiSSpzRjAOK32sd6WTZTGaBJimPx8TRG+gNM/yDMsuW2ISxmFTkk4mubJnkLWNrs+dSiRfV4rtmUK/AK6PGkcoiGQYBT0ycAY5F1BEdgUdYcr4lXw7e+wWcxFXu46VqZF0kTjxLiGjzM+uqOBSl/LpIeBiPKvLVBrcYlOdqfnzqQJLwsJVTE1IJhPQ0H/uzIeg5/g+ttcoywqtZLu7QGaX7B6M/Fc+1/HJ0FRcLRcroGCFNmqU+LLMt4t41MOCxT+VB/dqnXBiNfV3CyGM9s/IA98WHr2iIaIakfAvhnoKvncP1xmcHu2Kmt1oAC9IiMBEHCvDhF04CnluZ+IQ/lqL99i7sVlghxaTsLPZU3vk2I6mF2GibHLSzJxudlzrjmE29aTzmh270DCSIbtA82SIIBcKg9fVg85CtLnx3FK4lZzj8D9i60BaXOAbxgNmGoIYz6GFnYAl2op9hYGJLUJE/SQ/mx6x32WGm4lNpxNImfn3zqpaACjPI2q+2KJlMR3OgpnGPeJUBSU3B7+Ri3gt9lRAZrMOVtClrMjLvqE4AziXhKF85Q= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mtkRdYfMP8g3ePVxR5lztx6vSL3cqK9x/uYcOo0go3Pk+B4ABsgzgJfR2xWmMyTuefPmw41QvigbcWSUBy8JySupypmhOT1f7sMhzXdpF4QveAvtG41NfHwMV6EzE1pgQzmqOrFPm5+gGvfiVZOaQWfwN+3hOxTxI5JfACpSoAa2JZ8pemnJkr6J5ux9ENtQdXdwa545tpYuyybhaA6DOoMPN4gE53w8SexoIQVqR5ON9EtTMwfKVgOd6iPKRvhH5ppTAJzcELj9kQYOWbyHoD+vTUKdGSNlj7b14L8Ju9jDZ5cv4wtWFQA8CkdeyH6g6415Lfr39X8B+PB64wWwli4vSR+NN4j2t11o+Rjg6EP/bWqwChAk1TA6VlL9gJkqWVotwFzH1HhPp/0YlnYCfjeJymFIblCwOL1Feoa0uuFhxZSmO+PPNYkx0rOxnkoj X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:40.7035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88c4b4a0-cbce-4c94-efa3-08deb4ad44c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B373.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9679 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use mlx5_vport_set_other_func_general_cap() instead of open-coding the SET_HCA_CAP command. This removes redundant buffer allocation and ensures consistent use of vport-based function addressing. mlx5_vport_set_other_func_general_cap() supports both function_id and vhca_id based addressing, so this also enables SET_HCA_CAP for vhca_id indexed functions which was not supported before. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 27 +++++-------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/pci_irq.c index e051b9a939ee..0f5b8bc7861e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -87,9 +87,8 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, in= t function_id, int msix_vec_count) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap =3D NULL, *query_cap =3D NULL, *cap; int num_vf_msix, min_msix, max_msix; + void *query_cap, *hca_caps; bool ec_vf_function; int vport; int ret; @@ -111,11 +110,8 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev,= int function_id, return -EOVERFLOW; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto out; - } + if (!query_cap) + return -ENOMEM; =20 ec_vf_function =3D mlx5_core_ec_sriov_enabled(dev); vport =3D mlx5_core_func_to_vport(dev, function_id, ec_vf_function); @@ -123,21 +119,12 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev= , int function_id, if (ret) goto out; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(cmd_hca_cap, cap, dynamic_msix_table_size, msix_vec_count); - - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, ec_vf_function, ec_vf_function); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, function_id); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); + MLX5_SET(cmd_hca_cap, hca_caps, dynamic_msix_table_size, + msix_vec_count); =20 - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 7/8] net/mlx5: Use vport helper for IPsec eswitch set caps Date: Mon, 18 May 2026 10:13:55 +0300 Message-ID: <20260518071356.345723-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|LV3PR12MB9214:EE_ X-MS-Office365-Filtering-Correlation-Id: 36feebdf-eb15-4b97-020e-08deb4ad47c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|1800799024|82310400026|22082099003|18002099003|56012099003|3023799003|11063799003; X-Microsoft-Antispam-Message-Info: PZXT0cSiiFnSTx14Tgnj7VXMFCOJn7ZB3fSVsfq4xCcwDFVDdj/JX20iT353GTCOoTt/U6A8iXMlnxkW7zLd2a2yy6LxMZX+XV4no57148VVRG0q0txyTrPNCYJHvm8ea/a7ZxYLpx96LfG3o05qJqh5ZheMyhOL4Kev/lILzAPnUbLSLY6o9+jOgB8lT9YoG0QO9vRtmrm2pggJXptfucvmnBAE1Z4RkOXsJvlxdJ6puNs1WXIMtkoAvI3j+klVrUriUuErVUkxLQ0qThFo73/KEA75MtR3BK1a4n5RcaUpD50o4Np7q7ee+vpe7ztyt1cYjUWgyCYX9xYFi5WNX1q4Qet2+mqYQFBLw/P5N+j//4oNx3cOcpMpJxhc4VDOneVbK+gHkNMVddle4/rVA71T0ylZeHbiUSMSbCpTckWhzLOGlVWLyiIEywxGrpjuPoV+MscZxX0mzJMAK7C2yqVAI4+jjca9N97SKeh0AQZG5/aNfD6mKOqdnweh5KEWd7iBSv+N8wYdSynDLEM722TDgTMpeK8gNQeH4mszXTvBnl/5rB74nMmVB+0eFgIAxdyq065bsb9lkXVIR0/0aAkcj8bpo0XeJ9Hf+p1uT05X5qFZikQfKPF+uNZ5Jcy52fINmiJjKxOqgGcgahTptvhnszOBXIySY+tP5wqNauhEGXfoZ//mVidzFlMo5QnNE/9cnRlV8nNCOdvJrG4G9JVVCleqqHY/tETe76nBvxc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(1800799024)(82310400026)(22082099003)(18002099003)(56012099003)(3023799003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fdGIyNjB9mzw9LVW+zE/HuvkVwWfCmQof7AEcj1dbiMDTBfV3U4nMSI/kwjU9G5TUGj1ryf4wY0xuK0aEo66d1t67DqITg8g4V/pKGg0nOf0Y1/lp+cWXHZJerO1/NSZZg21/mnk+U2vgFWOHGHXD0jxY06shB7DoambZEm0F3pRrSibrc843qbXcyNMfQ3EOJl68KFG9maBzpaY1d8qMYDiVEfXKbC2/7UQSKwz3tvvLS44AIJh+P/FmaShf4PqlZ+EBy8SQrCa/fZnHX6wvEstA14fG9nQJYZ92NROX8BdMxf/52AkzHtZoQcm8RdmcbtL8k+JBB5rcdLCAcENH3fQRKofj/aZwnT8Q1435Y98EOfyaSewnTNsvrEJ+/dpDM4/FGinLUGcU1uArDla3f6XuvwJzVSPDMc16Ki6hexeu81jJ1rF769vXIXrRTZi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:45.7389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36feebdf-eb15-4b97-020e-08deb4ad47c0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9214 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Use mlx5_vport_set_other_func_cap() and mlx5_vport_set_other_func_general_cap() in the IPsec eswitch functions instead of open-coding the SET_HCA_CAP command. This removes redundant buffer allocation and boilerplate, and also enables vhca_id based addressing when supported. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/esw/ipsec.c | 81 ++++++------------- 1 file changed, 23 insertions(+), 58 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c b/drivers/= net/ethernet/mellanox/mlx5/core/esw/ipsec.c index b830ccd91e62..2b5765ab60d1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec.c @@ -81,38 +81,25 @@ int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev = *dev, struct mlx5_vport * static int esw_ipsec_vf_set_generic(struct mlx5_core_dev *dev, u16 vport_n= um, bool ipsec_ofld) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 if (!MLX5_CAP_GEN(dev, vhca_resource_manager)) return -EOPNOTSUPP; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_general_cap(dev, vport_num, query_cap); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(cmd_hca_cap, cap, ipsec_offload, ipsec_ofld); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); + MLX5_SET(cmd_hca_cap, hca_caps, ipsec_offload, ipsec_ofld); =20 - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport_num); - - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1); - ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap); + ret =3D mlx5_vport_set_other_func_general_cap(dev, hca_caps, vport_num); free: - kvfree(hca_cap); kvfree(query_cap); return ret; } @@ -121,49 +108,37 @@ static int esw_ipsec_vf_set_bytype(struct mlx5_core_d= ev *dev, struct mlx5_vport bool enable, enum esw_vport_ipsec_offload type) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 if (!MLX5_CAP_GEN(dev, vhca_resource_manager)) return -EOPNOTSUPP; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_cap(dev, vport->vport, query_cap, MLX5_= CAP_IPSEC); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); + hca_caps =3D MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability); =20 switch (type) { case MLX5_ESW_VPORT_IPSEC_CRYPTO_OFFLOAD: - MLX5_SET(ipsec_cap, cap, ipsec_crypto_offload, enable); + MLX5_SET(ipsec_cap, hca_caps, ipsec_crypto_offload, enable); break; case MLX5_ESW_VPORT_IPSEC_PACKET_OFFLOAD: - MLX5_SET(ipsec_cap, cap, ipsec_full_offload, enable); + MLX5_SET(ipsec_cap, hca_caps, ipsec_full_offload, enable); break; default: ret =3D -EOPNOTSUPP; goto free; } =20 - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport->vport); - - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_IPSEC << 1); - ret =3D mlx5_cmd_exec_in(dev, set_hca_cap, hca_cap); + ret =3D mlx5_vport_set_other_func_cap(dev, hca_caps, vport->vport, + MLX5_SET_HCA_CAP_OP_MOD_IPSEC); free: - kvfree(hca_cap); kvfree(query_cap); return ret; } @@ -171,34 +146,24 @@ static int esw_ipsec_vf_set_bytype(struct mlx5_core_d= ev *dev, struct mlx5_vport static int esw_ipsec_vf_crypto_aux_caps_set(struct mlx5_core_dev *dev, u16= vport_num, bool enable) { int query_sz =3D MLX5_ST_SZ_BYTES(query_hca_cap_out); - int set_sz =3D MLX5_ST_SZ_BYTES(set_hca_cap_in); - struct mlx5_eswitch *esw =3D dev->priv.eswitch; - void *hca_cap, *query_cap, *cap; + void *query_cap, *hca_caps; int ret; =20 query_cap =3D kvzalloc(query_sz, GFP_KERNEL); - hca_cap =3D kvzalloc(set_sz, GFP_KERNEL); - if (!hca_cap || !query_cap) { - ret =3D -ENOMEM; - goto free; - } + if (!query_cap) + return -ENOMEM; =20 ret =3D mlx5_vport_get_other_func_cap(dev, vport_num, query_cap, MLX5_CAP= _ETHERNET_OFFLOADS); if (ret) goto free; =20 - cap =3D MLX5_ADDR_OF(set_hca_cap_in, hca_cap, capability); - memcpy(cap, MLX5_ADDR_OF(query_hca_cap_out, query_cap, capability), - MLX5_UN_SZ_BYTES(hca_cap_union)); - MLX5_SET(per_protocol_networking_offload_caps, cap, insert_trailer, enabl= e); - MLX5_SET(set_hca_cap_in, hca_cap, opcode, MLX5_CMD_OP_SET_HCA_CAP); - MLX5_SET(set_hca_cap_in, hca_cap, other_function, 1); - MLX5_SET(set_hca_cap_in, hca_cap, function_id, vport_num); - MLX5_SET(set_hca_cap_in, hca_cap, op_mod, - MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS << 1); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Moshe Shemesh" , Akiva Goldberger , , , , Gal Pressman , Dragos Tatulea , Simon Horman Subject: [PATCH net-next V2 8/8] net/mlx5: Generalize enable/disable HCA for any PF vport Date: Mon, 18 May 2026 10:13:56 +0300 Message-ID: <20260518071356.345723-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260518071356.345723-1-tariqt@nvidia.com> References: <20260518071356.345723-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|LV3PR12MB9331:EE_ X-MS-Office365-Filtering-Correlation-Id: a4f78031-10b5-41dd-52e8-08deb4ad4c44 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700016|7416014|56012099003|22082099003|18002099003|11063799003; X-Microsoft-Antispam-Message-Info: PmRRD8+Q6KAQDO11s74b8hCSS6yUKCoWwQP4JunIBQAQmVfFGpziEf0ROjxnpklAqsmcJH2wYHFUUlN6S/UKBpaT9ua4yhdYLRNXplGkNC4mM2kX2IPSbq0pTQBuznYDp64jNhCWAMS1dlxY4xjjCA9M3CjPY8oaOJja9XA/Gy0ZCoewRL9nGUmevrK7ozYFL0wgSmHtu1CiEpXlLDPSCJlrZ0I/fkUPCBRrIEmJQ0YuqoIYl5646O5vtDr4lnPwkn3UwWzCPWtMWNQDXZ+aupmXCryeFDTTtL2OsBlBDOgmFGMJ2WnfSgUkETeZamC95QTrcYKrYVaWEmt66LSSmbnXQM5ok5gbkBL5IHWn/8HPbG5aBP1PToAkjHqzvWU1RuBMVYlObzXr8AkRBDdAaFrV7AGMvxnV0sO/pDhwopbqxyAWV760tYUwiJYYNxiiUs8UoGiL/FiLdf6SdniABsH+5DvqOIDVhYdjJ/J/P8kDbfIcAvt8XRq1Az1RpYeXxzaQKI8h0XfbKbBzznaxFaInhxx7YUhddqDGtd5c/kbvRd+ktKVEMVLb7mWRe9NTId5zbV3b9HY4jLVYzp6IIqSRZ5RGmGH5/GxwF+PABPiClmG2I65dG7oFeObYy2j4bY4AzVVZSiJUYuGiLSVUE2NjuqU6EdDZc4iY4PaT0pguNW0S55TMtGWzPmQLQVSS2HGHQWriegTaaVRlDywPAh7AogT2zXNG9FYXvSLo974= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700016)(7416014)(56012099003)(22082099003)(18002099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OYqzEoEITqGiGYk6iti5epi2l1S7WiJE0HMwvcqJzPz3lI2RNONKZKlwTRon1Qntz1thtGQvo36oHc6qwJJSd6tphY3ud0QhZjt7ExyOgDkjdQddrnYJV5IEa3xnIiwI+orP0RfPSfYgrsadMWkkKCiOT3F6mjXhh1BFlgrarvE8S0oFdRsyr1iChEctWijQ/sSIJ0/igIHE8xsUD/cE4mjW7zB9+EeRUnlwltg0T338o44z37IVBdyi4E1cWkBBiXJM0bWTj502BOOi9SY3VFbv4W5cGp5LUJSxpUlioN/uIkETk0qe6d0eGjbYqlWjRAdo4GKg88rtsQ3uuAYK1U1z2bHshmj+4povcPAa06Z48Kn7dL5FWEHSLTpcoW0owN9nYEP6FHHXxPWmpgCz5QprmTUudGLI8TRUF083mw+h4KQLlLJ10L+WeIRjrCtM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 07:15:53.3636 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4f78031-10b5-41dd-52e8-08deb4ad4c44 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9331 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Refactor the host-PF-specific mlx5_cmd_host_pf_enable/disable_hca() into generic mlx5_cmd_pf_enable/disable_hca() that accept a vport number. The new functions use vhca_id as function_id when supported. Similarly, refactor the eswitch layer into generic static helpers mlx5_esw_pf_enable/disable_hca() with thin wrappers for the host PF case, in preparation for enable_hca on satellite PF vports. Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/ecpf.c | 24 +++++++++++----- .../net/ethernet/mellanox/mlx5/core/ecpf.h | 4 +-- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 28 +++++++++++++------ .../ethernet/mellanox/mlx5/core/mlx5_core.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/vport.c | 4 +-- 5 files changed, 42 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.c index 15cb27aea2c9..350c47d3643b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c @@ -18,25 +18,35 @@ static bool mlx5_ecpf_esw_admins_host_pf(const struct m= lx5_core_dev *dev) return mlx5_core_is_ecpf_esw_manager(dev); } =20 -int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev) +int mlx5_cmd_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) { u32 out[MLX5_ST_SZ_DW(enable_hca_out)] =3D {}; u32 in[MLX5_ST_SZ_DW(enable_hca_in)] =3D {}; + u16 vhca_id; =20 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); - MLX5_SET(enable_hca_in, in, function_id, 0); - MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0); - return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); + if (mlx5_vport_use_vhca_id_as_func_id(dev, vport_num, &vhca_id)) { + MLX5_SET(enable_hca_in, in, function_id, vhca_id); + MLX5_SET(enable_hca_in, in, function_id_type, 1); + } else { + MLX5_SET(enable_hca_in, in, function_id, vport_num); + } + return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 -int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev) +int mlx5_cmd_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num) { u32 out[MLX5_ST_SZ_DW(disable_hca_out)] =3D {}; u32 in[MLX5_ST_SZ_DW(disable_hca_in)] =3D {}; + u16 vhca_id; =20 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); - MLX5_SET(disable_hca_in, in, function_id, 0); - MLX5_SET(disable_hca_in, in, embedded_cpu_function, 0); + if (mlx5_vport_use_vhca_id_as_func_id(dev, vport_num, &vhca_id)) { + MLX5_SET(disable_hca_in, in, function_id, vhca_id); + MLX5_SET(disable_hca_in, in, function_id_type, 1); + } else { + MLX5_SET(disable_hca_in, in, function_id, vport_num); + } return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.h index 40b6ad76dca6..d9f9a53b019b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.h @@ -17,8 +17,8 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev); int mlx5_ec_init(struct mlx5_core_dev *dev); void mlx5_ec_cleanup(struct mlx5_core_dev *dev); =20 -int mlx5_cmd_host_pf_enable_hca(struct mlx5_core_dev *dev); -int mlx5_cmd_host_pf_disable_hca(struct mlx5_core_dev *dev); +int mlx5_cmd_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num); +int mlx5_cmd_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num); =20 #else /* CONFIG_MLX5_ESWITCH */ =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 9a7de7c9a667..206911817a04 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1452,7 +1452,7 @@ static int mlx5_eswitch_load_ec_vf_vports(struct mlx5= _eswitch *esw, u16 num_ec_v return err; } =20 -int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev) +static int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; @@ -1461,15 +1461,15 @@ int mlx5_esw_host_pf_enable_hca(struct mlx5_core_de= v *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); + vport =3D mlx5_eswitch_get_vport(esw, vport_num); if (IS_ERR(vport)) return PTR_ERR(vport); =20 - /* Once vport and representor are ready, take out the external host PF - * out of initializing state. Enabling HCA clears the iser->initializing - * bit and host PF driver loading can progress. + /* Once vport and representor are ready, take the PF out of + * initializing state. Enabling HCA clears the iser->initializing + * bit and PF driver loading can progress. */ - err =3D mlx5_cmd_host_pf_enable_hca(dev); + err =3D mlx5_cmd_pf_enable_hca(dev, vport_num); if (err) return err; =20 @@ -1478,7 +1478,7 @@ int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev = *dev) return 0; } =20 -int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev) +static int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_nu= m) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; struct mlx5_vport *vport; @@ -1487,11 +1487,11 @@ int mlx5_esw_host_pf_disable_hca(struct mlx5_core_d= ev *dev) if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 - vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_HOST_PF); + vport =3D mlx5_eswitch_get_vport(esw, vport_num); if (IS_ERR(vport)) return PTR_ERR(vport); =20 - err =3D mlx5_cmd_host_pf_disable_hca(dev); + err =3D mlx5_cmd_pf_disable_hca(dev, vport_num); if (err) return err; =20 @@ -1500,6 +1500,16 @@ int mlx5_esw_host_pf_disable_hca(struct mlx5_core_de= v *dev) return 0; } =20 +int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev) +{ + return mlx5_esw_pf_enable_hca(dev, MLX5_VPORT_HOST_PF); +} + +int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev) +{ + return mlx5_esw_pf_disable_hca(dev, MLX5_VPORT_HOST_PF); +} + /* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs * whichever are present on the eswitch. */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index 2eba141bd521..51637e58a48b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -452,6 +452,8 @@ void mlx5_unload_one_light(struct mlx5_core_dev *dev); =20 void mlx5_query_nic_sw_system_image_guid(struct mlx5_core_dev *mdev, u8 *b= uf, u8 *len); +bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, + u16 vport_num, u16 *vhca_id); int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *h= ca_cap, u16 vport, u16 opmod); #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index f8e6b1ab7c5c..e0848f4e88dd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1283,8 +1283,8 @@ void mlx5_query_nic_sw_system_image_guid(struct mlx5_= core_dev *mdev, u8 *buf, buf[(*len)++] =3D MLX5_CAP_GEN_2(mdev, load_balance_id); } =20 -static bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, - u16 vport_num, u16 *vhca_id) +bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, + u16 vport_num, u16 *vhca_id) { if (!MLX5_CAP_GEN_2(dev, function_id_type_vhca_id)) return false; --=20 2.44.0