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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-369c5f0eb2bsm2058381a91.7.2026.05.17.23.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 23:59:37 -0700 (PDT) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Cc: Himanshu Chauhan Subject: [PATCH v4 1/2] riscv: Introduce support for hardware break/watchpoints Date: Mon, 18 May 2026 12:29:18 +0530 Message-ID: <20260518065920.872131-2-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> References: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE4MDA2NCBTYWx0ZWRfXxrGIhQLRIILJ KPzc9LldqXD31htEokhA5AebQP85KYrt/QTJPJOxUws052oZZOjxPDRNn8KTbWeZtDwlMZDe5nT SlfPHKoWvkK4W8FMn5FNgZww+BvLO1lIRj3F7J1gLDicT4cBSqtuK/Owc2ueXbXZMsMCGDWmoc5 YvMtxHh5tf+I515YdcljJ/b4XBC9kvQAwgeMoVAYegHdQ4wIJz4hDjoRD18CnrAj6IsbY4AyeuZ 1pZUqxUHGoKmZ9MGJsn6ao1k3UMAha7aJwG2ZwkX4EQGIzT2p/jl+ZHpYbdbxBDytbmqP7SZ9g5 xCy7QLcQG+cbPjsEsZJJ/LLa47l+yLPLadoAeae7zVGz1WFvIufUh/hntTe/CdvkjZ06MNbAaEY HM2/ERYJEEW4wT7f0CWevq2gF03qBdBGDuZB6Mm2xou8dUcenIjnLp9OyivswUtwdCk2Sn1ZrY4 bA034RLGElkk6ydU70g== X-Authority-Analysis: v=2.4 cv=Bq+tB4X5 c=1 sm=1 tr=0 ts=6a0ab8db cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=z58f_zlqE1tZ07ItSJAA:9 a=O8hF6Hzn-FEA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: aL3pX0vZBzKHd_JjRfZ3eaAIe4WbVKvt X-Proofpoint-ORIG-GUID: aL3pX0vZBzKHd_JjRfZ3eaAIe4WbVKvt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-18_01,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605180064 Content-Type: text/plain; charset="utf-8" RISC-V hardware breakpoint framework is built on top of perf subsystem and uses SBI debug trigger extension to install/uninstall/update/enable/disable hardware triggers as specified in Sdtrig ISA extension. Signed-off-by: Himanshu Chauhan --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/hw_breakpoint.h | 332 +++++++++++ arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 736 +++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 6 + 6 files changed, 1078 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d235396c4514..ad09c2a7dc46 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -170,6 +170,7 @@ config RISCV select HAVE_FUNCTION_ERROR_INJECTION select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO if MMU + select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_IRQ_TIME_ACCOUNTING select HAVE_KERNEL_BZIP2 if !EFI_ZBOOT select HAVE_KERNEL_GZIP if !EFI_ZBOOT diff --git a/arch/riscv/include/asm/hw_breakpoint.h b/arch/riscv/include/as= m/hw_breakpoint.h new file mode 100644 index 000000000000..acf05641f3ab --- /dev/null +++ b/arch/riscv/include/asm/hw_breakpoint.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + */ + +#ifndef __RISCV_HW_BREAKPOINT_H +#define __RISCV_HW_BREAKPOINT_H + +struct task_struct; + +#ifdef CONFIG_HAVE_HW_BREAKPOINT + +#include + +/* Maximum number of hardware breakpoints supported */ +#define RISCV_HW_BP_NUM_MAX 32 + +#if __riscv_xlen =3D=3D 64 +#define cpu_to_le cpu_to_le64 +#define le_to_cpu le64_to_cpu +#elif __riscv_xlen =3D=3D 32 +#define cpu_to_le cpu_to_le32 +#define le_to_cpu le32_to_cpu +#else +#error "Unexpected __riscv_xlen" +#endif + +#define RISCV_DBTR_BIT(_prefix, _name) \ + RISCV_DBTR_##_prefix##_##_name##_BIT + +#define RISCV_DBTR_BIT_MASK(_prefix, _name) \ + RISCV_DBTR_##_prefix##_name##_BIT_MASK + +#define RISCV_DBTR_BIT_MASK_VAL(_prefix, _name, _width) \ + (((1UL << (_width)) - 1) << RISCV_DBTR_BIT(_prefix, _name)) + +#define CLEAR_DBTR_BIT(_target, _prefix, _bit_name) \ + __clear_bit(RISCV_DBTR_BIT(_prefix, _bit_name), &(_target)) + +#define SET_DBTR_BIT(_target, _prefix, _bit_name) \ + __set_bit(RISCV_DBTR_BIT(_prefix, _bit_name), &(_target)) + +#define RISCV_DBTR_EXEC (0x1UL << 0) +#define RISCV_DBTR_LOAD (0x1UL << 1) +#define RISCV_DBTR_STORE (0x1UL << 2) +#define RISCV_DBTR_LDST (RISCV_DBTR_LOAD | RISCV_DBTR_STORE) + +enum { + RISCV_DBTR_TRIG_NONE =3D 0, + RISCV_DBTR_TRIG_LEGACY, + RISCV_DBTR_TRIG_MCONTROL, + RISCV_DBTR_TRIG_ICOUNT, + RISCV_DBTR_TRIG_ITRIGGER, + RISCV_DBTR_TRIG_ETRIGGER, + RISCV_DBTR_TRIG_MCONTROL6, +}; + +/* Trigger Data 1 */ +enum { + RISCV_DBTR_BIT(TDATA1, DATA) =3D 0, +#if __riscv_xlen =3D=3D 64 + RISCV_DBTR_BIT(TDATA1, DMODE) =3D 59, + RISCV_DBTR_BIT(TDATA1, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RISCV_DBTR_BIT(TDATA1, DMODE) =3D 27, + RISCV_DBTR_BIT(TDATA1, TYPE) =3D 28, +#else + #error "Unknown __riscv_xlen" +#endif +}; + +enum { +#if __riscv_xlen =3D=3D 64 + RISCV_DBTR_BIT_MASK(TDATA1, DATA) =3D RISCV_DBTR_BIT_MASK_VAL(TDATA1, DAT= A, 59), +#elif __riscv_xlen =3D=3D 32 + RISCV_DBTR_BIT_MASK(TDATA1, DATA) =3D RISCV_DBTR_BIT_MASK_VAL(TDATA1, DAT= A, 27), +#else + #error "Unknown __riscv_xlen" +#endif + RISCV_DBTR_BIT_MASK(TDAT1, DMODE) =3D RISCV_DBTR_BIT_MASK_VAL(TDATA1, DMO= DE, 1), + RISCV_DBTR_BIT_MASK(TDATA1, TYPE) =3D RISCV_DBTR_BIT_MASK_VAL(TDATA1, TYP= E, 4), +}; + +/* MC - Match Control Type Register */ +enum { + RISCV_DBTR_BIT(MC, LOAD) =3D 0, + RISCV_DBTR_BIT(MC, STORE) =3D 1, + RISCV_DBTR_BIT(MC, EXEC) =3D 2, + RISCV_DBTR_BIT(MC, U) =3D 3, + RISCV_DBTR_BIT(MC, S) =3D 4, + RISCV_DBTR_BIT(MC, RES2) =3D 5, + RISCV_DBTR_BIT(MC, M) =3D 6, + RISCV_DBTR_BIT(MC, MATCH) =3D 7, + RISCV_DBTR_BIT(MC, CHAIN) =3D 11, + RISCV_DBTR_BIT(MC, ACTION) =3D 12, + RISCV_DBTR_BIT(MC, SIZELO) =3D 16, + RISCV_DBTR_BIT(MC, TIMING) =3D 18, + RISCV_DBTR_BIT(MC, SELECT) =3D 19, + RISCV_DBTR_BIT(MC, HIT) =3D 20, +#if __riscv_xlen >=3D 64 + RISCV_DBTR_BIT(MC, SIZEHI) =3D 21, +#endif +#if __riscv_xlen =3D=3D 64 + RISCV_DBTR_BIT(MC, MASKMAX) =3D 53, + RISCV_DBTR_BIT(MC, DMODE) =3D 59, + RISCV_DBTR_BIT(MC, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RISCV_DBTR_BIT(MC, MASKMAX) =3D 21, + RISCV_DBTR_BIT(MC, DMODE) =3D 27, + RISCV_DBTR_BIT(MC, TYPE) =3D 28, +#else + #error "Unknown riscv xlen" +#endif +}; + +enum { + RISCV_DBTR_BIT_MASK(MC, LOAD) =3D RISCV_DBTR_BIT_MASK_VAL(MC, LOAD, 1), + RISCV_DBTR_BIT_MASK(MC, STORE) =3D RISCV_DBTR_BIT_MASK_VAL(MC, STORE, 1), + RISCV_DBTR_BIT_MASK(MC, EXEC) =3D RISCV_DBTR_BIT_MASK_VAL(MC, EXEC, 1), + RISCV_DBTR_BIT_MASK(MC, U) =3D RISCV_DBTR_BIT_MASK_VAL(MC, U, 1), + RISCV_DBTR_BIT_MASK(MC, S) =3D RISCV_DBTR_BIT_MASK_VAL(MC, S, 1), + RISCV_DBTR_BIT_MASK(MC, RES2) =3D RISCV_DBTR_BIT_MASK_VAL(MC, RES2, 1), + RISCV_DBTR_BIT_MASK(MC, M) =3D RISCV_DBTR_BIT_MASK_VAL(MC, M, 1), + RISCV_DBTR_BIT_MASK(MC, MATCH) =3D RISCV_DBTR_BIT_MASK_VAL(MC, MATCH, 4), + RISCV_DBTR_BIT_MASK(MC, CHAIN) =3D RISCV_DBTR_BIT_MASK_VAL(MC, CHAIN, 1), + RISCV_DBTR_BIT_MASK(MC, ACTION) =3D RISCV_DBTR_BIT_MASK_VAL(MC, ACTION, 4= ), + RISCV_DBTR_BIT_MASK(MC, SIZELO) =3D RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2= ), + RISCV_DBTR_BIT_MASK(MC, TIMING) =3D RISCV_DBTR_BIT_MASK_VAL(MC, TIMING, 1= ), + RISCV_DBTR_BIT_MASK(MC, SELECT) =3D RISCV_DBTR_BIT_MASK_VAL(MC, SELECT, 1= ), + RISCV_DBTR_BIT_MASK(MC, HIT) =3D RISCV_DBTR_BIT_MASK_VAL(MC, HIT, 1), +#if __riscv_xlen >=3D 64 + RISCV_DBTR_BIT_MASK(MC, SIZEHI) =3D RISCV_DBTR_BIT_MASK_VAL(MC, SIZEHI, = 2), +#endif + RISCV_DBTR_BIT_MASK(MC, MASKMAX) =3D RISCV_DBTR_BIT_MASK_VAL(MC, MASKMAX,= 6), + RISCV_DBTR_BIT_MASK(MC, DMODE) =3D RISCV_DBTR_BIT_MASK_VAL(MC, DMODE, 1), + RISCV_DBTR_BIT_MASK(MC, TYPE) =3D RISCV_DBTR_BIT_MASK_VAL(MC, TYPE, 4), +}; + +/* MC6 - Match Control 6 Type Register */ +enum { + RISCV_DBTR_BIT(MC6, LOAD) =3D 0, + RISCV_DBTR_BIT(MC6, STORE) =3D 1, + RISCV_DBTR_BIT(MC6, EXEC) =3D 2, + RISCV_DBTR_BIT(MC6, U) =3D 3, + RISCV_DBTR_BIT(MC6, S) =3D 4, + RISCV_DBTR_BIT(MC6, RES2) =3D 5, + RISCV_DBTR_BIT(MC6, M) =3D 6, + RISCV_DBTR_BIT(MC6, MATCH) =3D 7, + RISCV_DBTR_BIT(MC6, CHAIN) =3D 11, + RISCV_DBTR_BIT(MC6, ACTION) =3D 12, + RISCV_DBTR_BIT(MC6, SIZE) =3D 16, + RISCV_DBTR_BIT(MC6, TIMING) =3D 20, + RISCV_DBTR_BIT(MC6, SELECT) =3D 21, + RISCV_DBTR_BIT(MC6, HIT) =3D 22, + RISCV_DBTR_BIT(MC6, VU) =3D 23, + RISCV_DBTR_BIT(MC6, VS) =3D 24, +#if __riscv_xlen =3D=3D 64 + RISCV_DBTR_BIT(MC6, DMODE) =3D 59, + RISCV_DBTR_BIT(MC6, TYPE) =3D 60, +#elif __riscv_xlen =3D=3D 32 + RISCV_DBTR_BIT(MC6, DMODE) =3D 27, + RISCV_DBTR_BIT(MC6, TYPE) =3D 28, +#else + #error "Unknown riscv xlen" +#endif +}; + +enum { + RISCV_DBTR_BIT_MASK(MC6, LOAD) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, LOAD, 1), + RISCV_DBTR_BIT_MASK(MC6, STORE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, STORE, = 1), + RISCV_DBTR_BIT_MASK(MC6, EXEC) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, EXEC, 1), + RISCV_DBTR_BIT_MASK(MC6, U) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, U, 1), + RISCV_DBTR_BIT_MASK(MC6, S) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, S, 1), + RISCV_DBTR_BIT_MASK(MC6, RES2) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, RES2, 1), + RISCV_DBTR_BIT_MASK(MC6, M) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, M, 1), + RISCV_DBTR_BIT_MASK(MC6, MATCH) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, MATCH, 4= ), + RISCV_DBTR_BIT_MASK(MC6, CHAIN) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, CHAIN, 1= ), + RISCV_DBTR_BIT_MASK(MC6, ACTION) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, ACTION,= 4), + RISCV_DBTR_BIT_MASK(MC6, SIZE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, SIZE, 4), + RISCV_DBTR_BIT_MASK(MC6, TIMING) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, TIMING,= 1), + RISCV_DBTR_BIT_MASK(MC6, SELECT) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, SELECT,= 1), + RISCV_DBTR_BIT_MASK(MC6, HIT) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, HIT, 1), + RISCV_DBTR_BIT_MASK(MC6, VU) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, VU, 1), + RISCV_DBTR_BIT_MASK(MC6, VS) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, VS, 1), +#if __riscv_xlen =3D=3D 64 + RISCV_DBTR_BIT_MASK(MC6, DMODE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, DMODE, 1= ), + RISCV_DBTR_BIT_MASK(MC6, TYPE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, TYPE, 4), +#elif __riscv_xlen =3D=3D 32 + RISCV_DBTR_BIT_MASK(MC6, DMODE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, DMODE, 1= ), + RISCV_DBTR_BIT_MASK(MC6, TYPE) =3D RISCV_DBTR_BIT_MASK_VAL(MC6, TYPE, 4), +#else + #error "Unknown riscv xlen" +#endif +}; + +#define RISCV_DBTR_SET_TDATA1_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (td1t1) =3D (_t1); \ + (td1t1) &=3D ~RISCV_DBTR_BIT_MASK(TDATA1, TYPE); \ + (td1t1) |=3D (((unsigned long)(_type) \ + << RISCV_DBTR_BIT(TDATA1, TYPE)) \ + & RISCV_DBTR_BIT_MASK(TDATA1, TYPE)); \ + (td1t1); \ + }) + +#define RISCV_DBTR_SET_MC_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (mct1) =3D (_t1); \ + (mct1) &=3D ~RISCV_DBTR_BIT_MASK(MC, TYPE); \ + (mct1) |=3D (((unsigned long)(_type) \ + << RISCV_DBTR_BIT(MC, TYPE)) \ + & RISCV_DBTR_BIT_MASK(MC, TYPE)); \ + (mct1); \ + }) + +#define RISCV_DBTR_SET_MC6_TYPE(_t1, _type) \ + ({ \ + typeof(_t1) (mc6t1) =3D (_t1); \ + (mc6t1) &=3D ~RISCV_DBTR_BIT_MASK(MC6, TYPE); \ + (mc6t1) |=3D (((unsigned long)(_type) \ + << RISCV_DBTR_BIT(MC6, TYPE)) \ + & RISCV_DBTR_BIT_MASK(MC6, TYPE)); \ + (mc6t1); \ + }) + +#define RISCV_DBTR_SET_MC_EXEC_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, EXEC) + +#define RISCV_DBTR_SET_MC_LOAD_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, LOAD) + +#define RISCV_DBTR_SET_MC_STORE_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC, STORE) + +#define RISCV_DBTR_SET_MC_SIZELO(_t1, _val) \ + ({ \ + typeof(_t1) (mcslt1) =3D (_t1); \ + mcslt1 &=3D ~RISCV_DBTR_BIT_MASK(MC, SIZELO); \ + mcslt1 |=3D (((_val) << RISCV_DBTR_BIT(MC, SIZELO)) \ + & RISCV_DBTR_BIT_MASK(MC, SIZELO)); \ + (mcslt1); \ + }) + +#define RISCV_DBTR_SET_MC_SIZEHI(_t1, _val) \ + ({ \ + typeof(_t1) (mcsht1) =3D (_t1); \ + mcsht1 &=3D ~RISCV_DBTR_BIT_MASK(MC, SIZEHI); \ + mcsht1 |=3D (((_val) << RISCV_DBTR_BIT(MC, SIZEHI)) \ + & RISCV_DBTR_BIT_MASK(MC, SIZEHI)); \ + (mcsht1); \ + }) + +#define RISCV_DBTR_SET_MC6_EXEC_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, EXEC) + +#define RISCV_DBTR_SET_MC6_LOAD_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, LOAD) + +#define RISCV_DBTR_SET_MC6_STORE_BIT(_t1) \ + SET_DBTR_BIT(_t1, MC6, STORE) + +#define RISCV_DBTR_SET_MC6_SIZE(_t1, _val) \ + ({ \ + typeof(_t1) (mc6szt1) =3D (_t1); \ + (mc6szt1) &=3D ~RISCV_DBTR_BIT_MASK(MC6, SIZE); \ + (mc6szt1) |=3D (((_val) << RISCV_DBTR_BIT(MC6, SIZE)) \ + & RISCV_DBTR_BIT_MASK(MC6, SIZE)); \ + (mc6szt1); \ + }) + +struct arch_hw_breakpoint { + unsigned long address; + unsigned long len; + unsigned int type; + + /* Trigger configuration data */ + unsigned long tdata1; + unsigned long tdata2; + unsigned long tdata3; +}; + +struct perf_event_attr; +struct notifier_block; +struct perf_event; +struct pt_regs; + +int hw_breakpoint_slots(int type); +int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw); +int hw_breakpoint_arch_parse(struct perf_event *bp, + const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw); +int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data); + +void arch_enable_hw_breakpoint(struct perf_event *bp); +void arch_update_hw_breakpoint(struct perf_event *bp); +void arch_disable_hw_breakpoint(struct perf_event *bp); +int arch_install_hw_breakpoint(struct perf_event *bp); +void arch_uninstall_hw_breakpoint(struct perf_event *bp); +void hw_breakpoint_pmu_read(struct perf_event *bp); +void clear_ptrace_hw_breakpoint(struct task_struct *tsk); +void flush_ptrace_hw_breakpoint(struct task_struct *tsk); + +#else + +int hw_breakpoint_slots(int type) +{ + return 0; +} + +static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +static inline void flush_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +void arch_enable_hw_breakpoint(struct perf_event *bp) +{ +} + +void arch_update_hw_breakpoint(struct perf_event *bp) +{ +} + +void arch_disable_hw_breakpoint(struct perf_event *bp) +{ +} + +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ +#endif /* __RISCV_HW_BREAKPOINT_H */ diff --git a/arch/riscv/include/asm/kdebug.h b/arch/riscv/include/asm/kdebu= g.h index 85ac00411f6e..53e989781aa1 100644 --- a/arch/riscv/include/asm/kdebug.h +++ b/arch/riscv/include/asm/kdebug.h @@ -6,7 +6,8 @@ enum die_val { DIE_UNUSED, DIE_TRAP, - DIE_OOPS + DIE_OOPS, + DIE_DEBUG }; =20 #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index cabb99cadfb6..590a280762c9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) +=3D mcount-dyn.o =20 obj-$(CONFIG_PERF_EVENTS) +=3D perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) +=3D perf_regs.o +obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o obj-$(CONFIG_RISCV_SBI) +=3D sbi.o sbi_ecall.o ifeq ($(CONFIG_RISCV_SBI), y) obj-$(CONFIG_SMP) +=3D sbi-ipi.o diff --git a/arch/riscv/kernel/hw_breakpoint.c b/arch/riscv/kernel/hw_break= point.c new file mode 100644 index 000000000000..34556a8f3c9b --- /dev/null +++ b/arch/riscv/kernel/hw_breakpoint.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Registered per-cpu bp/wp */ +static DEFINE_PER_CPU(struct perf_event *, pcpu_hw_bp_events[RISCV_HW_BP_N= UM_MAX]); +static DEFINE_PER_CPU(unsigned long, ecall_lock_flags); +static DEFINE_PER_CPU(raw_spinlock_t, ecall_lock); + +/* Per-cpu shared memory between S and M mode */ +static union sbi_dbtr_shmem_entry __percpu *sbi_dbtr_shmem; + +/* number of debug triggers on this cpu . */ +static int dbtr_total_num __ro_after_init; +static int dbtr_type __ro_after_init; +static int dbtr_init __ro_after_init; + +#if __riscv_xlen =3D=3D 64 +#define MEM_HI(_m) 0 +#define MEM_LO(_m) ((u64)(_m)) +#elif __riscv_xlen =3D=3D 32 +#define MEM_HI(_m) ((u64)(_m) >> 32) +#define MEM_LO(_m) ((u64)(_m) & 0xFFFFFFFFUL) +#else +#error "Unknown __riscv_xlen" +#endif + +static int arch_smp_setup_sbi_shmem(unsigned int cpu) +{ + union sbi_dbtr_shmem_entry *dbtr_shmem; + unsigned long shmem_pa; + struct sbiret ret; + int rc =3D 0; + + dbtr_shmem =3D per_cpu_ptr(sbi_dbtr_shmem, cpu); + if (!dbtr_shmem) { + pr_err("Invalid per-cpu shared memory for debug triggers\n"); + return -ENODEV; + } + + shmem_pa =3D __pa(dbtr_shmem); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, + MEM_LO(shmem_pa), MEM_HI(shmem_pa), 0, 0, 0, 0); + + if (ret.error) { + switch (ret.error) { + case SBI_ERR_DENIED: + pr_warn("Access denied for shared memory at %lx\n", + shmem_pa); + rc =3D -EPERM; + break; + + case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_ADDRESS: + pr_warn("Invalid address parameter (%lu)\n", + ret.error); + rc =3D -EINVAL; + break; + + case SBI_ERR_ALREADY_AVAILABLE: + pr_warn("Shared memory is already set\n"); + rc =3D -EADDRINUSE; + break; + + case SBI_ERR_FAILURE: + pr_err("Internal sdtrig state error\n"); + rc =3D -ENXIO; + break; + + default: + pr_warn("Unknown error %lu\n", ret.error); + rc =3D -ENXIO; + break; + } + } + + pr_info("CPU %d: HW Breakpoint shared memory registered.\n", cpu); + + return rc; +} + +static int arch_smp_teardown_sbi_shmem(unsigned int cpu) +{ + struct sbiret ret; + + /* Disable shared memory */ + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, + -1UL, -1UL, 0, 0, 0, 0); + + if (ret.error) { + switch (ret.error) { + case SBI_ERR_DENIED: + pr_err("Access denied for shared memory.\n"); + break; + + case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_ADDRESS: + pr_err("Invalid address parameter (%lu)\n", ret.error); + break; + + case SBI_ERR_ALREADY_AVAILABLE: + pr_err("Shared memory is already set\n"); + break; + case SBI_ERR_FAILURE: + pr_err("Internal sdtrig state error\n"); + break; + default: + pr_err("Unknown error %lu\n", ret.error); + break; + } + } + + pr_warn("CPU %d: HW Breakpoint shared memory disabled.\n", cpu); + + return 0; +} + +static void init_sbi_dbtr(void) +{ + unsigned long tdata1; + struct sbiret ret; + + if (sbi_probe_extension(SBI_EXT_DBTR) <=3D 0) { + pr_warn("SBI_EXT_DBTR is not supported\n"); + dbtr_total_num =3D 0; + goto done; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + 0, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("Failed to detect triggers\n"); + dbtr_total_num =3D 0; + goto done; + } + + tdata1 =3D 0; + tdata1 =3D RISCV_DBTR_SET_TDATA1_TYPE(tdata1, RISCV_DBTR_TRIG_MCONTROL6); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + tdata1, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("Failed to detect mcontrol6 triggers\n"); + } else if (!ret.value) { + pr_warn("Type 6 triggers not available\n"); + } else { + dbtr_total_num =3D ret.value; + dbtr_type =3D RISCV_DBTR_TRIG_MCONTROL6; + pr_warn("Mcontrol6 trigger available.\n"); + goto done; + } + + /* fallback to type 2 triggers if type 6 is not available */ + + tdata1 =3D 0; + tdata1 =3D RISCV_DBTR_SET_TDATA1_TYPE(tdata1, RISCV_DBTR_TRIG_MCONTROL); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS, + tdata1, 0, 0, 0, 0, 0); + if (ret.error) { + pr_warn("Failed to detect mcontrol triggers\n"); + } else if (!ret.value) { + pr_warn("Type 2 triggers not available\n"); + } else { + dbtr_total_num =3D ret.value; + dbtr_type =3D RISCV_DBTR_TRIG_MCONTROL; + goto done; + } + +done: + dbtr_init =3D 1; +} + +int hw_breakpoint_slots(int type) +{ + /* + * We can be called early, so don't rely on + * static variables being initialised. + */ + + if (!dbtr_init) + init_sbi_dbtr(); + + return dbtr_total_num; +} + +int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) +{ + unsigned int len; + unsigned long va; + + va =3D hw->address; + len =3D hw->len; + + return (va >=3D TASK_SIZE) && ((va + len - 1) >=3D TASK_SIZE); +} + +static int rv_init_mcontrol_trigger(const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + switch (attr->bp_type) { + case HW_BREAKPOINT_X: + hw->type =3D RISCV_DBTR_EXEC; + RISCV_DBTR_SET_MC_EXEC_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_R: + hw->type =3D RISCV_DBTR_LOAD; + RISCV_DBTR_SET_MC_LOAD_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_W: + hw->type =3D RISCV_DBTR_STORE; + RISCV_DBTR_SET_MC_STORE_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_RW: + hw->type =3D RISCV_DBTR_LDST; + RISCV_DBTR_SET_MC_LOAD_BIT(hw->tdata1); + RISCV_DBTR_SET_MC_STORE_BIT(hw->tdata1); + break; + default: + return -EINVAL; + } + + if (attr->bp_type =3D=3D HW_BREAKPOINT_X) { + /* + * Userspace debuggers can request execute breakpoints with + * bp_len =3D=3D 2 for compressed/non-aligned instruction + * addresses. Program execute triggers with "match any size" + * to avoid missing valid instruction fetches. + */ + hw->len =3D 0; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 0); + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0); + } else { + switch (attr->bp_len) { + case HW_BREAKPOINT_LEN_1: + hw->len =3D 1; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 1); + break; + case HW_BREAKPOINT_LEN_2: + hw->len =3D 2; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 2); + break; + case HW_BREAKPOINT_LEN_4: + hw->len =3D 4; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 3); + break; +#if __riscv_xlen >=3D 64 + case HW_BREAKPOINT_LEN_8: + hw->len =3D 8; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 1); + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 1); + break; +#endif + /* Set to match any size */ + default: + hw->len =3D 0; + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZELO(hw->tdata1, 0); + hw->tdata1 =3D RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0); + break; + } + } + + hw->tdata1 =3D RISCV_DBTR_SET_MC_TYPE(hw->tdata1, RISCV_DBTR_TRIG_MCONTRO= L); + + CLEAR_DBTR_BIT(hw->tdata1, MC, DMODE); + CLEAR_DBTR_BIT(hw->tdata1, MC, TIMING); + CLEAR_DBTR_BIT(hw->tdata1, MC, SELECT); + CLEAR_DBTR_BIT(hw->tdata1, MC, ACTION); + CLEAR_DBTR_BIT(hw->tdata1, MC, CHAIN); + CLEAR_DBTR_BIT(hw->tdata1, MC, MATCH); + CLEAR_DBTR_BIT(hw->tdata1, MC, M); + + SET_DBTR_BIT(hw->tdata1, MC, S); + SET_DBTR_BIT(hw->tdata1, MC, U); + + return 0; +} + +static int rv_init_mcontrol6_trigger(const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + switch (attr->bp_type) { + case HW_BREAKPOINT_X: + hw->type =3D RISCV_DBTR_EXEC; + RISCV_DBTR_SET_MC6_EXEC_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_R: + hw->type =3D RISCV_DBTR_LOAD; + RISCV_DBTR_SET_MC6_LOAD_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_W: + hw->type =3D RISCV_DBTR_STORE; + RISCV_DBTR_SET_MC6_STORE_BIT(hw->tdata1); + break; + case HW_BREAKPOINT_RW: + hw->type =3D RISCV_DBTR_LDST; + RISCV_DBTR_SET_MC6_STORE_BIT(hw->tdata1); + RISCV_DBTR_SET_MC6_LOAD_BIT(hw->tdata1); + break; + default: + return -EINVAL; + } + + if (attr->bp_type =3D=3D HW_BREAKPOINT_X) { + /* See rv_init_mcontrol_trigger() for rationale. */ + hw->len =3D 0; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 0); + } else { + switch (attr->bp_len) { + case HW_BREAKPOINT_LEN_1: + hw->len =3D 1; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 1); + break; + case HW_BREAKPOINT_LEN_2: + hw->len =3D 2; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 2); + break; + case HW_BREAKPOINT_LEN_4: + hw->len =3D 4; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 3); + break; +#if __riscv_xlen >=3D 64 + case HW_BREAKPOINT_LEN_8: + hw->len =3D 8; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 5); + break; +#endif + /* Set to match any size */ + default: + hw->len =3D 0; + hw->tdata1 =3D RISCV_DBTR_SET_MC6_SIZE(hw->tdata1, 0); + } + } + + hw->tdata1 =3D RISCV_DBTR_SET_MC6_TYPE(hw->tdata1, RISCV_DBTR_TRIG_MCONTR= OL6); + + CLEAR_DBTR_BIT(hw->tdata1, MC6, DMODE); + CLEAR_DBTR_BIT(hw->tdata1, MC6, TIMING); + CLEAR_DBTR_BIT(hw->tdata1, MC6, SELECT); + CLEAR_DBTR_BIT(hw->tdata1, MC6, ACTION); + CLEAR_DBTR_BIT(hw->tdata1, MC6, CHAIN); + CLEAR_DBTR_BIT(hw->tdata1, MC6, MATCH); + CLEAR_DBTR_BIT(hw->tdata1, MC6, M); + CLEAR_DBTR_BIT(hw->tdata1, MC6, VS); + CLEAR_DBTR_BIT(hw->tdata1, MC6, VU); + + SET_DBTR_BIT(hw->tdata1, MC6, S); + SET_DBTR_BIT(hw->tdata1, MC6, U); + + return 0; +} + +int hw_breakpoint_arch_parse(struct perf_event *bp, + const struct perf_event_attr *attr, + struct arch_hw_breakpoint *hw) +{ + int ret; + + /* Breakpoint address */ + hw->address =3D attr->bp_addr; + hw->tdata2 =3D attr->bp_addr; + hw->tdata3 =3D 0x0; + + switch (dbtr_type) { + case RISCV_DBTR_TRIG_MCONTROL: + ret =3D rv_init_mcontrol_trigger(attr, hw); + break; + case RISCV_DBTR_TRIG_MCONTROL6: + ret =3D rv_init_mcontrol6_trigger(attr, hw); + break; + default: + pr_warn("Unsupported trigger type\n"); + ret =3D -EOPNOTSUPP; + break; + } + + return ret; +} + +/* + * HW Breakpoint/watchpoint handler + */ +static int hw_breakpoint_handler(struct die_args *args) +{ + int ret =3D NOTIFY_DONE; + struct arch_hw_breakpoint *bp; + struct perf_event *event; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + event =3D this_cpu_read(pcpu_hw_bp_events[i]); + if (!event) + continue; + + bp =3D counter_arch_bp(event); + switch (bp->type) { + /* Breakpoint */ + case RISCV_DBTR_EXEC: + if (bp->address =3D=3D args->regs->epc) { + perf_bp_event(event, args->regs); + ret =3D NOTIFY_STOP; + } + break; + + /* Watchpoint */ + case RISCV_DBTR_LOAD: + case RISCV_DBTR_STORE: + case RISCV_DBTR_LDST: + { + unsigned long stval =3D csr_read(CSR_STVAL); + unsigned long bp_start =3D bp->address; + unsigned long bp_len =3D bp->len ?: 1; + unsigned long bp_end =3D bp_start + bp_len - 1; + unsigned long stval_end =3D stval + sizeof(long) - 1; + unsigned long tdata1; + bool hit =3D false; + struct sbiret sret; + union sbi_dbtr_shmem_entry *shmem; + + if (bp_end < bp_start) + bp_end =3D ~0UL; + if (stval_end < stval) + stval_end =3D ~0UL; + + /* + * Prefer tdata1.hit from SBI trigger readout whenever + * possible. Fall back to address-based matching if HIT + * isn't observed/supported. + */ + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + shmem =3D this_cpu_ptr(sbi_dbtr_shmem); + sret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_READ, + i, 1, 0, 0, 0, 0); + if (!sret.error) { + tdata1 =3D le_to_cpu(shmem->data.tdata1); + + if (dbtr_type =3D=3D RISCV_DBTR_TRIG_MCONTROL) + hit =3D !!(tdata1 & RISCV_DBTR_BIT_MASK(MC, HIT)); + else if (dbtr_type =3D=3D RISCV_DBTR_TRIG_MCONTROL6) + hit =3D !!(tdata1 & RISCV_DBTR_BIT_MASK(MC6, HIT)); + } + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + /* + * Sdtrig may report STVAL as the lowest accessed + * address while the watchpoint can match a higher byte + * in the same access. + */ + if (hit || + (stval >=3D bp_start && stval <=3D bp_end) || + (bp_start >=3D stval && bp_start <=3D stval_end)) { + perf_bp_event(event, args->regs); + ret =3D NOTIFY_STOP; + } + break; + } + + default: + pr_warn("Unknown type: %u\n", bp->type); + break; + } + } + + return ret; +} + +int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data) +{ + if (val !=3D DIE_DEBUG) + return NOTIFY_DONE; + + return hw_breakpoint_handler(data); +} + +/* atomic: counter->ctx->lock is held */ +int arch_install_hw_breakpoint(struct perf_event *event) +{ + struct arch_hw_breakpoint *bp =3D counter_arch_bp(event); + union sbi_dbtr_shmem_entry *shmem =3D this_cpu_ptr(sbi_dbtr_shmem); + struct sbi_dbtr_data_msg *xmit; + struct sbi_dbtr_id_msg *recv; + struct perf_event **slot; + unsigned long idx; + struct sbiret ret; + int err =3D 0; + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + xmit =3D &shmem->data; + recv =3D &shmem->id; + xmit->tdata1 =3D cpu_to_le(bp->tdata1); + xmit->tdata2 =3D cpu_to_le(bp->tdata2); + xmit->tdata3 =3D cpu_to_le(bp->tdata3); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_INSTALL, + 1, 0, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("Failed to install trigger\n"); + err =3D -EIO; + goto done; + } + + idx =3D le_to_cpu(recv->idx); + if (idx >=3D dbtr_total_num) { + pr_warn("Invalid trigger index %lu\n", idx); + err =3D -EINVAL; + goto done; + } + + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[idx]); + if (*slot) { + pr_warn("Slot %lu is in use\n", idx); + err =3D -EBUSY; + goto done; + } + + /* Save the event - to be looked up in handler */ + *slot =3D event; + +done: + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + return err; +} + +/* atomic: counter->ctx->lock is held */ +void arch_uninstall_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + for (i =3D 0; i < dbtr_total_num; i++) { + struct perf_event **slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) { + *slot =3D NULL; + break; + } + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("Breakpoint not installed.\n"); + goto out; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_UNINSTALL, + i, 1, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("Failed to uninstall trigger %d.\n", i); + goto out; + } + + out: + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); +} + +void arch_enable_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + struct perf_event **slot; + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + for (i =3D 0; i < dbtr_total_num; i++) { + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("Breakpoint not installed.\n"); + goto out; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_ENABLE, + i, 1, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("Failed to install trigger %d\n", i); + goto out; + } + + out: + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); +} +EXPORT_SYMBOL_GPL(arch_enable_hw_breakpoint); + +void arch_update_hw_breakpoint(struct perf_event *event) +{ + struct arch_hw_breakpoint *bp =3D counter_arch_bp(event); + union sbi_dbtr_shmem_entry *shmem =3D this_cpu_ptr(sbi_dbtr_shmem); + struct sbi_dbtr_data_msg *xmit; + struct perf_event **slot; + struct sbiret ret; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("Breakpoint not installed.\n"); + return; + } + + raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); + + xmit =3D &shmem->data; + xmit->tdata1 =3D cpu_to_le(bp->tdata1); + xmit->tdata2 =3D cpu_to_le(bp->tdata2); + xmit->tdata3 =3D cpu_to_le(bp->tdata3); + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_UPDATE, + i, 1, 0, 0, 0, 0); + if (ret.error) + pr_warn("Failed to update trigger %d.\n", i); + + raw_spin_unlock_irqrestore(this_cpu_ptr(&ecall_lock), + *this_cpu_ptr(&ecall_lock_flags)); +} +EXPORT_SYMBOL_GPL(arch_update_hw_breakpoint); + +void arch_disable_hw_breakpoint(struct perf_event *event) +{ + struct sbiret ret; + int i; + + for (i =3D 0; i < dbtr_total_num; i++) { + struct perf_event **slot =3D this_cpu_ptr(&pcpu_hw_bp_events[i]); + + if (*slot =3D=3D event) + break; + } + + if (i =3D=3D dbtr_total_num) { + pr_warn("Breakpoint not installed.\n"); + return; + } + + ret =3D sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_TRIG_DISABLE, + i, 1, 0, 0, 0, 0); + + if (ret.error) { + pr_warn("Failed to uninstall trigger %d.\n", i); + return; + } +} +EXPORT_SYMBOL_GPL(arch_disable_hw_breakpoint); + +void hw_breakpoint_pmu_read(struct perf_event *bp) +{ +} + +void clear_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +void flush_ptrace_hw_breakpoint(struct task_struct *tsk) +{ +} + +static int __init arch_hw_breakpoint_init(void) +{ + unsigned int cpu; + int rc =3D 0; + + for_each_possible_cpu(cpu) + raw_spin_lock_init(&per_cpu(ecall_lock, cpu)); + + if (!dbtr_init) + init_sbi_dbtr(); + + if (dbtr_total_num) { + pr_info("Total number of type %d triggers: %u\n", + dbtr_type, dbtr_total_num); + } else { + pr_info("No hardware triggers available\n"); + goto out; + } + + /* Allocate per-cpu shared memory */ + sbi_dbtr_shmem =3D __alloc_percpu(sizeof(*sbi_dbtr_shmem) * dbtr_total_nu= m, + PAGE_SIZE); + + if (!sbi_dbtr_shmem) { + pr_warn("Failed to allocate shared memory.\n"); + rc =3D -ENOMEM; + goto out; + } + + /* Hotplug handler to register/unregister shared memory with SBI */ + rc =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "riscv/hw_breakpoint:prepare", + arch_smp_setup_sbi_shmem, + arch_smp_teardown_sbi_shmem); + + if (rc < 0) { + pr_warn("Failed to setup CPU hotplug state\n"); + free_percpu(sbi_dbtr_shmem); + return rc; + } + out: + return rc; +} +arch_initcall(arch_hw_breakpoint_init); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c62c771a656..029fd66a285e 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -286,6 +286,12 @@ void handle_break(struct pt_regs *regs) if (probe_breakpoint_handler(regs)) return; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-369c5f0eb2bsm2058381a91.7.2026.05.17.23.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 23:59:41 -0700 (PDT) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Cc: Himanshu Chauhan Subject: [PATCH v4 2/2] riscv: Add breakpoint and watchpoint test for riscv Date: Mon, 18 May 2026 12:29:19 +0530 Message-ID: <20260518065920.872131-3-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> References: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=cuSrVV4i c=1 sm=1 tr=0 ts=6a0ab8df cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=DSfzdtd1K3_Evk7s5LgA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE4MDA2NSBTYWx0ZWRfX4tgqSm5Ux0Eo 185opb2SlNcCvAZ/AKeqM+sanho8gZtlM6rKggE4AdhHlpR/QYkVmm1nK3c2dVeUNmWLrSPYmiX yfwwh2RBvyDsElU0yE1IkHXlncxYP49kx/jK0gUY/DiZ8lsEtyc7wJx3fq57o8w0iYco06eDRzt yJelNvVkl9cErdANCN4AaP7HzOhH0/brEQOIp9iuKTyt6ySY0E8FDOXHOPXy/2rvheZtdTCkLm6 lspAoFgAxopAV+fgmc4q/mnuzkAkQ9j4AtURZwonkwJk19o7QuOuLM77sBQApEziPmaxiGpHKzZ 0W56yw7oSNmWTJdZa686Vv81N294n1xAqvQ7OputoPsdhbqnIwnBc11o+0DSRlAh0hXcYMgUYLK v0BPquF8k4cCTdwuIff78ZLsCDdOeR+paFHuEcDfqZIbNo8TZAQcpd8aFnKOfKT8dn77IUnSROd XbF5lnGAxohdNdoiGfQ== X-Proofpoint-GUID: y3DyQrKiYwh_82Gj3PWAzB5yngsvZsNv X-Proofpoint-ORIG-GUID: y3DyQrKiYwh_82Gj3PWAzB5yngsvZsNv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-18_01,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605180065 Content-Type: text/plain; charset="utf-8" Add self test for riscv architecture. It uses ptrace to ptrace framework to set/unset break/watchpoint and uses signals to check triggers. Signed-off-by: Himanshu Chauhan --- tools/testing/selftests/breakpoints/Makefile | 5 + .../breakpoints/breakpoint_test_riscv.c | 214 ++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_ris= cv.c diff --git a/tools/testing/selftests/breakpoints/Makefile b/tools/testing/s= elftests/breakpoints/Makefile index 0b8f5acf7c78..c16782460b49 100644 --- a/tools/testing/selftests/breakpoints/Makefile +++ b/tools/testing/selftests/breakpoints/Makefile @@ -12,5 +12,10 @@ ifneq (,$(filter $(ARCH),aarch64 arm64)) TEST_GEN_PROGS +=3D breakpoint_test_arm64 endif =20 +ifneq (,$(filter $(ARCH),riscv)) +CFLAGS +=3D -static +TEST_GEN_PROGS +=3D breakpoint_test_riscv +endif + include ../lib.mk =20 diff --git a/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c b/= tools/testing/selftests/breakpoints/breakpoint_test_riscv.c new file mode 100644 index 000000000000..35c043f4271c --- /dev/null +++ b/tools/testing/selftests/breakpoints/breakpoint_test_riscv.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Qualcomm Technologies, Inc. + * + * Author: Himanshu Chauhan + */ + +#define _GNU_SOURCE +#include /* Definition of PERF_* constants */ +#include /* Definition of HW_* constants */ +#include /* Definition of SYS_* constants */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int gfd; +sem_t ib_mtx, wp_mtx; +static int bp_triggered, wp_triggered; +static volatile int test_func_sink; +static const int wait_timeout_sec =3D 5; + +int setup_bp(bool is_x, void *addr, int sig) +{ + struct perf_event_attr pe; + int fd; + + memset(&pe, 0, sizeof(struct perf_event_attr)); + pe.type =3D PERF_TYPE_BREAKPOINT; + pe.size =3D sizeof(struct perf_event_attr); + + pe.config =3D 0; + pe.bp_type =3D is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W; + pe.bp_addr =3D (unsigned long)addr; + pe.bp_len =3D sizeof(long); + + pe.sample_period =3D 1; + pe.sample_type =3D PERF_SAMPLE_IP; + pe.wakeup_events =3D 1; + + pe.disabled =3D 1; + pe.exclude_kernel =3D 1; + pe.exclude_hv =3D 1; + + fd =3D syscall(SYS_perf_event_open, &pe, 0, -1, -1, 0); + if (fd < 0) { + printf("Failed to open event: %llx\n", pe.config); + return -1; + } + + fcntl(fd, F_SETFL, O_RDWR | O_NONBLOCK | O_ASYNC); + fcntl(fd, F_SETSIG, sig); + fcntl(fd, F_SETOWN, getpid()); + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + + return fd; +} + +static void sig_handler_bp(int signum, siginfo_t *oh, void *uc) +{ + int ret; + + bp_triggered++; + + printf("Breakpoint triggered!\n"); + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + ret =3D sem_post(&ib_mtx); + if (ret) { + printf("Failed to report BP success\n"); + return; + } +} + +static void sig_handler_wp(int signum, siginfo_t *oh, void *uc) +{ + int ret; + + printf("Watchpoint triggered!\n"); + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + wp_triggered++; + + ret =3D sem_post(&wp_mtx); + + if (ret) { + printf("Failed to report WP success\n"); + return; + } +} + +/* + * Keep a real instruction address for HW execute breakpoints: prevent inl= ining + * and force a visible side effect so the function can't be optimized away. + */ +static __attribute__((noinline)) void test_func(void) +{ + test_func_sink++; +} + +static int trigger_bp(void) +{ + struct sigaction sa; + + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_sigaction =3D (void *)sig_handler_bp; + sa.sa_flags =3D SA_SIGINFO; + + if (sigaction(SIGIO, &sa, NULL) < 0) { + printf("Failed to setup signal handler\n"); + return -1; + } + + gfd =3D setup_bp(1, test_func, SIGIO); + + if (gfd < 0) { + printf("Failed to setup breakpoint.\n"); + return -1; + } + + ioctl(gfd, PERF_EVENT_IOC_ENABLE, 0); + + test_func(); + + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + + close(gfd); + + return 0; +} + +static int trigger_wp(void) +{ + struct sigaction sa; + unsigned long test_data; + + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_sigaction =3D (void *)sig_handler_wp; + sa.sa_flags =3D SA_SIGINFO; + + if (sigaction(SIGUSR1, &sa, NULL) < 0) { + printf("Failed to setup signal handler\n"); + return -1; + } + + gfd =3D setup_bp(0, &test_data, SIGUSR1); + + if (gfd < 0) { + printf("Failed to setup watchpoint\n"); + return -1; + } + + ioctl(gfd, PERF_EVENT_IOC_ENABLE, 0); + test_data =3D 0xdeadbeef; + ioctl(gfd, PERF_EVENT_IOC_DISABLE, 0); + + return 0; +} + +static int wait_event(sem_t *sem, const char *name) +{ + struct timespec ts; + + if (clock_gettime(CLOCK_REALTIME, &ts)) { + printf("%s: Failed to get current time\n", name); + return -1; + } + + /* + * Deadlock fix: avoid blocking forever on sem_wait() if the breakpoint/ + * watchpoint signal never arrives. Use a bounded wait and fail the test + * on timeout instead. + */ + ts.tv_sec +=3D wait_timeout_sec; + if (!sem_timedwait(sem, &ts)) + return 0; + + if (errno =3D=3D ETIMEDOUT) + printf("%s: Timed out waiting for event\n", name); + else + printf("%s: sem_timedwait() failed with %d\n", name, errno); + + return -1; +} + +int main(int argc, char *argv[]) +{ + sem_init(&ib_mtx, 0, 0); + if (trigger_bp() < 0) + return -1; + if (wait_event(&ib_mtx, "Breakpoint") < 0) + return -1; + + if (bp_triggered) + printf("Breakpoint test passed!\n"); + + sem_init(&wp_mtx, 0, 0); + if (trigger_wp() < 0) + return -1; + if (wait_event(&wp_mtx, "Watchpoint") < 0) + return -1; + + if (wp_triggered) + printf("Watchpoint test passed!\n"); + + return 0; +} --=20 2.43.0