From nobody Mon May 25 05:58:57 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE603DE430 for ; Mon, 18 May 2026 06:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085796; cv=none; b=Y3+lLAq4OLrO8q9VSgfknqNJjdPlVF03ZPR1VDLUFOiGbokk/PVkEdpXJe3UFAxl0Xju8LISbnD5C5DBFRKEsM8mz/z+2qPrL64GAsxeDJEsnYU3xBbu8VelnWgWN7QGosYKpnNmmTEg5r3IRyrjfFHJ1Pmgy7ucRSAf/rcrAA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085796; c=relaxed/simple; bh=H+icPAriBZWrdlYyD8bWFA9xYukOL9VTzqfsaOiDpJw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bHY6EIukwKeeoDVcn5rA4tvDJwt/dVIOgPwnTmfBQ7kcEOaPQSzeZWSjJRcSQjkHUE20fuDKm0QGi1HC5GBflgEE2AnZH4O92baH7mSfYGSuYqz6gXxsfAuYcE5ASCxtWzcgfCup668+WVSSEzPb1HP+HHuI+8r16LtnMNLaLcI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: f4eaec2a528211f1aa26b74ffac11d73-20260518 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:3bf6197a-939b-43af-8494-931d46484943,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:483781cd61cd259dd97a0f64e3341516,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|850|865|898,TC:nil,Content:0|1 5|50,EDM:-3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: f4eaec2a528211f1aa26b74ffac11d73-20260518 X-User: zenghongling@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 2128557614; Mon, 18 May 2026 14:29:43 +0800 From: Hongling Zeng To: vkoul@kernel.org, neil.armstrong@linaro.org, johan@kernel.org, kishon@kernel.org, rogerq@ti.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, zhongling0719@126.com, Hongling Zeng , Sashiko AI Subject: [PATCH v5 1/4] phy: ti-pipe3: Fix ignored clock enable return value in init Date: Mon, 18 May 2026 14:29:35 +0800 Message-Id: <20260518062938.48114-2-zenghongling@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260518062938.48114-1-zenghongling@kylinos.cn> References: <20260518062938.48114-1-zenghongling@kylinos.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ti_pipe3_init() ignores the return value of ti_pipe3_enable_clocks(), which can lead to: 1. Unclocked hardware access if clock enable fails 2. Unbalanced clock disables in error paths ti_pipe3_enable_clocks() returns an error code when clock enable fails and rolls back any partially enabled clocks. If we ignore this error and continue, we access hardware without proper clocking, which can cause bus errors. Additionally, if we reach error paths later in the function and call ti_pipe3_disable_clocks(), we'll be disabling already-disabled clocks, causing unbalanced disable warnings. Fix this by checking the return value of ti_pipe3_enable_clocks() and returning early if it fails. Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate = function") Reported-by: Sashiko AI Signed-off-by: Hongling Zeng --- Change in v5: -Add Fix ignored clock enable return value in init patch --- drivers/phy/ti/phy-ti-pipe3.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index b5543b5c674c..b8c055893742 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -500,7 +500,10 @@ static int ti_pipe3_init(struct phy *x) u32 val; int ret =3D 0; =20 - ti_pipe3_enable_clocks(phy); + ret =3D ti_pipe3_enable_clocks(phy); + if (ret) + return ret; + /* * Set pcie_pcs register to 0x96 for proper functioning of phy * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table --=20 2.25.1 From nobody Mon May 25 05:58:57 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1841FC10C for ; Mon, 18 May 2026 06:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085794; cv=none; b=AhVejZfpv7aj24QLYIERMku/QstbsRLrbzWxLdblyGx7+8oFGsCZ9JbCIgYpyoBg5XxyaaMKMtx2y7pEcO855GJ4S1RitXlg5+ScoLiCbJdaoNgLDgygydZWdJgRahfr+vze9Jql6JgfvYV52S2gIh7IB+SpXik4CP9QoXJ7Eew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085794; c=relaxed/simple; bh=1e1t+yvuTqPsCYQH6RMJjWPkbrM9Cfm3YsNFJM0bNDQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=axqmTBYxdTEU14qvAORutBE+YlsDARK097yRpKyOa3HzLTcMxZORiuBOa98AIDbqEw9y6XdN2qR4FvM5sjnO1z1wD4AvRgSzaTW2LpQz9HaY8N1lZ9tgnZWkHKF5wd7yLxxpVBZn0SV0bUBMpR7oAaqd4yIQFeWMbj4E+RtWWJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: f5458bbc528211f1aa26b74ffac11d73-20260518 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:f4634ab2-a037-462c-8870-10f88776babb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:6ba77a806615c08d25187b8a895c8eff,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|850|865|898,TC:nil,Content:0|1 5|50,EDM:-3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: f5458bbc528211f1aa26b74ffac11d73-20260518 X-User: zenghongling@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 858854688; Mon, 18 May 2026 14:29:43 +0800 From: Hongling Zeng To: vkoul@kernel.org, neil.armstrong@linaro.org, johan@kernel.org, kishon@kernel.org, rogerq@ti.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, zhongling0719@126.com, Hongling Zeng Subject: [PATCH v5 2/4] phy: ti: pipe3: Fix clock resource leak on probe errors Date: Mon, 18 May 2026 14:29:36 +0800 Message-Id: <20260518062938.48114-3-zenghongling@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260518062938.48114-1-zenghongling@kylinos.cn> References: <20260518062938.48114-1-zenghongling@kylinos.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When devm_phy_create() or devm_of_phy_provider_register() fails, the refclk that was enabled earlier is not disabled, causing a resource leak. Fix this by adding an error handling path to disable the clock when these functions fail. Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate = function") Signed-off-by: Hongling Zeng --- Change in v2: -Add pm_runtime_disable() in error path (reported by Sashiko AI). --- change in v3: -Fix unbalanced clock disable by checking clk_prepare_enable()return valu= e and setting sata_refclk_enabledonly on success. -Fix error path teardown order to match ti_pipe3_remove()(disable clock b= efore disabling runtime PM). --- change in v4: -Fix the patch version --- Change in v5: -Add Fix ignored clock enable return value in init patch --- drivers/phy/ti/phy-ti-pipe3.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index b8c055893742..2d36fe4c4218 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -834,21 +834,39 @@ static int ti_pipe3_probe(struct platform_device *pde= v) */ if (phy->mode =3D=3D PIPE3_MODE_SATA) { if (!IS_ERR(phy->refclk)) { - clk_prepare_enable(phy->refclk); + ret =3D clk_prepare_enable(phy->refclk); + if (ret) { + dev_err(dev, "Failed to enable refclk %d\n", ret); + goto err_pm_disable; + } phy->sata_refclk_enabled =3D true; } } =20 generic_phy =3D devm_phy_create(dev, NULL, &ops); - if (IS_ERR(generic_phy)) - return PTR_ERR(generic_phy); + if (IS_ERR(generic_phy)) { + ret =3D PTR_ERR(generic_phy); + goto err_clk_disable; + } =20 phy_set_drvdata(generic_phy, phy); =20 ti_pipe3_power_off(generic_phy); =20 phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); - return PTR_ERR_OR_ZERO(phy_provider); + if (IS_ERR(phy_provider)) { + ret =3D PTR_ERR(phy_provider); + goto err_clk_disable; + } + + return 0; + +err_clk_disable: + if (phy->sata_refclk_enabled && !IS_ERR(phy->refclk)) + clk_disable_unprepare(phy->refclk); +err_pm_disable: + pm_runtime_disable(dev); + return ret; } =20 static void ti_pipe3_remove(struct platform_device *pdev) --=20 2.25.1 From nobody Mon May 25 05:58:57 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13855208D0 for ; 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Mon, 18 May 2026 14:29:44 +0800 From: Hongling Zeng To: vkoul@kernel.org, neil.armstrong@linaro.org, johan@kernel.org, kishon@kernel.org, rogerq@ti.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, zhongling0719@126.com, Hongling Zeng Subject: [PATCH v5 3/4] phy: ti-pipe3: Fix EPROBE_DEFER handling for clock resources Date: Mon, 18 May 2026 14:29:37 +0800 Message-Id: <20260518062938.48114-4-zenghongling@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260518062938.48114-1-zenghongling@kylinos.cn> References: <20260518062938.48114-1-zenghongling@kylinos.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ti_pipe3_get_clk() has two issues with -EPROBE_DEFER error handling: 1. When devm_clk_get() for sysclk fails, the function returns -EINVAL instead of propagating the actual error code. This masks -EPROBE_DEFER to -EINVAL, breaking the probe deferral mechanism and causing permanent driver initialization failure on systems with non-deterministic probe ordering. 2. For SATA PHY refclk, the function ignores all errors to support older DTBs missing the refclk property. However, this incorrectly ignores -EPROBE_DEFER as well, causing the driver to proceed without waiting for the clock provider to become available. Fix both issues: - Return PTR_ERR(phy->sys_clk) instead of -EINVAL to propagate all error codes including -EPROBE_DEFER - Use devm_clk_get_optional() for SATA refclk to handle optional clocks while propagating -EPROBE_DEFER and other errors Fixes: a70143bbef6b ("drivers: phy: usb3/pipe3: Adapt pipe3 driver to Gener= ic PHY Framework") Fixes: 7f33912d2978 ("phy: ti-pipe3: Fix SATA across suspend/resume") Signed-off-by: Hongling Zeng --- Change in v4: - Merge refclk leak fix and EPROBE_DEFER fix into a single patch - Use devm_clk_get_optional() for SATA refclk - Drop manual -ENOENT handling - Ensure error paths are fully symmetric --- Change in v5: -Add Fix ignored clock enable return value in init patch --- drivers/phy/ti/phy-ti-pipe3.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 2d36fe4c4218..9ec228c2a940 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -608,14 +608,20 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) struct clk *clk; struct device *dev =3D phy->dev; =20 - phy->refclk =3D devm_clk_get(dev, "refclk"); + /* + * refclk is optional for SATA PHY to support older DTBs, but + * required for other modes. Use devm_clk_get_optional() for SATA + * which returns NULL for -ENOENT, allowing us to propagate all + * other errors including -EPROBE_DEFER. + */ + if (phy->mode =3D=3D PIPE3_MODE_SATA) + phy->refclk =3D devm_clk_get_optional(dev, "refclk"); + else + phy->refclk =3D devm_clk_get(dev, "refclk"); + if (IS_ERR(phy->refclk)) { dev_err(dev, "unable to get refclk\n"); - /* older DTBs have missing refclk in SATA PHY - * so don't bail out in case of SATA PHY. - */ - if (phy->mode !=3D PIPE3_MODE_SATA) - return PTR_ERR(phy->refclk); + return PTR_ERR(phy->refclk); } =20 if (phy->mode !=3D PIPE3_MODE_SATA) { @@ -632,7 +638,7 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) phy->sys_clk =3D devm_clk_get(dev, "sysclk"); if (IS_ERR(phy->sys_clk)) { dev_err(dev, "unable to get sysclk\n"); - return -EINVAL; + return PTR_ERR(phy->sys_clk); } } =20 --=20 2.25.1 From nobody Mon May 25 05:58:57 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82BBA37FF68; Mon, 18 May 2026 06:29:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085798; cv=none; b=T/gHW/aRNHv+po+bHSQW3mNS0MUsMpVbvcFcXljzr7s6fx0sbdRmK0lp0WjAB47bqd0LSre1aiFf0W+FTo9yMsI8p+vYBIuTHyVd400l185eZUoaCxjlwKRnuvxOkLEe8yDXHIwIHXvvXZ4lcUDfrFpM5s9omk86AMagbNegvf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779085798; c=relaxed/simple; bh=HJlCY8DOaqDOhKrls2zg5ibUsXi7m2DzGGh/4c+j2bU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=og8Qn2FUkf+MNpE7l6LKmQv+B8I+2iejH+eqxLTsOJizBfUP/vESwOIqv3S+cOncXkA4HLd+It0T0k5V/TizUAwEws3lANnU3UKj8e/+P2V2ZZT27zMg79ax74ymGRLcp7+FGbEkLsgrqzxMq/vB44ipqVyx+KfjydDDfrjc1wY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: f607e8ba528211f1aa26b74ffac11d73-20260518 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:4bb8eabc-56d3-4dfa-a082-a4f92b4d3046,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:e7bac3a,CLOUDID:2cf1c7d3a309c4189b32b605f2a15957,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|850|865|898,TC:nil,Content:0|1 5|50,EDM:-3,IP:nil,URL:99|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: f607e8ba528211f1aa26b74ffac11d73-20260518 X-User: zenghongling@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 2073245212; Mon, 18 May 2026 14:29:45 +0800 From: Hongling Zeng To: vkoul@kernel.org, neil.armstrong@linaro.org, johan@kernel.org, kishon@kernel.org, rogerq@ti.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, zhongling0719@126.com, Hongling Zeng , Sashiko AI , stable@vger.kernel.org Subject: [PATCH v5 4/4] phy: ti-pipe3: Fix clock leak in init error path Date: Mon, 18 May 2026 14:29:38 +0800 Message-Id: <20260518062938.48114-5-zenghongling@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260518062938.48114-1-zenghongling@kylinos.cn> References: <20260518062938.48114-1-zenghongling@kylinos.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When regmap_update_bits() fails in ti_pipe3_init() for PCIe mode, the function returns the error without calling ti_pipe3_disable_clocks(). This leaves the clocks permanently enabled since the PHY framework won't invoke the .exit callback on init failure. Fix this by adding proper clock cleanup in the PCIe error path, consistent with how the DPLL program error path handles cleanup. Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate = function") Reported-by: Sashiko AI Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@smtp.kernel.= org/ Signed-off-by: Hongling Zeng Cc: stable@vger.kernel.org --- Change in v5: -Add Fix ignored clock enable return value in init patch --- drivers/phy/ti/phy-ti-pipe3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 9ec228c2a940..4897e4ba2d7d 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -518,6 +518,8 @@ static int ti_pipe3_init(struct phy *x) val =3D 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; ret =3D regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, PCIE_PCS_MASK, val); + if (ret) + ti_pipe3_disable_clocks(phy); return ret; } =20 --=20 2.25.1