From nobody Mon May 25 09:58:19 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97887353EE5; Mon, 18 May 2026 03:51:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779076280; cv=none; b=e5Pgsx6MJD7b7BQNrIRNFNoAypE0RB1sVeq91Z1KyWz4Ak+idJ9rNm0g5B8p/H4Ui0SDUv0I7uYaYILbUM2CSPO6D5Y28X6yZCVhR92jrNH+eSH4NKkdd2NXY7kKMtJdwXEE3bkrTl5O2e/XA5uLfEZ7yKH9afZPiC5yyjox+6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779076280; c=relaxed/simple; bh=mYI4/Y8zgD9eQltq2KZsNuiUt8OW+Vf5tCiNpDtmugQ=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=h2sLW80T5GZCGVxzV+3et9zXm9eCA5jtw2Ze5Pw8yM+mctPFrr0nYpWBbqthRMazIjWGByWx++O09kwhs2+QiIHDPQg5CNZU7g/inqJOvZZoewMC1R/sGSdOJB1bGUXx6eJhH6FvvUGDKdgH9K7U5ZMIyosoDHOsT6nVAnF8VgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: cec83752526c11f1aa26b74ffac11d73-20260518 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:4d259904-15aa-4066-9d8b-1798aa4239b4,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:e7bac3a,CLOUDID:81117671d00c71f4aed1f1daaac19d9d,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:102|850|865|898,TC:nil,Content:0|15|50,E DM:-3,IP:nil,URL:99|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0, OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: cec83752526c11f1aa26b74ffac11d73-20260518 X-User: zenghongling@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 1849986429; Mon, 18 May 2026 11:51:10 +0800 From: Hongling Zeng To: vkoul@kernel.org, neil.armstrong@linaro.org, johan@kernel.org, kishon@kernel.org, rogerq@ti.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, zhongling0719@126.com, Hongling Zeng , Sashiko AI , stable@vger.kernel.org Subject: [PATCH] phy: ti-pipe3: Fix clock leak in init error path Date: Mon, 18 May 2026 11:51:05 +0800 Message-Id: <20260518035105.26607-1-zenghongling@kylinos.cn> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When regmap_update_bits() fails in ti_pipe3_init() for PCIe mode, the function returns the error without calling ti_pipe3_disable_clocks(). This leaves the clocks permanently enabled since the PHY framework won't invoke the .exit callback on init failure. Fix this by adding proper clock cleanup in the PCIe error path, consistent with how the DPLL program error path handles cleanup. Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate = function") Reported-by: Sashiko AI Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@smtp.kernel.= org/ Signed-off-by: Hongling Zeng Cc: stable@vger.kernel.org --- drivers/phy/ti/phy-ti-pipe3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index e0ab7d21e99c..ba1c937272b1 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -515,6 +515,8 @@ static int ti_pipe3_init(struct phy *x) val =3D 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; ret =3D regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, PCIE_PCS_MASK, val); + if (ret) + ti_pipe3_disable_clocks(phy); return ret; } =20 --=20 2.25.1