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From: Chintan Patel <chintanlike@gmail.com>
To: sumit.semwal@linaro.org,
	neil.armstrong@linaro.org
Cc: dianders@chromium.org,
	jesszhan0024@gmail.com,
	maarten.lankhorst@linux.intel.com,
	mripard@kernel.org,
	tzimmermann@suse.de,
	airlied@gmail.com,
	simona@ffwll.ch,
	dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,
	Chintan Patel <chintanlike@gmail.com>
Subject: [PATCH v2] drm/panel: novatek-nt36672a: Inline panel init sequences
Date: Sun, 17 May 2026 20:42:52 -0700
Message-ID: <20260518034252.16337-1-chintanlike@gmail.com>
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Inline the panel initialization command sequences and remove the
table-based command abstraction used by the NT36672A panel driver.

Replace the nt36672a_panel_cmd tables and nt36672a_send_cmds()
helper with explicit initialization functions using
mipi_dsi_dcs_write_seq_multi() and
mipi_dsi_dcs_write_var_seq_multi() directly.

This improves readability by making the panel programming sequence
explicit in code and allows future sharing of common command
subsequences between panels. It also removes an unnecessary wrapper
around the MIPI DSI helpers.

Additionally, compress repeated register writes into small loops where
appropriate to reduce duplication in the initialization sequences.

Add:
tianma_fhd_video_on_init_1()
tianma_fhd_video_on_init_2()
tianma_fhd_video_off_init()

Update nt36672a_panel_desc to use function pointers for panel init
sequences and invoke them directly from prepare/unprepare paths.

Signed-off-by: Chintan Patel <chintanlike@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v2:
- Replace command tables with explicit init functions
- Remove nt36672a_send_cmds() helper entirely
- Use mipi_dsi_dcs_write_seq_multi() directly
- Use mipi_dsi_dcs_write_var_seq_multi() loops for repeated register writes
- Convert nt36672a_panel_desc command table fields to function pointers
---
 .../gpu/drm/panel/panel-novatek-nt36672a.c    | 522 +++++++-----------
 1 file changed, 186 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d=
rm/panel/panel-novatek-nt36672a.c
index 7e8b5e059575..4c706c6e9b1c 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c
@@ -28,10 +28,6 @@
=20
 #include <video/mipi_display.h>
=20
-struct nt36672a_panel_cmd {
-	const char data[2];
-};
-
 static const char * const nt36672a_regulator_names[] =3D {
 	"vddio",
 	"vddpos",
@@ -55,13 +51,9 @@ struct nt36672a_panel_desc {
 	enum mipi_dsi_pixel_format format;
 	unsigned int lanes;
=20
-	unsigned int num_on_cmds_1;
-	const struct nt36672a_panel_cmd *on_cmds_1;
-	unsigned int num_on_cmds_2;
-	const struct nt36672a_panel_cmd *on_cmds_2;
-
-	unsigned int num_off_cmds;
-	const struct nt36672a_panel_cmd *off_cmds;
+	void (*on_init_1)(struct mipi_dsi_multi_context *dsi_ctx);
+	void (*on_init_2)(struct mipi_dsi_multi_context *dsi_ctx);
+	void (*off_init)(struct mipi_dsi_multi_context *dsi_ctx);
 };
=20
 struct nt36672a_panel {
@@ -79,19 +71,6 @@ static inline struct nt36672a_panel *to_nt36672a_panel(s=
truct drm_panel *panel)
 	return container_of(panel, struct nt36672a_panel, base);
 }
=20
-static void nt36672a_send_cmds(struct mipi_dsi_multi_context *dsi_ctx,
-			       const struct nt36672a_panel_cmd *cmds, int num)
-{
-	unsigned int i;
-
-	for (i =3D 0; i < num; i++) {
-		const struct nt36672a_panel_cmd *cmd =3D &cmds[i];
-
-		/* cmd->data[0] is the DCS command, cmd->data[1] is the parameter */
-		mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd->data, sizeof(cmd->data));
-	}
-}
-
 static void nt36672a_panel_power_off(struct drm_panel *panel)
 {
 	struct nt36672a_panel *pinfo =3D to_nt36672a_panel(panel);
@@ -110,8 +89,8 @@ static int nt36672a_panel_unprepare(struct drm_panel *pa=
nel)
 	struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D pinfo->link };
=20
 	/* send off cmds */
-	nt36672a_send_cmds(&dsi_ctx, pinfo->desc->off_cmds,
-			   pinfo->desc->num_off_cmds);
+	if (pinfo->desc->off_init)
+		pinfo->desc->off_init(&dsi_ctx);
=20
 	/* Reset error to continue with display off even if send_cmds failed */
 	dsi_ctx.accum_err =3D 0;
@@ -162,8 +141,8 @@ static int nt36672a_panel_prepare(struct drm_panel *pan=
el)
 	dsi_ctx.accum_err =3D nt36672a_panel_power_on(pinfo);
=20
 	/* send first part of init cmds */
-	nt36672a_send_cmds(&dsi_ctx, pinfo->desc->on_cmds_1,
-			   pinfo->desc->num_on_cmds_1);
+	if (pinfo->desc->on_init_1)
+		pinfo->desc->on_init_1(&dsi_ctx);
=20
 	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
=20
@@ -173,8 +152,8 @@ static int nt36672a_panel_prepare(struct drm_panel *pan=
el)
 	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
=20
 	/* Send rest of the init cmds */
-	nt36672a_send_cmds(&dsi_ctx, pinfo->desc->on_cmds_2,
-			   pinfo->desc->num_on_cmds_2);
+	if (pinfo->desc->on_init_2)
+		pinfo->desc->on_init_2(&dsi_ctx);
=20
 	mipi_dsi_msleep(&dsi_ctx, 120);
=20
@@ -213,310 +192,184 @@ static const struct drm_panel_funcs panel_funcs =3D=
 {
 	.get_modes =3D nt36672a_panel_get_modes,
 };
=20
-static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_1[] =3D {
+static void tianma_fhd_video_on_init_1(struct mipi_dsi_multi_context *dsi_=
ctx)
+{
+	u8 reg;
+
 	/* skin enhancement mode */
-	{ .data =3D {0xFF, 0x22} },
-	{ .data =3D {0x00, 0x40} },
-	{ .data =3D {0x01, 0xC0} },
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-	{ .data =3D {0x9A, 0x80} },
-	{ .data =3D {0x9B, 0x80} },
-	{ .data =3D {0x9C, 0x80} },
-	{ .data =3D {0x9D, 0x80} },
-	{ .data =3D {0x9E, 0x80} },
-	{ .data =3D {0x9F, 0x80} },
-	{ .data =3D {0xA0, 0x8A} },
-	{ .data =3D {0xA2, 0x80} },
-	{ .data =3D {0xA6, 0x80} },
-	{ .data =3D {0xA7, 0x80} },
-	{ .data =3D {0xA9, 0x80} },
-	{ .data =3D {0xAA, 0x80} },
-	{ .data =3D {0xAB, 0x80} },
-	{ .data =3D {0xAC, 0x80} },
-	{ .data =3D {0xAD, 0x80} },
-	{ .data =3D {0xAE, 0x80} },
-	{ .data =3D {0xAF, 0x80} },
-	{ .data =3D {0xB7, 0x76} },
-	{ .data =3D {0xB8, 0x76} },
-	{ .data =3D {0xB9, 0x05} },
-	{ .data =3D {0xBA, 0x0D} },
-	{ .data =3D {0xBB, 0x14} },
-	{ .data =3D {0xBC, 0x0F} },
-	{ .data =3D {0xBD, 0x18} },
-	{ .data =3D {0xBE, 0x1F} },
-	{ .data =3D {0xBF, 0x05} },
-	{ .data =3D {0xC0, 0x0D} },
-	{ .data =3D {0xC1, 0x14} },
-	{ .data =3D {0xC2, 0x03} },
-	{ .data =3D {0xC3, 0x07} },
-	{ .data =3D {0xC4, 0x0A} },
-	{ .data =3D {0xC5, 0xA0} },
-	{ .data =3D {0xC6, 0x55} },
-	{ .data =3D {0xC7, 0xFF} },
-	{ .data =3D {0xC8, 0x39} },
-	{ .data =3D {0xC9, 0x44} },
-	{ .data =3D {0xCA, 0x12} },
-	{ .data =3D {0xCD, 0x80} },
-	{ .data =3D {0xDB, 0x80} },
-	{ .data =3D {0xDC, 0x80} },
-	{ .data =3D {0xDD, 0x80} },
-	{ .data =3D {0xE0, 0x80} },
-	{ .data =3D {0xE1, 0x80} },
-	{ .data =3D {0xE2, 0x80} },
-	{ .data =3D {0xE3, 0x80} },
-	{ .data =3D {0xE4, 0x80} },
-	{ .data =3D {0xE5, 0x40} },
-	{ .data =3D {0xE6, 0x40} },
-	{ .data =3D {0xE7, 0x40} },
-	{ .data =3D {0xE8, 0x40} },
-	{ .data =3D {0xE9, 0x40} },
-	{ .data =3D {0xEA, 0x40} },
-	{ .data =3D {0xEB, 0x40} },
-	{ .data =3D {0xEC, 0x40} },
-	{ .data =3D {0xED, 0x40} },
-	{ .data =3D {0xEE, 0x40} },
-	{ .data =3D {0xEF, 0x40} },
-	{ .data =3D {0xF0, 0x40} },
-	{ .data =3D {0xF1, 0x40} },
-	{ .data =3D {0xF2, 0x40} },
-	{ .data =3D {0xF3, 0x40} },
-	{ .data =3D {0xF4, 0x40} },
-	{ .data =3D {0xF5, 0x40} },
-	{ .data =3D {0xF6, 0x40} },
-	{ .data =3D {0xFB, 0x1} },
-	{ .data =3D {0xFF, 0x23} },
-	{ .data =3D {0xFB, 0x01} },
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x22);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x00, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0xC0);
+	for (reg =3D 0x02; reg <=3D 0x10; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x11, 0x50);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x12, 0x60);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x13, 0x70);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x14, 0x58);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x15, 0x68);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x16, 0x78);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x17, 0x77);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x18, 0x39);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x19, 0x2D);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1A, 0x2E);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1B, 0x32);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1C, 0x37);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1D, 0x3A);
+	for (reg =3D 0x1E; reg <=3D 0x28; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x00);
+	for (reg =3D 0x2F; reg <=3D 0x3B; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
+	for (reg =3D 0x3F; reg <=3D 0x52; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x53, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x54, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x55, 0xFE);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x56, 0x77);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x58, 0xCD);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x59, 0xD0);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x5A, 0xD0);
+	for (reg =3D 0x5B; reg <=3D 0x6F; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x50);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x70, 0x07);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x71, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x72, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x73, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x74, 0x06);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x75, 0x0C);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x76, 0x03);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x77, 0x09);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x78, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x79, 0x68);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7A, 0x88);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7C, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7D, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7E, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x7F, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x81, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x83, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x84, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x85, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x86, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x87, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x88, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x89, 0x91);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x8A, 0x98);
+	for (reg =3D 0x8B; reg <=3D 0x9F; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xA0, 0x8A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xA2, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xA6, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xA7, 0x80);
+	for (reg =3D 0xA9; reg <=3D 0xAF; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xB7, 0x76);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xB8, 0x76);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xB9, 0x05);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBA, 0x0D);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBB, 0x14);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBC, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBD, 0x18);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBE, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xBF, 0x05);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC0, 0x0D);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC1, 0x14);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC2, 0x03);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC3, 0x07);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC4, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC5, 0xA0);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC6, 0x55);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC7, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC8, 0x39);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC9, 0x44);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xCA, 0x12);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xCD, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDB, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x80);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDD, 0x80);
+	for (reg =3D 0xE0; reg <=3D 0xE4; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x80);
+	for (reg =3D 0xE5; reg <=3D 0xF6; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x23);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
 	/* dimming enable */
-	{ .data =3D {0x01, 0x84} },
-	{ .data =3D {0x05, 0x2D} },
-	{ .data =3D {0x06, 0x00} },
-	 /* resolution 1080*2246 */
-	{ .data =3D {0x11, 0x01} },
-	{ .data =3D {0x12, 0x7B} },
-	{ .data =3D {0x15, 0x6F} },
-	{ .data =3D {0x16, 0x0B} },
-	 /* UI mode */
-	{ .data =3D {0x29, 0x0A} },
-	{ .data =3D {0x30, 0xFF} },
-	{ .data =3D {0x31, 0xFF} },
-	{ .data =3D {0x32, 0xFF} },
-	{ .data =3D {0x33, 0xFF} },
-	{ .data =3D {0x34, 0xFF} },
-	{ .data =3D {0x35, 0xFF} },
-	{ .data =3D {0x36, 0xFF} },
-	{ .data =3D {0x37, 0xFF} },
-	{ .data =3D {0x38, 0xFC} },
-	{ .data =3D {0x39, 0xF8} },
-	{ .data =3D {0x3A, 0xF4} },
-	{ .data =3D {0x3B, 0xF1} },
-	{ .data =3D {0x3D, 0xEE} },
-	{ .data =3D {0x3F, 0xEB} },
-	{ .data =3D {0x40, 0xE8} },
-	{ .data =3D {0x41, 0xE5} },
-	 /* STILL mode */
-	{ .data =3D {0x2A, 0x13} },
-	{ .data =3D {0x45, 0xFF} },
-	{ .data =3D {0x46, 0xFF} },
-	{ .data =3D {0x47, 0xFF} },
-	{ .data =3D {0x48, 0xFF} },
-	{ .data =3D {0x49, 0xFF} },
-	{ .data =3D {0x4A, 0xFF} },
-	{ .data =3D {0x4B, 0xFF} },
-	{ .data =3D {0x4C, 0xFF} },
-	{ .data =3D {0x4D, 0xED} },
-	{ .data =3D {0x4E, 0xD5} },
-	{ .data =3D {0x4F, 0xBF} },
-	{ .data =3D {0x50, 0xA6} },
-	{ .data =3D {0x51, 0x96} },
-	{ .data =3D {0x52, 0x86} },
-	{ .data =3D {0x53, 0x76} },
-	{ .data =3D {0x54, 0x66} },
-	 /* MOVING mode */
-	{ .data =3D {0x2B, 0x0E} },
-	{ .data =3D {0x58, 0xFF} },
-	{ .data =3D {0x59, 0xFF} },
-	{ .data =3D {0x5A, 0xFF} },
-	{ .data =3D {0x5B, 0xFF} },
-	{ .data =3D {0x5C, 0xFF} },
-	{ .data =3D {0x5D, 0xFF} },
-	{ .data =3D {0x5E, 0xFF} },
-	{ .data =3D {0x5F, 0xFF} },
-	{ .data =3D {0x60, 0xF6} },
-	{ .data =3D {0x61, 0xEA} },
-	{ .data =3D {0x62, 0xE1} },
-	{ .data =3D {0x63, 0xD8} },
-	{ .data =3D {0x64, 0xCE} },
-	{ .data =3D {0x65, 0xC3} },
-	{ .data =3D {0x66, 0xBA} },
-	{ .data =3D {0x67, 0xB3} },
-	{ .data =3D {0xFF, 0x25} },
-	{ .data =3D {0xFB, 0x01} },
-	{ .data =3D {0x05, 0x04} },
-	{ .data =3D {0xFF, 0x26} },
-	{ .data =3D {0xFB, 0x01} },
-	{ .data =3D {0x1C, 0xAF} },
-	{ .data =3D {0xFF, 0x10} },
-	{ .data =3D {0xFB, 0x01} },
-	{ .data =3D {0x51, 0xFF} },
-	{ .data =3D {0x53, 0x24} },
-	{ .data =3D {0x55, 0x00} },
-};
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x84);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x05, 0x2D);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x06, 0x00);
+	/* resolution 1080*2246 */
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x11, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x12, 0x7B);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x15, 0x6F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x16, 0x0B);
+	/* UI mode */
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x29, 0x0A);
+	for (reg =3D 0x30; reg <=3D 0x37; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x38, 0xFC);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x39, 0xF8);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3A, 0xF4);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3B, 0xF1);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0xEE);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0xEB);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x40, 0xE8);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x41, 0xE5);
+	/* STILL mode */
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2A, 0x13);
+	for (reg =3D 0x45; reg <=3D 0x4C; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x4D, 0xED);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x4E, 0xD5);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x4F, 0xBF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x50, 0xA6);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x51, 0x96);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x52, 0x86);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x53, 0x76);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x54, 0x66);
+	/* MOVING mode */
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2B, 0x0E);
+	for (reg =3D 0x58; reg <=3D 0x5F; reg++)
+		mipi_dsi_dcs_write_var_seq_multi(dsi_ctx, reg, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x60, 0xF6);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x61, 0xEA);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x62, 0xE1);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x63, 0xD8);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x64, 0xCE);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x65, 0xC3);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x66, 0xBA);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x67, 0xB3);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x25);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x05, 0x04);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x26);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x1C, 0xAF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x10);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x51, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x53, 0x24);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x55, 0x00);
+}
=20
-static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_2[] =3D {
-	{ .data =3D {0xFF, 0x24} },
-	{ .data =3D {0xFB, 0x01} },
-	{ .data =3D {0xC3, 0x01} },
-	{ .data =3D {0xC4, 0x54} },
-	{ .data =3D {0xFF, 0x10} },
-};
+static void tianma_fhd_video_on_init_2(struct mipi_dsi_multi_context *dsi_=
ctx)
+{
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x24);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC3, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC4, 0x54);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x10);
+}
=20
-static const struct nt36672a_panel_cmd tianma_fhd_video_off_cmds[] =3D {
-	{ .data =3D {0xFF, 0x24} },
-	{ .data =3D {0xFB, 0x01} },
-	{ .data =3D {0xC3, 0x01} },
-	{ .data =3D {0xFF, 0x10} },
-};
+static void tianma_fhd_video_off_init(struct mipi_dsi_multi_context *dsi_c=
tx)
+{
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x24);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFB, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xC3, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xFF, 0x10);
+}
=20
 static const struct drm_display_mode tianma_fhd_video_panel_default_mode =
=3D {
 	.clock		=3D 161331,
@@ -546,12 +399,9 @@ static const struct nt36672a_panel_desc tianma_fhd_vid=
eo_panel_desc =3D {
 			| MIPI_DSI_MODE_VIDEO_BURST,
 	.format =3D MIPI_DSI_FMT_RGB888,
 	.lanes =3D 4,
-	.on_cmds_1 =3D tianma_fhd_video_on_cmds_1,
-	.num_on_cmds_1 =3D ARRAY_SIZE(tianma_fhd_video_on_cmds_1),
-	.on_cmds_2 =3D tianma_fhd_video_on_cmds_2,
-	.num_on_cmds_2 =3D ARRAY_SIZE(tianma_fhd_video_on_cmds_2),
-	.off_cmds =3D tianma_fhd_video_off_cmds,
-	.num_off_cmds =3D ARRAY_SIZE(tianma_fhd_video_off_cmds),
+	.on_init_1 =3D tianma_fhd_video_on_init_1,
+	.on_init_2 =3D tianma_fhd_video_on_init_2,
+	.off_init =3D tianma_fhd_video_off_init,
 };
=20
 static int nt36672a_panel_add(struct nt36672a_panel *pinfo)
--=20
2.43.0