From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5FE13A1B5; Mon, 18 May 2026 00:43:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065042; cv=none; b=Ow+jwJCZPkmlq0/2fNwFOvexYaJTHt9/+1b8EmVNPOZcG7IeKBFqNI7uYd7uXotb+xAF3K5Jkpx4NxsHpXVWQWcUG4ofH63siC7iirUFL4xdz1yzX2fTy2fv5ky2RtNJax0vRsQWu4IZLdbUbRaKBgAuF1Mjk+owVRg/jFFF8Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065042; c=relaxed/simple; bh=JfYVBKfwJuxtma2lzdMXINx6rDMMHn85ybTodOf74x4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IUJlJpvLGEovdKFsky2flFusRvidG+thyZ4yzUJuVo4W3N61OI5jtknySLSLVFZP9PSh2ZdL96bDozLrlZ6L2PqfOEh7ZAPOCCMdKtH42UZxHCGpp2S/CmoWsMPhGamF3Yi0Tre8rlNiR5SiJOZ+lNzxvWwrIt9pRJuA7wKFJUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=jrtk3yyV; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jrtk3yyV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=li bXhe/4t1biWmfrc6stRZt7aayY7R8wQ9CZqvdPLA0=; b=jrtk3yyVD5Ff/hj2W7 L46KQXVPLqg2pjC5ffYX3OSmBXJfUetP01uJQGLkzTa71oGkmly2FGM6WSqgbYfL MmatVnaGSN6swkZ/A5pJukYmWN9ID/jdRTJEJmBFXMf8QEW0vUAkvUfVuMs9Nip4 mES+1Y9/gtMRd3zCW4v/1Cx84= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S3; Mon, 18 May 2026 08:42:52 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 1/7] PCI: Add pci_host_common_link_train_delay() helper Date: Mon, 18 May 2026 08:42:40 +0800 Message-ID: <20260518004246.1384532-2-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cr15uw48KryxGryDtF4fZrb_yoW8CFyrpa 98AF13CF40grW3uwsxAa4DWry5X3Z5t3yUK397G3sayr9rtrsavFWvg3yIqF1rJFZ8Zr17 A3W5K3Z7Cr4xtF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziqXdrUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6w1Y+2oKYI2yDQAA33 Content-Type: text/plain; charset="utf-8" PCIe r6.0, sec 6.6.1 (Conventional Reset) requires that for a Downstream Port supporting Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending any Configuration Request. Introduce a static inline helper pci_host_common_link_train_delay() that checks the given max_link_speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s, etc.) and calls msleep(100) only when the speed is greater than 5.0 GT/s. This allows multiple host controller drivers to share the same mandatory delay without duplicating the logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pci-host-common.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h index b5075d4bd7eb..d709f7e3e11a 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -10,6 +10,9 @@ #ifndef _PCI_HOST_COMMON_H #define _PCI_HOST_COMMON_H =20 +#include +#include "../pci.h" + struct pci_ecam_ops; =20 int pci_host_common_probe(struct platform_device *pdev); @@ -20,4 +23,18 @@ void pci_host_common_remove(struct platform_device *pdev= ); =20 struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); + +/** + * pci_host_common_link_train_delay - Wait 100 ms if link speed > 5 GT/s + * @max_link_speed: the maximum link speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s= , ...) + * + * Must be called after Link training completes and before the first + * Configuration Request is sent. + */ +static inline void pci_host_common_link_train_delay(int max_link_speed) +{ + if (max_link_speed > 2) + msleep(PCIE_RESET_CONFIG_WAIT_MS); +} + #endif --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B9E412E1DC; Mon, 18 May 2026 00:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065043; cv=none; b=Cr5clasZTxWIM4mEeLx66excdFM33vaH17vBfDLffxKxyZ3J0/D1aibtLB0DOWcQV6BEFts2FdS1HkekM6sIhCOSUvHmb72fcBknfgtVGgixCsohv7Jz+0E4NiSKLtRQPDs6W/IKQcfJ8hQ3CwfNFv0Ukwrr3+ne7vXF5eanOKE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065043; c=relaxed/simple; bh=lQyn9D4U5WvqWBnatkUYn5Y2YqHoCSLoRXPaXquEoJI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RErG2TseNd6zLRPYPQFe5WOqQod5kpBMDShzYvx8LaaDw6Ar5a981dtGXWHxjI1vNmJlViJgwGsh8Il78IvFOY6gGt2h5ts/jKXnJDDJAmdHrabGpVpUWabNyzxUiqXtfvCuQNBM+AqzdFVZU9FoHwwOOVq/5JGhGH0S18px/+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=mGngdtKn; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="mGngdtKn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=3F 13ZakzR2RSsT1F2D7I1CFIuqoD/ehoB7Hh/Xe6CP8=; b=mGngdtKnqDAYiq0K16 nFCreG2iac289umqPMc5xdw6O9eQ8A/tTy9F4jh86kP+Ikp3Xo+8CE0OfEKZVOTG ZZglwnzSL6RnCAxofrkWYE0Vi0cPFG3EOLsXmYVJgfAr51gFf8BsiTfxi143X3Dq XC+T8FU0ZMky3J9m8qrHhO+/M= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S4; Mon, 18 May 2026 08:42:53 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 2/7] PCI: cadence: Add post-link delay for LGA and j721e glue driver Date: Mon, 18 May 2026 08:42:41 +0800 Message-ID: <20260518004246.1384532-3-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxGFWUWFyktFy3trW5Ar4fXwb_yoWrCF4fpa yUGFyfG3WIqrWY9a1kZ3WUXryaqFn8A3srJ3929w1xWF17Cr98JF42gF1fJFZxKrZrAr17 ZF1DtF9rGr1ayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRwjjkUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7A5Y+2oKYI65OgAA3M Content-Type: text/plain; charset="utf-8" The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1. Add a 'max_link_speed' field to struct cdns_pcie. In the common host layer function cdns_pcie_host_start_link(), after the link has been successfully established, call pci_host_common_link_train_delay() to insert the required delay. For the j721e glue driver, set cdns_pcie.max_link_speed from the existing link speed logic. For other LGA-based glue drivers (sky1, sg2042), the common LGA host setup (pcie-cadence-host.c) provides a fallback reading of the device tree property "max-link-speed" when available. This ensures that the delay is not missed on those platforms once they enable the property. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-j721e.c | 1 + drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ 4 files changed, 11 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index bfdfe98d5aba..ae916e7b1927 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie = *pcie, (pcie_get_link_speed(link_speed) =3D=3D PCI_SPEED_UNKNOWN)) link_speed =3D 2; =20 + pcie->cdns_pcie->max_link_speed =3D link_speed; val =3D link_speed - 1; ret =3D regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..18e4b6c760b5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -14,6 +14,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../pci-host-common.h" =20 #define LINK_RETRAIN_TIMEOUT HZ =20 @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, if (!ret && rc->quirk_retrain_flag) ret =3D cdns_pcie_retrain(pcie, pcie_link_up); =20 + if (!ret) + pci_host_common_link_train_delay(pcie->max_link_speed); + return ret; } EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 0bc9e6e90e0e..058e4e619654 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -13,6 +13,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../../pci.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -397,6 +398,9 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) rc->device_id =3D 0xffff; of_property_read_u32(np, "device-id", &rc->device_id); =20 + if (pcie->max_link_speed < 1) + pcie->max_link_speed =3D of_pci_get_max_link_speed(np); + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); if (IS_ERR(pcie->reg_base)) { dev_err(dev, "missing \"reg\"\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 574e9cf4d003..042a4c49bb9a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data { * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + * @max_link_speed: Maximum supported link speed */ struct cdns_pcie { void __iomem *reg_base; @@ -98,6 +99,7 @@ struct cdns_pcie { struct device_link **link; const struct cdns_pcie_ops *ops; const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + int max_link_speed; }; =20 /** --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6548422A80D; Mon, 18 May 2026 00:44:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065054; cv=none; b=dhUvYC2PaHWFnl43Q52LHOtP5sEwq7GFAQ0FgRWNZo7FQpxCDiboFyXd+JT7SehGjlFFjxYuBOAhb57v78R+GJvX+AzGTevJBG89uSnhVE9kB/Iib26hbmps4a7osYoyAVSH8jkPjVHpAPLzJLP6vWljDKeuo5joySS1RlVatt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065054; c=relaxed/simple; bh=YmjpV2/XYxF3z2VOf693ppznOWPaMwkQGcAST0O6rl8=; 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(unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S5; Mon, 18 May 2026 08:42:54 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 3/7] PCI: cadence: HPA: Add post-link delay Date: Mon, 18 May 2026 08:42:42 +0800 Message-ID: <20260518004246.1384532-4-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZF1xur48Kr4kAr43WF4Uurg_yoW8tFyxpa 4DWFyfGF18Xr4Y9an3Aa45XryaqFn8A39rt3yv9w1xZrnrCr4DtFnFgF1xWa43KFZrAr17 J3ZrtF9rGr15ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UoWl9UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCww9Y+2oKYI8OGwAA31 Content-Type: text/plain; charset="utf-8" The Cadence HPA (High Performance Architecture IP) specific link setup function cdns_pcie_hpa_host_link_setup() waits for the link to come up but does not implement the required 100 ms delay after link training completes for speeds > 5.0 GT/s (PCIe r6.0 sec 6.6.1). Add a call to pci_host_common_link_train_delay() immediately after the link is confirmed to be up, using the max_link_speed field. Also, in the HPA host setup function, read the device tree property "max-link-speed" to initialize max_link_speed if not already set by a glue driver. This ensures compliance for HPA-based platforms. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pcie-cadence-host-hpa.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c index 0f540bed58e8..8ef58ed01daa 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -15,6 +15,8 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../pci-host-common.h" +#include "../../pci.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x3F, @@ -304,6 +306,8 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *= rc) ret =3D cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); if (ret) dev_dbg(dev, "PCIe link never came up\n"); + else + pci_host_common_link_train_delay(pcie->max_link_speed); =20 return ret; } @@ -313,6 +317,7 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) { struct device *dev =3D rc->pcie.dev; struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; struct pci_host_bridge *bridge; enum cdns_pcie_rp_bar bar; struct cdns_pcie *pcie; @@ -343,6 +348,9 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) rc->cfg_res =3D res; } =20 + if (pcie->max_link_speed < 1) + pcie->max_link_speed =3D of_pci_get_max_link_speed(np); + /* Put EROM Bar aperture to 0 */ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); =20 --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A94EAC7; Mon, 18 May 2026 00:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065054; cv=none; b=p02Geen7xxxmcYZB1ICCqTGr9pPGR1gb+R47VXUGDBWgv9qoHszd0x/0+M2hyoxJinM3cMuKSrqmoaZavm1vyREItejx+CNmcf1fgDTIjFcZaSHisI/+CiMEqDdIbQL+lAykLn/gTuHqzhI94bzGQ2phfkgCiPWTVmGF2W2Zt5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065054; c=relaxed/simple; bh=JNqsQVGrqXVIhCFc1/rakDaWxKWTPahhzDboC+V8smk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N/ApshvPB3sEpzvInYcXWhPyl80nlRKb3jBkMYXKrochftDzaZ46kp/vwAB5sXE5Dz2BmCAhtdSjc19K1J9AqZGfJ9ISBgSVX6svqBssP9uf8Vyb94NMEUwphFr54buEt5NQzdt+S/pg/yYsY0sJPulcNTBu6oax9ztxiuGvquI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=OBLktX/Q; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="OBLktX/Q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=W+ iY+H9j+f9PNzUKxRBrw9mP4VotmbR1fEw7bGSFMtw=; b=OBLktX/QL1bp7nppSR ss9udT5vHbDCnQASRX6xyJ0KggrTktln+//elEXxBio0h5GBIhcmQVPO+GTBXpQk /oPY4pdYvX0Wm+KGsrdpecPvExDTH1Ujzrl67oDS0YWbeGrZX20QDgVTMoQAu7jo AcePIw/zKbbRpF6KJ5N3P6i2I= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S6; Mon, 18 May 2026 08:42:55 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 4/7] PCI: dwc: Use common pci_host_common_link_train_delay() helper Date: Mon, 18 May 2026 08:42:43 +0800 Message-ID: <20260518004246.1384532-5-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7tw1rAFW5Cry3Wr45ArWxXrb_yoW8Xw15pa 98AFWFyFWrJF43uanrCasxZry5X3Z8Cay7GFZaga4fZa47ArZFqw10g34SqFyxJrZFvr1a 9r17tFnrGw48AF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziSfO3UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xBZ-GoKYJCycwAA3P Content-Type: text/plain; charset="utf-8" The DWC driver already implements the 100 ms delay required by PCIe r6.0 sec 6.6.1 by checking pci->max_link_speed and calling msleep(100). Replace the open-coded msleep() with the new common helper pci_host_common_link_train_delay() to reduce code duplication and improve maintainability. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c11cf61b8319..7021d21bb601 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -22,6 +22,7 @@ #include #include =20 +#include "../pci-host-common.h" #include "../../pci.h" #include "pcie-designware.h" =20 @@ -799,13 +800,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) return -ETIMEDOUT; } =20 - /* - * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link - * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms - * after Link training completes before sending a Configuration Request. - */ - if (pci->max_link_speed > 2) - msleep(PCIE_RESET_CONFIG_WAIT_MS); + pci_host_common_link_train_delay(pci->max_link_speed); =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77DA5140E5F; Mon, 18 May 2026 00:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065043; cv=none; b=LMYuCK243YPvasjTkACaSIZlXDng8yNsPL6MzO6dmmEgEoTwMXsaGbDae4PwAZdIAWPsJln6TPLwrJhWC3dokdSKiPIqYHFRMejUFsGhsV/nMMgjSP93auXTS+4I1WRoxhhtULplsCb1vY6uRhk2bt3ZQ02b+fBjdxPCUrfftBk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065043; c=relaxed/simple; bh=muHbfrRpIVSSxtoi0GG0IRPpos+mmnyB5QlBbAm9EwI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eHV2++VPgC5BECMx184k+WGoSISePcqc/awqK11HSpiAhn/SiT0RnvB7e+qJydPloag99s7P8AJHrvgjgInyS3Z6EmXDNWYEvamKvdIBa1ETUd7SxLk6QQJcpB5T7yqs5hbCOSlkMrfNssWXdeTbYTDMUug+oStdes7W+ScafaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=qFIrxqYl; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="qFIrxqYl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=UP Hg3PhRQ/iRlu2JQO+wt+J//uW4Lc+cTIqd/znwy0w=; b=qFIrxqYlAAyOpwBXPR wvEMCmwLAi4HbuXJMO9BsujHYMAnbT/IPoQy9JYunlrEkMEBRLlA5FMO/HrBbLD0 78xKL1YydB75uknp+oIB+XCvLjlgVdCPl4cK9gluy33ugXFyXd31+EFIg8aLP/Yv JuZklAWk1+0XZdEMjjg5/P4Ok= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S7; Mon, 18 May 2026 08:42:56 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 5/7] PCI: aardvark: Add 100 ms delay after link training Date: Mon, 18 May 2026 08:42:44 +0800 Message-ID: <20260518004246.1384532-6-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFWfGF4fJw1UXryftF1fZwb_yoW8GFWrpa y3CrZrJrs5tr43ua17Aa4fWFy3Wan0ka47Jr92gw13ZFnrKryUJr1jk3sagF17ArWvvr13 Ca43t3Z3Gr43XFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziSfO3UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwxFZ-GoKYJEOSwAA3j Content-Type: text/plain; charset="utf-8" The Aardvark PCIe controller driver waits for the link to come up but does not implement the mandatory 100 ms delay after link training completes for speeds greater than 5.0 GT/s (PCIe r6.0 sec 6.6.1). The driver already maintains a 'link_gen' field that holds the negotiated link speed. Use it together with pci_host_common_link_train_delay() to insert the required delay immediately after confirming that the link is up. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pci-aardvark.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index e34bea1ff0ac..fd9c7d53e8a7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -26,6 +26,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" #include "../pci-bridge-emul.h" =20 @@ -350,8 +351,10 @@ static int advk_pcie_wait_for_link(struct advk_pcie *p= cie) =20 /* check if the link is up or not */ for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (advk_pcie_link_up(pcie)) + if (advk_pcie_link_up(pcie)) { + pci_host_common_link_train_delay(pcie->link_gen); return 0; + } =20 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); } --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A369C1C5D59; Mon, 18 May 2026 00:44:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065044; cv=none; b=FPfMmDsHMIR+kmp1ImZ/YGufpMX2lN0wttqSS28tyGIr8AyB+dMFSlm/m6br2SE3u0B/8+K79DyROvpcqJMi5y1upUdAaB4dxFsk8CX223DR8yVGCBD2E5YpDFk9Qsxrp+ZZAGviIvfqmgHa09eR76jb9WKLC3nvMEHFRptU06s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065044; c=relaxed/simple; bh=FGzBDwThUWkuoKwHocii3mtJMxt3D6WApYRlPWjuAZk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p+jSqeXsy+OiMbNHAKjQMtTxGWc9oF+J7hikA0QaC34I7oIW0RHk6bXRyXxp2lFv+9bjY39ghFYMFzuaoOPaJgbdJpYDU8nmgSVr4cgB8tjHAc9v9Lbg7RK3Ka4zMOLCT632Quv/u2WjVU5LQeVlHiPW9voAySgEJ6Sun5uGROs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Kg0XnWrh; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Kg0XnWrh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=dW IpNo104u5obDhE2dFSS+vTm/NpbYqoKeVdxuNBDUQ=; b=Kg0XnWrhG94E8cn/Lz /WyFaa3U0hSIji8sl2XD+x6cLiLCwlkvZY4Zilc6jonLn8xnjzGFLgYcSEeYH7I3 UwlXEnQ7XdqPoTBtDvZmZb1djo7KEV/8cCl3I37cMvYSTTMhuJeQTXQLcFFi/Imj rXar4CEBKA8KbXesMHGuZZXFI= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S8; Mon, 18 May 2026 08:42:58 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 6/7] PCI: mediatek-gen3: Add 100 ms delay after link up Date: Mon, 18 May 2026 08:42:45 +0800 Message-ID: <20260518004246.1384532-7-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S8 X-Coremail-Antispam: 1Uf129KBjvdXoW7Jr4kWw4fAw18WF4rJF1kZrb_yoWkKrcE9a yxZFWfZayjkrySkFnayFyrZr9Yy3s7Wr10qF4fKF13Aa48urn0qr9avryDAF4kGw43tF12 yryqk3W8WrykCjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRKCJmDUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBJZ-GoKYJIFsAAA3U Content-Type: text/plain; charset="utf-8" The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0 sec 6.6.1. The driver already stores max_link_speed (from the device tree). After mtk_pcie_startup_port() successfully brings up the link, call pci_host_common_link_train_delay() to comply with the specification. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-mediatek-gen3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b0accd828589..5abddec4e9be 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -30,6 +30,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" =20 #define PCIE_BASE_CFG_REG 0x14 @@ -570,6 +571,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *= pcie) goto err_power_down_device; } =20 + pci_host_common_link_train_delay(pcie->max_link_speed); + return 0; =20 err_power_down_device: --=20 2.43.0 From nobody Mon May 25 05:55:53 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7484EAC7; Mon, 18 May 2026 00:43:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065041; cv=none; b=B+2+habToeVD0Kh/ydoNz8qhlJ5RSIg+590uEck+qUJ2shEug6kIRwRvY6QGguU+J/oJYgGXSWJ6gDOpPf62VIAtUNF3r7dqyvaHaim5vfOJuyKzQZOw9B1C0DKSY5zrmXrDJqSgdJdGs1B81k79zdlDkXvTPmifAY+89RxTmT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779065041; c=relaxed/simple; bh=YMFxhFiHQCoBwAI9kaRzLeDfcBldTXfL6lQVRUaOm0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mqgHLOtGGPAypJRFa8RPfrCWCnFPOLUJfnPd5hBtVbIxurQWCl3wGWYvGJq0BLVfPsBYsU1rm8pjmKslnbRVKvZJnW80ei1YHRCxw1We/7yEpn9okoKtwQNbknv8lWeBpUjSxfSTY0h4yJLBWmHUGK8/1AEbDFUrxEDauN4y1Y0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=GWuKyRrO; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="GWuKyRrO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=hc ZbWnpqTBBcWyQnhfBBodfgLLsigOVlRE5RikKEkBI=; b=GWuKyRrOy6UuE8O7C/ HsxV6xT1jpXNS6oE2G8VvdtpN4yzBb8zpUjDnS9xyQNZfU5W9jKs4PM1zlq+wx0C vHbMthlX/Cfnjdop1OxjfOmeFx1PCiyjhao+r7smSrO5phZanDIqhU8VhWwoXH9g WLqP4qvUXHAZ8uKhxPFzHbmWw= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wCnj6SIYApq2fikCA--.4779S9; Mon, 18 May 2026 08:42:59 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v4 7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper Date: Mon, 18 May 2026 08:42:46 +0800 Message-ID: <20260518004246.1384532-8-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnj6SIYApq2fikCA--.4779S9 X-Coremail-Antispam: 1Uf129KBjvdXoW7JFy7uw17AFWrCFyDAry7KFg_yoWkArg_u3 47CF9rAw45Kr9xCF12v3ySvFyYya4Iqr1jga1rK3W3Jay2yFnYywn7ZFs0yr15u3W7J342 vrykCa48CryfCjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRMfOztUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBNZ-GoKYJMF0AAA30 Content-Type: text/plain; charset="utf-8" Replace the unconditional msleep(100) with the common helper pci_host_common_link_train_delay(). The helper only waits when max_link_speed > 2, as required by PCIe r6.0 sec 6.6.1. This avoids unnecessary delay for Gen1/Gen2 links while retaining the mandatory 100 ms for higher speeds. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-rzg3s-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index d86e7516dcc2..66f687304c1c 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -35,6 +35,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" =20 /* AXI registers */ @@ -1663,7 +1664,7 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, if (ret) dev_info(dev, "Failed to set max link speed\n"); =20 - msleep(PCIE_RESET_CONFIG_WAIT_MS); + pci_host_common_link_train_delay(host->max_link_speed); =20 return 0; =20 --=20 2.43.0