From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48B5634E754 for ; Tue, 19 May 2026 05:47:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169645; cv=none; b=LKAS+Yz3eegCAfVFUUHArKXw9JP8L6PvwHKX4vmcTAR7JjNKdu2NPY/JRowGftGr/YOGTukEkCHKUdJgR71SCSABVgZihxWJgOkFMzc8I42B1z9wjilYLeaQgSwrT/ET0oAf/8g2GAnPUHU9SAQXWV38PMSbfmoWSoPP6CbOAQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169645; c=relaxed/simple; bh=/GzJSMoS9msbAtJPMhiojx/3pCxgRir7RfY8D/ogF4k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PM/+Ckg+9ES7ekeJasD5fPSVpvfaXIRllmy14KS/BIz7YSJmSyaIZaX/5hdsmC3R5cr/OJazhVUJCyPEwUwHTRypNORqr4iNkVSYf27ojJ7lY75Eo1AJa7aVTRTAeaSThL6duYcJ5LKraxFzzjuwO02Hg0Sn6V2kIN42EwT1uQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ZTap0Nj5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=iY6kgxBR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ZTap0Nj5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="iY6kgxBR" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64ILwEq42891748 for ; Tue, 19 May 2026 05:47:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= B0O0IEIIuy7vAzmzRp9+03b/boaEZMZFLkZCHHXQ2fg=; b=ZTap0Nj57umfjt2B kcob8186W3p4l6tgUTyXbxQGnVr34MuzyqqTfIKD38pGP2X+xTHT4UCI7mOQixoJ eSZqQN3wUyeHgigsq/bxGj1L0m/EaHrTghaop4drNtpOjX3jhu3vDrO6T+enSCz5 Szj6ad0TYWGKKi/ZW6zmcGbnqTFEDo9bNU43fcIoxHhivQQhmZdOjncvOJFnxkhS Ytwl/55LGF/x87R1zWxLRUbCJ6JjvDglBpam8Ef3DPyjp3AqDlgKg9ZuVUCWXIbr TM//Q4bIsU6MLhxkXQMaqIENnreaQqYarGx7Xy3L6h26v6so2rBPHa30PktRdN4b SAsEZA== Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e7xk1ckvn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:23 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-2ee1da7a13fso3915037eec.1 for ; Mon, 18 May 2026 22:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169643; x=1779774443; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B0O0IEIIuy7vAzmzRp9+03b/boaEZMZFLkZCHHXQ2fg=; b=iY6kgxBRXsDduwU+XDeomAoohf+6+mM/5eZWwxKiAeYQu9Ls3MePYJ5+qFPIGe384d hRnKBWKbCitRbyXWF5zeycAaw0nmQaxeBIoS5uSQSd3HdvKbRGJQ74FyDCss3ufDu9kX K61rYz8k5ZVBdi3RrtzAvl4xkKtc9qJJlpn0DjhBpyXnJL6+sGGzhk6yvz8s96ss+XEv tcbvxxOd5R5jayAmIO5joytoMTiG9Xe7cCmBo8s48S4dSCco6MdLLMs6WQWFFbMShAy3 bSKpkeKdpi2xNKLtc+KqHRiO2LNeCP4M6/3W4vLXxUsYSIpcNUXgG9PHZfwFggGCTYoV hAgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169643; x=1779774443; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=B0O0IEIIuy7vAzmzRp9+03b/boaEZMZFLkZCHHXQ2fg=; b=AG1ZUMa/rTyrr5hs+jcWdncT33l9jqad1nae12Nv0dsxVVuns5ujbAoFTF3xE68ori lZiPgBqDHfc7ykR7/FS1BbwQy91LTsl9SIVrKnwoKpyQd7U5NLvST1il6oYq8mhbhDB+ 9KeMeXdFBZR1yqFwBRhxdeqqY6sUDitCQwXj4GlNXAMZTdBgX0s1rgJElPLLaDsazYRH YgnqdOOMgCD/2IDaBK88ZWFFruILNGSyeijcJuuamOrsII0y0lAjb0ZBe5/tqBEswwSg 1E2is8QU0otKmOWX8fJ6n4ooqMmUe37KNgzRcNolFC7syUKn3BtIfkpcIJFOMVgbjK23 wUDg== X-Forwarded-Encrypted: i=1; AFNElJ/9tL0XbYsBWi3Vpw6e6jA+dWAXK0BUN1t/utSu1GvVQ2K4b4oPoyCkvqpk1u84ZLTjQcK1ZjdrLWRKMvI=@vger.kernel.org X-Gm-Message-State: AOJu0YwqToJEzbnfndZqU6KIGD0FqccgB06KZY/XH2RtpyFuTa53Ot3B W94v6f+xvnbGnYjjq8YmLzHyJAe+us2lqd3NxCEM1yWnDz5Ftyu9jkNi05AtknBJ5E/CP3ALa26 riGmRbb1+8WLc26trwNZ74kxfyzxFW82xhxVh1LcdRMD7EIOWnnmtbBdbymCL6lS9Jng= X-Gm-Gg: Acq92OFE7KDCZkhJXxlw9UdyibEVxb28OGmq8h050zddXafeW6Rl2+BX/EAjEOmHk7F idsxsJQQ0e7Cx12S7EikYQ+LBF165EiMdUZQkNNHff9DBlfoYTGGtM7K9NnqdrdJSR+j+S4eutQ jlnHn1hYI68LQ1zBp1JJhL4p9bdYr8EC1AJ9LNUalVQ6Iy+eZ9a6xUneuHFQi0MEFIN56Wwi/2I KKCsfwyawePGQCkdEWMQwdJyZAtfL4/3buc9jvzCV6E5yAIH1rVrqY9z7y7UvHUVi9NZoZCm6qT AphmYMxNoVR2ZfYVQqSb1gKLZ1chWIP18BIZBLjbCAV7vzgYNI6DjZ3a3PJrobtmOXY9JXxlz6Z tDfbMxWXgxb3ZtQR/7UqweODZis5zV4O6T1Op1XueBq5PBmY+Qsr6RwF0GM08+WdRmGZV X-Received: by 2002:a05:7300:8b95:b0:2e0:1f09:d924 with SMTP id 5a478bee46e88-3039813cab5mr8494404eec.5.1779169642594; Mon, 18 May 2026 22:47:22 -0700 (PDT) X-Received: by 2002:a05:7300:8b95:b0:2e0:1f09:d924 with SMTP id 5a478bee46e88-3039813cab5mr8494379eec.5.1779169641875; Mon, 18 May 2026 22:47:21 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:21 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:12 -0700 Subject: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-1-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=6963; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=/GzJSMoS9msbAtJPMhiojx/3pCxgRir7RfY8D/ogF4k=; b=KgruVv6cFJ5PFUCqlCf6ohCZdOolIp7KX7leRvFDn+Z3pnbdwhuShekuUrmk8p48yUcIBrD/Z NUUzCxoL1fZB1aKAxH/vkl+NJ4PHcd3fVDuFb7xeQpt+Rt7uohKQgcU X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: AAMfUJcqToBgnvQmJxNRC8wTYrQImsmI X-Proofpoint-ORIG-GUID: AAMfUJcqToBgnvQmJxNRC8wTYrQImsmI X-Authority-Analysis: v=2.4 cv=BICDalQG c=1 sm=1 tr=0 ts=6a0bf96b cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=3VQrzie0oMwTYjLhUJMA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXyQJX6U0ky/bg LrQnFWSQxnZRpG4tGwvChBolg2xjLD9NTLI8Sl4JVZ2/H/Wa3MQm16oqQ4I7YCsNYxE6ZqItVT9 1HCryeLOlz6lymFWRqvkcxrNr5Gf5a6/cKMwu4pe9XjeD36OmGydsB/PVjqQ2W99KE+vXe/DVh0 200G1svi0jr8lVaXH3p/CoNyg1fqHIrOvzyvS0Zs5xgmQOUOduA6mRtLgAExlnsX3ACMxNEQBDt 8x4gbd7axhgGIKMc/q/nM2TJGxgxhWkO0mw6wV9g/RXHNsOsiXf2CJbCoC3NBSssOlyp5lP2DZb SqlvHUPEiUi+o3Pn8vKC5pNIVvDxuCNMfjAEvLN4TUPh1ZLSgicW9qFQWui2cTARYG+1DgKaQk3 /KQ4PSrC46uKCCjOz7ZjRUt6hZ5TY3LUOhWJPvx0Jiu3ntVChhBo5HR5rr8PJyRLtJ787PwcfWT rOzbnR4TSdzQ6YUP5+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the PCIe3a/PCIe3b controllers. This block supports two link modes: 1. x4+x4: two 4-lane PHY instances are exposed 2. x8: one 8-lane PHY instance is exposed Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and document the new link-mode property, which selects the active link mode via a TCSR syscon register. Document the required clocks, resets, and power-domains for both PHY instances active in x8 mode. Use #phy-cells =3D <1> for this compatible, where the cell value is the PHY index within the active link mode. Signed-off-by: Qiang Yu --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 140 +++++++++++++++++= +--- 1 file changed, 126 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3a35120a77ec..5877e40244ba 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -58,7 +59,7 @@ properties: =20 clocks: minItems: 5 - maxItems: 6 + maxItems: 10 =20 clock-names: minItems: 5 @@ -68,20 +69,29 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [pipediv2, phy_b_aux] + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b =20 power-domains: - maxItems: 1 + minItems: 1 + items: + - description: PCIe PHY power domain. + - description: Additional PCIe PHY power domain (if present). =20 resets: minItems: 1 - maxItems: 2 + maxItems: 4 =20 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr =20 vdda-phy-supply: true =20 @@ -98,13 +108,29 @@ properties: - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY =20 + qcom,link-mode: + description: + Configures the link mode of the PCIe PHY. Some PHYs support multiple + link modes, such as a single x8 link or two independent x4 links. The + link mode selection is performed by writing to a register in the TCSR + syscon, specified as a phandle to the syscon, the register offset, a= nd + the link mode value. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of link mode register + - description: link mode value + "#clock-cells": true =20 clock-output-names: - maxItems: 1 + minItems: 1 + items: + - description: Name of the first pipe clock output. + - description: Name of the second pipe clock output (if present). =20 - "#phy-cells": - const: 0 + "#phy-cells": true =20 required: - compatible @@ -130,19 +156,40 @@ allOf: - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1p42100-qmp-gen4x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy then: properties: reg: items: - description: port a - description: port b - required: - - qcom,4ln-config-sel else: properties: reg: maxItems: 1 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy + then: + required: + - qcom,4ln-config-sel + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + required: + - qcom,link-mode + - if: properties: compatible: @@ -198,8 +245,40 @@ allOf: properties: clocks: minItems: 6 + maxItems: 6 clock-names: minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + clocks: + minItems: 10 + maxItems: 10 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: phy_b_aux + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b + power-domains: + minItems: 2 + else: + properties: + power-domains: + maxItems: 1 =20 - if: properties: @@ -223,11 +302,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 =20 - if: properties: @@ -237,6 +329,7 @@ allOf: - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy then: properties: "#clock-cells": @@ -246,6 +339,25 @@ allOf: "#clock-cells": const: 0 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + clock-output-names: + minItems: 2 + "#phy-cells": + const: 1 + else: + properties: + clock-output-names: + maxItems: 1 + "#phy-cells": + const: 0 + examples: - | #include --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7F7034E777 for ; Tue, 19 May 2026 05:47:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169646; cv=none; b=m9RO6As2X4ZG2mTb4tInjItei+BiYTtun+ZG7BX28h3a4SFOKBKzzIC9Sx5SPWC74IeiIXXfxzfnuhlEQupxMKNRLdQ+VdZTefAqDLGDcHc4oyP1LjUvA66frV+KKfKkQQnRf8tvKd2vqjSjnK3oqKTRiKGtQehiipEmgTgwxLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169646; c=relaxed/simple; bh=LGL4VHxqKITnhSL7axVc8uFn3R+u5JVC+56a547NSCM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ai2spX0wfoRPGAUxzQgAVL+YF4TDAbYVQc90mEe99pas/Xok1Tn79tkcAfO74/s7PN8VewZmfAa0kja9UHA8zeIkZ4XCwSVjr00mOlPNH4/DKeAkTmQe1uFxmxVojak4OLadKJ2zIoZGKDmiaLdTiALTuDUwVApStUfBWN/uP78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ivDzhSe2; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=X+JyzM90; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ivDzhSe2"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="X+JyzM90" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J5WOZS4131347 for ; Tue, 19 May 2026 05:47:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VZ0NwMyzJUB2GQ7WiRH1btiCyEC/1XQsRKRIRIi2gqw=; b=ivDzhSe2Nl7+MLrD QPsmkAixAxCKAGIhTthgVrTiy7Oia7h6wbWrl7zoZ5r0OBs1aMlqFtmxA1YtHxQ9 HUBWUvpVbfqs5B5tgT/Y+FMXVuVsEAsW9nl83P1DCt5km4Z52s+ziJv1GdxvuP+x wvxNW2McNEgoNu8s/JIpGw4e1EUlsZyjEKkTZwX389rHeP5uNetGpvniu2qG4N3j w9fPN8f1F7jXmLZP23EgH4VKpNv+ldLfWEbHfbXdmxMKauyt1y2vtitzhoed9IIK X/4Qh9AfLs6yBG9BzNm/PT/nWTTF1rlLMNlPmPMjiBeJrjcYyoenDeXDb1/MJq6o toQWaQ== Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e8ht1g1te-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:24 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-2f3eb8f3419so2299634eec.1 for ; Mon, 18 May 2026 22:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169643; x=1779774443; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VZ0NwMyzJUB2GQ7WiRH1btiCyEC/1XQsRKRIRIi2gqw=; b=X+JyzM90tdl6aycUxN9DcJOTMMixaDroNA8h/Feg6A55Y2oWp8xY0zZaH9DNCaZmDr tVLC9Tgnuk44ZtVjhpP/LFsWmrYO6Rvu4JnIOaDJeguxdgETmBVW1/C+lXyp+c38/oUB H60aL/3cE7EC+W3He0lrG+mQrdBFco/k3XQqXD6ZYOZBy37t5z+K1ukw+EXfomWd9+8j EbVS7NuLEOUX5lc17d/D7FHGlacGEP9ZO4r8717YZ39hDn8wlCTkm2TgW5w+suCQyoTL vGQ/qmfLBRFxUq0z4zrOoGJ2awEhYroQRJzObKJ5U6VU7VmqyWRkOff0g5l711Mwb1FZ dAAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169643; x=1779774443; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VZ0NwMyzJUB2GQ7WiRH1btiCyEC/1XQsRKRIRIi2gqw=; b=eyXVfZX9E9NFdkScGVN6cFaHLQf+Ovxkvp1HzvsEQ7U4q9z9o7rqE8wCGawO3d7CO0 tDLw/dx89tnIhbIk9hnqJsFTuQT3qCwgu1nuK88dkwuBzfBhwSpH0Yhl4EUkR1BkP7CP JFONcNawZEhLjjNgQy/A+gQ+0tMHzWbctD3CK4B3aV7EuYKANw3nU0ihfJ6bjTERMeiQ oZ3aq5eEWAqPzBAfGKqQH77MTYsWa1AAKsotxHSrdO62NklIG8qpAnPTgdnFmq6tHB3l M9jzYaDcgblv15aYnRd0YFSiMGP66HYr+Vry1pVuNlaEec0aQ4iqU80SWeje/uIWLolO cUSw== X-Forwarded-Encrypted: i=1; AFNElJ+RmnS/VJAtPhnDIULBv10IkJIMoQTkvA9Y/VeWmOdvINjc47K9qYM5mNU50cZeCKZK6kfVOkPOCaPAuos=@vger.kernel.org X-Gm-Message-State: AOJu0Yz66aEUFT8GOMVn2P6LQqrv7/cjKc0p1EXa3b7IjFhBk81LjuK4 EOCtTVPWnupu7CIMhl48Zsnt2vtGONd5HkZilIC2WWjqZ0IcY8b0GLCwoM2ay48Dm0w4+YPosKj I4PR4UijcBTdmEdFQB1TWgzqGGcWiFkH/DsIufiauAr8sc5yaDakX+h44lu0uIcwaHkQ= X-Gm-Gg: Acq92OGxGUeTDCuD3sppfLfeLd3pyKZrAtq/1aUTwYml+yUBRFCv/a4Fd8JV7I+ut7u snOg40rfyIAn4BJkZUkz6p2t8xOjMIMJhmj7MbjvTDnuV20t7q9wD7QGvmlJ1C5/09vgXPJyDfv L5QgXy9Gsl2B0t1p7kwY0w54W5qS06UuPXxUQ7MsaZmcC9rbGKtqeuG4VJbjc3VZbZOm2tqW2WK fNcvUBmlXs0kMhXzeuR+FCE06Y0P+YB/3KRfGXc/0ymCjT0v1SlLe5eK+u9DhGPsspXTWbPkPtp Yaoy3xY+NiRFajRQF8hWgcdb8U/RRe/7mfDGk8Idntd/BA0s/7IavZTlwxFDU1IxsxlhNNedndp G52cgNJuQGe0ZhNLnqkbnvwdQdmYyPtwZJhFjFZmTgtffB46FPmGYij7JgEvpV7pX0v9l X-Received: by 2002:a05:7300:6429:b0:2df:7fe3:96a with SMTP id 5a478bee46e88-30397c321d6mr9406032eec.0.1779169643329; Mon, 18 May 2026 22:47:23 -0700 (PDT) X-Received: by 2002:a05:7300:6429:b0:2df:7fe3:96a with SMTP id 5a478bee46e88-30397c321d6mr9406011eec.0.1779169642830; Mon, 18 May 2026 22:47:22 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:22 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:13 -0700 Subject: [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-2-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=1262; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=LGL4VHxqKITnhSL7axVc8uFn3R+u5JVC+56a547NSCM=; b=WKP9YnTK4vYGaVO0+9dyaRHPMS4ebEb4bYteVtJj/gWytZ4fE/tYJGj+u8VCDw0E3kMnA+dHj hhX8CbwrCUKC+GdufP8pYpGn6xxe6xjagIVekpe8polHzLcl9JUMe7c X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=JKULdcKb c=1 sm=1 tr=0 ts=6a0bf96c cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=B0oFbsU2YAVyZoOp_L8A:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: 7Rg_GCpWfpf3QzysPk-4MeDtnOlt-u6G X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX5IH4BkrqICNx mNxglcXJexgMfYI6MSD9esurWtGgy0Di/cIOo7D6/m6phMsiRMDWWbFbxYiUyr0mjk6/7oDS6j+ 8Hge6dg16ju+G2dMumwVsreUUE8sWcKYj8EFScH/hMPytnPOw+eaqUgHuzd2fzHQXA//89HSx5W a6uyaRUixjdF3AgrW4s/M+9qELrzmdXDKzxT9ghxN117Z8UwdzjG1IBM4V89JRrRJ20Xeqo0xs0 yzmpdvNagdI0kxi+7FiyK5KBhdF2ZsHIKRVuRa9z2thf9cxhEKAR43f32IdKwFpqK4QdIjbblqL 92PuJbcToS2qoJYMqhZVJtZRt/yN5J/bklBAO9kbsRtkmeUMFQn7wxe6LI9FhGHWWQoPs8bh13e lGULh+ru2G91q/BvVEOwHqKeRwBU2cU3I2R7+VFYVKn+N3r1+MU/4aWtQtRA4V5PqdRZBVETByY buzkZ9VomxvabVKxz4g== X-Proofpoint-ORIG-GUID: 7Rg_GCpWfpf3QzysPk-4MeDtnOlt-u6G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Add two sets of constants to phy-qcom-qmp.h to support upcoming multiple link mode QMP PHY: - QMP_PHY_SELECTOR_0 / QMP_PHY_SELECTOR_1: generic logical PHY index values for QMP providers that expose multiple PHY instances under a single DT node (i.e. #phy-cells =3D <1>). - QMP_PCIE_GLYMUR_MODE_X8 / QMP_PCIE_GLYMUR_MODE_X4X4: link-mode values for the Glymur Gen5x8 PCIe PHY "qcom,link-mode" syscon property, selecting between the x8 single-PHY and x4+x4 dual-PHY topologies. Signed-off-by: Qiang Yu --- include/dt-bindings/phy/phy-qcom-qmp.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/p= hy/phy-qcom-qmp.h index 6b43ea9e0051..befa76f8392f 100644 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -21,4 +21,12 @@ #define QMP_PCIE_PIPE_CLK 0 #define QMP_PCIE_PHY_AUX_CLK 1 =20 +/* Generic QMP logical PHY selectors */ +#define QMP_PHY_SELECTOR_0 0 +#define QMP_PHY_SELECTOR_1 1 + +/* Glymur QMP PCIe link modes (for link-mode property value) */ +#define QMP_PCIE_GLYMUR_MODE_X8 0 +#define QMP_PCIE_GLYMUR_MODE_X4X4 1 + #endif /* _DT_BINDINGS_PHY_QMP */ --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07A8D34FF78 for ; Tue, 19 May 2026 05:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169647; cv=none; b=DTkVf2zVLn5WfMDiPNiy5ByI8FZcqZciwvZkgJTX+9BvzP4ssW7PnBpWBmEyMF4pUfuYz4n91C+rS7NQ7TMx2p+kVQhrD4dr9mCC+sSq0eaM5yb9QKgiwCYdEcMbhKwFnr58KjP08eL5LFfXq1IXoqmlKTgpvO6/OFFo+S0FyRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169647; c=relaxed/simple; bh=0SfbZYNjk789aGYvSOXe+aw7DeVeyc7Kx10vw0KqrQw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R0qsBc2/t/Qbtt8XoppI9Pvk7MiPBbhSjq8+hGNwfaUA/tJPXxPJgkRhz67z6TPhNYV3OdLtRgXLmWedmvg5vdaZfdt47aY7eiY3s/LPzftO+EFDa++p9hoTRpmdYaI6s5W6Kfc7621IbfhzQOQ0xUqnrN2FqZTZ4EXIw/lXSik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TFmMaIpg; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Ojx2aUsf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TFmMaIpg"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Ojx2aUsf" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J1BTgY2975785 for ; Tue, 19 May 2026 05:47:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VtTEoJrQ863EpCklHl4K1iMrE0nExfGouoieBxC+FJQ=; b=TFmMaIpgIHCHlj76 I0rUJqlAyXopxTRYDAEq5fKY0sFK6UewYqji5/nPpx299GNXsqYq+E0oKtXUMa/6 Vx/NOv4nBb7p1RH/BT0JVke0kaywynB4o1kr30DqV5Vew0MzE9Ux5j0oCbARzY1A 07uHuvfIq2GonIkALsyhpU/5dJqsltqRI0l9dNpXo2T9vXylBw0cfOyd39kvlruK ef3kAzailOmypjGuroSYTlyVSSmL2e7FnPmEE0JLsAcSq4C5bjo2Xxv3MElnKGbl UbfcVx4yxAncwEglHUUs4+OFuKr9O9III6e4gMxImlJqDnTlVzl04Y+TqCaLZEi5 5gXYBA== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e84v4asjy-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:25 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2fe1cf409a1so6106934eec.1 for ; Mon, 18 May 2026 22:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169644; x=1779774444; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VtTEoJrQ863EpCklHl4K1iMrE0nExfGouoieBxC+FJQ=; b=Ojx2aUsfMaEQFjGlCjV9Iedk1Z5WRaXB7iIgpaOHcLFR3jiHUq6COS2bfLhTcUIvcL vG3UfGuEjPEpimJROyKm+yopTB7aFa6E49NeUwPwJhMjfSTydVk6VyOteYRH6W9x41uU jWC5iCaRoUK2MJ82oY8jNZBoFDhEJuJL3SLdejuNNJ3d78JK58vmJ0b2VqqN/ugPTcYv cbNBDTx8wZ4KyDBevSUhV73tlVf3nh2GStJldcO3wF7OJK6zqunIYP/CKpdx+uNPC1yz QohV8bQXCmVUC6cDnjUS1lRfdqWkqTL/up7kRVFAJ0dLH/v1dAu/fdZ0D90gZoYJ7ckN GM4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169644; x=1779774444; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VtTEoJrQ863EpCklHl4K1iMrE0nExfGouoieBxC+FJQ=; b=Rp05FHeoR+Z1vQmVPAg/EoPuHPlQHUZ4aMr+vOJqoKzHiC8sxeGl44IVRxnP+URuHX xlW/Y+bbjXVWaQRAExmxuL7cWuHXNhUe+fSOIw9ks7qvCGu4eqowo6j9nlZGEgyUi7wT RoHmlek6N57MDt7SEINqcNK4qwlmODBOmpt3IhQ/Qlu+oZRPlGfpDt22I8YN6ggLCZun aTtCgOxbqMNv8d4rlW7qgy5wMZ/AWpJy+OlQdvlbFufF81RY56s5E1p33zmlrHqX2YOn vnlg7RTwqD82y2tuZuPGK0r15hxzLkUiMJnFyotiB1FUShBq2ekL048kH9yPjP/q+3nd FA4Q== X-Forwarded-Encrypted: i=1; AFNElJ9izDyOpHoVtrALBdFxVZTgkPDakUG+bDnoc3Eav/rOXWN6LNBulO4uV+DTUn2yhgKle/R2U4f5wODxCaA=@vger.kernel.org X-Gm-Message-State: AOJu0YwZLpnVNUUwPjLzZkapT8GH+yPkSuVeRbUAogXTv9xdMo18h194 JPkSWBZ4O8akgINn8JxpGGW4rzZMur3e7ykH+z135YySBqsEQJYYZVIYD0VjhcXlpmg9MS3JnS+ Td2DNTcAP9hrsO/viRa0pNSUNrd+qWC35/wba96IGWmLnaElYqI95AKvhd3xsk/JQbLk= X-Gm-Gg: Acq92OHczkktr4722panmLC0b/GOwAhE1RMtrxP8eNxnRBRLQvOu1ur8ENo08INu56M dL14XXRGm2DC/SeVmntCqGO12IKCu6nRRVNSLGI/+/UJVPnMOXITmN5se6zIFZjzce99MEwvmKW y4Gf53gx1r5fKnkAfhOtfJ9qBj2mxR4kmFjJK1c37EVpoqvOv+VIYImTIsQ3piN9YVCL8G8waiS Rms2z8px3zuMLDnxzpmZBHEwCj2u0KDFrofn2eIcuRGUuFdCdyvbnD5+caYfIbUiXosUszl7HV8 xbbczRKtCKQO8GGKd3v+bTEahy9D9d5RS4QS08xEsTulGWlXGihUbSvCsZZfkc25Z+dok2w1RqX ueFGf7Bpdzr7RMfUR5bz//zDb45nMesiUpoWq8bnv6c9xZCsthjyiOQJOGODSEg5ihrTKneFmKJ fp41s= X-Received: by 2002:a05:693c:2b0e:b0:2dd:2ad3:f799 with SMTP id 5a478bee46e88-303982ac821mr6840950eec.9.1779169644390; Mon, 18 May 2026 22:47:24 -0700 (PDT) X-Received: by 2002:a05:693c:2b0e:b0:2dd:2ad3:f799 with SMTP id 5a478bee46e88-303982ac821mr6840937eec.9.1779169643852; Mon, 18 May 2026 22:47:23 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:23 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:14 -0700 Subject: [PATCH RFC v4 3/9] phy: qcom: qmp-pcie: Add multiple power-domains support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-3-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=2515; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=0SfbZYNjk789aGYvSOXe+aw7DeVeyc7Kx10vw0KqrQw=; b=BO2RmfNFHbFIq1KEG1dO+4zWeOtGTTNbu/g4DipyMdJHGlwMB3onbNYR2YE0WyW5uigCUblZp mF6GK6wBoVLDmAnjOHt5c1QsCtCGbDlQ6NZBx1r0rE0ZjBjpKqDDYUp X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=VJPtWdPX c=1 sm=1 tr=0 ts=6a0bf96d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=eu5IZVYEi8O4nexjJlAA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: 5YELl543fQ5mrCnBtFeoTYq3GxnkM4du X-Proofpoint-GUID: 5YELl543fQ5mrCnBtFeoTYq3GxnkM4du X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXyL2zy/Z64g5s HHUn7OqBNQcYNgGwCbzPTF8CIdxpeGXLE6nqJMriKRIZkLzTsXYheGr4RqLUDh+7kD2d1MwAXdr 6TblM7YTosJYFyB8hYm8H+jRMmI5F8na5OKOuz6GHyx11x8TIet/jiL2QM9KJm+1EaQIvFwjx8+ pCtLEdmKafey4hhez+BbORbgziP/N4Gdc2gv268CxXBcT07Pa60KGmfzrTI6Bn2RlQntRfsmc/A 6obx4kVL+KXBl1histV4AMT/5VpUhVJZJELtcqQdq1j0OP3vfmje2VY/Wx7/IUcgCUdURzNVp/r FZ+ExJpOOMWkH1as+dNbaJRdstPPTrO9YdsJtLc1o1SqUyYV71emds8+eKFTvQOO64YtC5Jy23/ NNBQ7Gh5jqRXiV82fcbFEtoc5jX/211wDEaYTiSRdbFe+UBBfaq/kVGB/qdtNZeOl8CtacwBzrg fSSc+Zz5Pqo1delAq8A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in a bifurcated configuration. Each PHY has its own power domain (phy_gdsc) that must be powered on before initialization per hardware requirements. Current PHY power management assumes a single power domain per PHY, preventing proper setup for this dual-PHY scenario. Add support for multiple power domains by using devm_pm_domain_attach_list() to attach power domains manually, while maintaining compatibility with single power domain PHYs. Enable runtime PM to allow power domain control when the PCIe driver calls phy_power_on/phy_power_off: - Single power domain: QMP PHY platform device directly attaches to power domain and controls it during runtime resume/suspend - Multiple power domains: devm_pm_domain_attach_list() creates virtual devices as power domain suppliers, linked to the QMP PHY platform device as consumer This ensures power domains are properly attached and turned on/off for both single and multiple power domain configurations. Reviewed-by: Dmitry Baryshkov Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 75afbd15aaf4..832b5d93105b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -5329,6 +5330,7 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) =20 static int qmp_pcie_probe(struct platform_device *pdev) { + struct dev_pm_domain_list *pd_list; struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct device_node *np; @@ -5348,6 +5350,16 @@ static int qmp_pcie_probe(struct platform_device *pd= ev) WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); WARN_ON_ONCE(!qmp->cfg->phy_status); =20 + ret =3D devm_pm_domain_attach_list(dev, NULL, &pd_list); + if (ret < 0 && ret !=3D -EEXIST) { + dev_err(dev, "Failed to attach power domain\n"); + return ret; + } + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret =3D qmp_pcie_clk_init(qmp); if (ret) return ret; --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95077352C51 for ; Tue, 19 May 2026 05:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169649; cv=none; b=AC4eRBU2D3yk4AsHw8kR7E+zWKpikKDQFdkr5tRdq8aeopkjghb8hzH86GPD2QylUpPPib9PBzoK71VLA7G/hwOJnd8iyd5gjKL1ahWeoLa8p50owcKhhZ7csAGvzkMD8QkE1kvneoybTEfT/kXS9ej0kICUJCyd5rzXerj/tEM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169649; c=relaxed/simple; bh=rk+0s7fYFGz4ada/2dzRBhZiTmhHIS5lzExg1uX5PS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O7tc1gxGcD4GDPVeX7PoWGHr/y+8V3BkRp59eyxXinKvSv8Dm8gWqPxueh1joHbgKqq6+No5VO2NMIFdhHiEfk1J/7xRX7ZXKdg55AI3dhfiq2wwpUMh7cum+w0n3hQO0mdF/Sv63UXTPFsvxVoVRrRp41XIca/Jzcza4IVVgKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QvXClfaB; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Au5rSbHa; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QvXClfaB"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Au5rSbHa" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J39lqp2090992 for ; Tue, 19 May 2026 05:47:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bXD+NQxxyPWJVbCY8I4Rhkosv+1Pgs7F7zwEdLEgcoE=; b=QvXClfaBABmKWE3/ Lq7dGdJNMK6MGeXW0FJvxYLmagvNayTVcmHyp9gcazdKWlxh0je57mewKbVEB8Eg 7WDagzFUHoZcScCc58tdMxE1knO4f7up+yniuUL1okl95zB7XmOMmYEpHfzE18yS zE9Lw7SO8wnGzyZMSpl2qQnBPnl9+bnU3HXSNTQiXIWK7sbOskwxWHCoDVsYjiBH IraKxVrjIg79OMKCgK0QtKWESdKRBgLZ55xN9+woc2GCyWvK+otmUmHDaKTEVUVF geYC6d+gc95aM3TAsM8hDe/WDFYwUU9rw119PQRyCy+wMyULpL8pWOaH2Kif7+qI chJ5pA== Received: from mail-dl1-f70.google.com (mail-dl1-f70.google.com [74.125.82.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e80rpkwnq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:26 +0000 (GMT) Received: by mail-dl1-f70.google.com with SMTP id a92af1059eb24-135916eefa0so14544148c88.1 for ; Mon, 18 May 2026 22:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169645; x=1779774445; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bXD+NQxxyPWJVbCY8I4Rhkosv+1Pgs7F7zwEdLEgcoE=; b=Au5rSbHaME6c+ssDjp5wi2/alptWG4z/PPxAiaOBDnJ1sDfCOmFWBUH5Egfy2boxyP d5H9QUtrfFC359jvCZH3jq7kk6XfMWW9Po/yNiSzPAf+TKOKknJYMsmPtCl4Q/iySDn7 kS3vV7WF4hc+9gutGHNvIXc8EurgrPr9eiO0wCEMrMLOGR0ntiTW73ds1p0Di6eZdSkZ BlhmZBlWHjc2cRJkvsty7uN8Iq0cj4SLjwyAISGaUvQJrd5zkt5+C3lP5r8eLVu3+s6n TiwUvSC/hkItHbip0viE7t2s7Ne9LEBteBJy/Qn/knpOPQAT0dxuaJvc/6TqrB2NXaty Gpjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169645; x=1779774445; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=bXD+NQxxyPWJVbCY8I4Rhkosv+1Pgs7F7zwEdLEgcoE=; b=dwv8hLwll7RzwzJzDIXW0fchXxZWS/5cjkIB3zDx2AOezSoR0rYucHfRbFVZK2tUK/ KyTH+wBGBpdT/ke8NY6Y9lTV8L/6xlTQCiRF1JjFXNAR0gucEpGdU30uUW6Re5sBEeak CHdeU4TMJQujy1cBo9GujkgOk5vsf9Z2l5eFlSOSkscyvTYD+d4EbQJSsblOXTf9Mj7f zthUtQdm6L+5fseMmvuvTsgR3pPUSGVRETQs8HWNbiSLTRPobgTJOuQfP5sWSME+sIDa RtN38HNPuyloHdm2Hn6tC6jCGt3PDsDbg1A+H7S45B/aGqQCZRGuwJ2OEjy2Yr3v6I1w Gs5Q== X-Forwarded-Encrypted: i=1; AFNElJ/7M44EZD4pab7F1GUUMMkzgV12TjltCRtcOmmTSE67e0cgnDoMsoeWeTwzB5t9obfia49zPvz9aCk1fFU=@vger.kernel.org X-Gm-Message-State: AOJu0YyqSkv0/6spxa0FhrAHW541yYmGmRBtGPJSxOMMCNwNDd/+ER3n gNlqvUh8nf/gPFqDYbIWmn1ozSRvvV8CQ/B6pAxRPL7q+EEgEQQ40QWbFV+h4pIE7F4E1B4DX9a x/3YmbHmdX0vLqjfRlVIob37Hkwr2z80oXTdv4hldzUW23nJM4c5ureBph11ZVSnEbnQ= X-Gm-Gg: Acq92OHRwWGb+p2C0m4IUHh7kV/5w9dY7jSUXuJsqh3ILkBOxAEVoJJCMF+084i01Ad zed6ppLrDWIDsE569X0lVWsqSE8g/k8s+PiDefskmoELMsc3Dbz3OOXF4ah4gGq+srusiJULbLg ja4meM+JbtnWQrcpBlhi6+nxSd8Ve7MR7rrqMJ7Y3SYs3QB5e2i33SE7OAypGw63uJDnH+/+aVw 9Xp2BBsWngiO7ixXURKI7VMLNWRLsdmbkeXznqLpwhek0D+TKtNNePZHtkd4D4WwdMOldKiL6S4 RlORDOl1lt7dm43WVKWNNl96kMBoccZXMty1O3kpEMzBEAjpgWpJOavkccp6UYf8HMjwAktH6de bQX795rbIhfbxnd9YVuIcfwPlOQpoC18/TNj7h2EbLqJhfBOVl43M+K+fCJCvZp8Sq5x+ X-Received: by 2002:a05:7300:a907:b0:2e6:e868:4f38 with SMTP id 5a478bee46e88-3039818b054mr8291905eec.3.1779169645388; Mon, 18 May 2026 22:47:25 -0700 (PDT) X-Received: by 2002:a05:7300:a907:b0:2e6:e868:4f38 with SMTP id 5a478bee46e88-3039818b054mr8291880eec.3.1779169644881; Mon, 18 May 2026 22:47:24 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:24 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:15 -0700 Subject: [PATCH RFC v4 4/9] phy: qcom: qmp-pcie: Support multiple nocsr resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-4-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=10082; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=rk+0s7fYFGz4ada/2dzRBhZiTmhHIS5lzExg1uX5PS0=; b=26BdTMWY7fz/sE3b8rb3BJd8aqky6O1gF5pALIKz3QIKrqO3mtLnVY/QXn/nOKpHnVXKW3yHT OUgcf8fg436BhnZTemT60Jc7puONiAcVv0innmyAR7ZyS8tcCYSU+IX X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: IgzOZmzlJk57KZVHS5P2_N8MF7mr7ehK X-Proofpoint-ORIG-GUID: IgzOZmzlJk57KZVHS5P2_N8MF7mr7ehK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXxSvL5HWndWYK oCHTRM9jlrvfvRR+5axODPAqy6lURsjII0UQWb0ekAhX1J4OVv1aDjoDdQfyPRfcjArqa/GLsA7 2IqwJZfOA4R+SUWjGj4VlSzKRbR957dChjIBCppKjvfrrIdzGiZo5hjO+42xp8BvQ45uPH5/xRD NMCH+O1oDFSOdYpBh4SA36FCIGTFelSjB6vQLe63wCaEqjmBJSyAXpm7Om8eAY0+xlrGgROnt9Y L7rCCZIS6lKzGgD8CFzb3Rh7Ieof+I6XlmKRKcv2ngoZdumU1mV4tnZJqqM601+VyyEAD6rNFtz WS4CX7xkRo/DmNM2TS1HVgkYV954lhGiLlSX7V5cVBdcGv2bxRPbX65moA3tALS7Ra5p2iRSiiT UePEquoTXHUE7AIaTsSs5K/0dFPuDB+fq/Sa+6xgl14dZ4I0DmJTeOBglLPRIi6vDrRr7b6WFJS cLBAi7VGD/nVm54ZTYA== X-Authority-Analysis: v=2.4 cv=ecMNubEH c=1 sm=1 tr=0 ts=6a0bf96e cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=wBkCwaD4edhj46uzH8YA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Refactor nocsr reset handling to support multiple nocsr resets required for PHY configurations with bifurcated operation modes. The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in bifurcation, where each PHY requires its own nocsr reset to be controlled simultaneously. The current implementation only supports a single nocsr reset per PHY configuration. Add num_nocsr and nocsr_list fields to struct qmp_phy_cfg to represent the number and names of a group of nocsr reset names. Initialize these fields for all PHYs that have nocsr resets, allowing the driver to correctly acquire multiple nocsr resets during probe and control them as an array by using reset_control_bulk APIs. The refactoring maintains backward compatibility for existing single nocsr reset configurations while enabling support for multi-PHY scenarios like Glymur's 8-lane bifurcation mode. Additionally, introduces x1e80100_qmp_gen3x2_pciephy_cfg as a separate configuration from sm8550_qmp_gen3x2_pciephy_cfg since the x1e80100 Gen3x2 PHY requires nocsr reset support while the sm8550 Gen3x2 PHY does not. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 87 ++++++++++++++++++++++++++++= ---- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 832b5d93105b..1dee4733d4f2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3281,6 +3281,11 @@ struct qmp_phy_cfg { /* resets to be requested */ const char * const *reset_list; int num_resets; + + /* nocsr resets to be requested */ + const char * const *nocsr_reset_list; + int num_nocsr_resets; + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -3327,7 +3332,7 @@ struct qmp_pcie { int num_pipe_clks; =20 struct reset_control_bulk_data *resets; - struct reset_control *nocsr_reset; + struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; =20 struct phy *phy; @@ -3392,6 +3397,10 @@ static const char * const sdm845_pciephy_reset_l[] = =3D { "phy", }; =20 +static const char * const sm8550_pciephy_nocsr_reset_l[] =3D { + "phy_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp =3D { .serdes =3D 0, .pcs =3D 0x1800, @@ -4348,6 +4357,8 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4380,6 +4391,8 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4480,6 +4493,35 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_p= ciephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .serdes =3D sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v5_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -4502,6 +4544,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4535,6 +4579,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4566,6 +4612,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4581,6 +4629,8 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4609,6 +4659,8 @@ static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v8_regs_layout, @@ -4624,6 +4676,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4640,6 +4694,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4768,7 +4824,7 @@ static int qmp_pcie_init(struct phy *phy) } } =20 - ret =3D reset_control_assert(qmp->nocsr_reset); + ret =3D reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset= ); if (ret) { dev_err(qmp->dev, "no-csr reset assert failed\n"); goto err_assert_reset; @@ -4805,7 +4861,7 @@ static int qmp_pcie_exit(struct phy *phy) const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 if (qmp->nocsr_reset) - reset_control_assert(qmp->nocsr_reset); + reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset); else reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 @@ -4849,7 +4905,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) return ret; =20 - ret =3D reset_control_deassert(qmp->nocsr_reset); + ret =3D reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_res= et); if (ret) { dev_err(qmp->dev, "no-csr reset deassert failed\n"); goto err_disable_pipe_clk; @@ -4998,14 +5054,25 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) for (i =3D 0; i < cfg->num_resets; i++) qmp->resets[i].id =3D cfg->reset_list[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->= resets); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, + qmp->resets); if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 - qmp->nocsr_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy_= nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); + if (!cfg->num_nocsr_resets) + return 0; + qmp->nocsr_reset =3D devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_reset), GFP_KERNEL); + if (!qmp->nocsr_reset) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_reset[i].id =3D cfg->nocsr_reset_list[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_nocsr_resets, + qmp->nocsr_reset); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr reset\n"); =20 return 0; } @@ -5520,7 +5587,7 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { .data =3D &sm8750_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data =3D &sm8550_qmp_gen3x2_pciephy_cfg, + .data =3D &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data =3D &x1e80100_qmp_gen4x2_pciephy_cfg, --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF65A3537C0 for ; Tue, 19 May 2026 05:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169649; cv=none; b=QSvrkqVAtc2A0c1pGphwi3QGwbavP8qCtOJaJ4Xi3CvPWWV5co/byex2H4g3gqBq+VgUv8IaWEWsUkMGT09LhIjn4O6bitw/vG+5br8RjMcU9gfhhttEC/np/9dDaPdeRb4Gi+97XX5lKgUXzSBwtW7gnaeKcu+Cm6sOQt3C0+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169649; c=relaxed/simple; bh=MbaTZPbJ/JsKncMTk7duiSh2ZYiCvvSREcklhYtrLDc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VVLBflJoaZSqsLjGyCLdL1UBPQTQ0r4G4kq/HvfWBnhlvm00LdIIT/ZVXBNZqdw3Ioj3OlcdwcV0vMluruFbyhlmp6Vb+0XRLPxaF4IMvirYm+E4g9sxl+V8WVQysCJ82ibZAlbNw/h+QF1iDlMTxYtIrQAnbj2D4UbU2KJIHQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=gkRnk846; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=aPOtuErF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="gkRnk846"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="aPOtuErF" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J5Kx5T1252691 for ; Tue, 19 May 2026 05:47:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= P5B1VrBCZnVKjjIU3TaDRNw/BnDir7OFUrpirZ5gPu8=; b=gkRnk846rzCIkExj s0v+5HaktDA1pg0paPZD5FI5hLgM4E33gUQmnvskFjG/GxAsXJiRc/LxNjfR81LJ qN3l5poLWdI0p4/5DGg2m6UfG0CtBJa11MqW6OWED+bYOIqUbFcoQrz/qHeUChuL dwIVsdJ9RfAIGSWIxm3WswngL3h723JS8jqgIiqq09/yzedtb2XpiSliRT2OOJfC +yjcdhvg1l74W2aG1Yobxa1amTtKoRuL1gT45G4Ha35Urevo6YGuFPN5e2IRWBmr LgTWXlKGeIEVKeoelIcCJLv7kpOBsU3rSdhxaBwfNtC21Rt57g9AuKWuLOk7PDy/ knH/JA== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e82c0kj95-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:27 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2fded513994so14401852eec.1 for ; Mon, 18 May 2026 22:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169646; x=1779774446; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=P5B1VrBCZnVKjjIU3TaDRNw/BnDir7OFUrpirZ5gPu8=; b=aPOtuErFes1hPrc30DhQkXqx5/0zZWtdh1rOcBXNRGnt6sCejna+W2AFB4FnPzDAHB yBybWarkTGgRJZmtLmkVT5U83KEMjNCsNV01efVgn+18dJEugjCaouDZx1I3KxL9bdN3 mhKgRvTFKRKIXMyXK/0fOwv5N+sPqOPV7DNWAkNyKKn/GBJE4Echt7qqLoJi/6nuJ3Kx 1AtHoeLCqxdFCXp39x341M/icjlPbHbjp71LPr4sLlCzLDBRC1YkdEqBMbg76DZYzMAh Ld+PW0XfJr7GwATLsgtmp+UvNgrw8Mo1A5YwvX3p3TGtaArJ0LFnxoT0S90ruOav0fwE mqtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169646; x=1779774446; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=P5B1VrBCZnVKjjIU3TaDRNw/BnDir7OFUrpirZ5gPu8=; b=lfha2IpmGkaYqyoycHHAsPA7FRKgHvX/PvVHyV0nuAHcgtaRDuXIx9N3BsG7I50On1 QenpCp9d44v3Pox2oI0Do+2iV/rSSC9xz2AlMm579RB0bZUQw1yawPvJsdVxK8oCOskR B1Pjn4J1KvFc1gimOePygKOJyk2UL2C9Uy1VE+Kx6SlKnAjsb2wvX7xIHlnVlueQv2H0 ed2n1LIln1EWcFOMGJS7CanAufVhXwknCg2FTknSePsFqBltRXfE+teQ7P5HK2rxuaQ0 ADKEq43K7GzcisLRQiH9+ol5IU715paaDOoKAsRWa9DkBocld+DApr15DAaVX4AV38Ge Ue1A== X-Forwarded-Encrypted: i=1; AFNElJ/q74XZGUJXQ6UYr+4d5bFWxk04rBw5ETOcL7GChIviw7B5tAo13WfSdBdlJbZm4lO30VgDbjpXS7O+Hlw=@vger.kernel.org X-Gm-Message-State: AOJu0YyHRx/EPbf0+INgaoNbXnCZfL4yAGEEoNMZ40yghQSRKbCaKdFE xSIbjkukLdd5sSgyQXCz92BUlnWHX1wWnPnQ/P4mvGGchqRA7xU3L8L6klA/rwhoHPGOZw836p4 1BQigFCJPvvBvGGZyLvXi6epAc71lm2TNkk+dhsV0YurFwFnSxTugxF8CM2mZtjsCSMs= X-Gm-Gg: Acq92OEuV6XPZ9pHThX0b+4BbhSUZDJA90vWBL/L1+eAfP8A5Pk+siIM9YbUC3POlor kA7eRdgxnCqiFCdAsERXc6H366l1c43x1+s2L0ru7lWzBRgQaxVVebtZ5U43MjlBuxzjZRCVBRo 5xGTqHuQdc8w1mzk7WcgSeTSDA8RzEnaQ59ZHWenu9HKvbKpPcwoD9U8htSVn46PYioLYIcfKV/ jlXdKJmQnflHj8AZeUVukiLwnYN+2UrvVgCU++RDSJcBD1E7ntpZ0XAVdr9sK8kdGJQzYYrZtkD GDD+klufbYVi2qqey2j1MHAuLErYn52sCBZ5CYkWD2uFAYd5StV1AkDRDTQbHt/pEMBRZMBtLdp 5rE1x2i8a0WvJBcGSh1shRxkEdpM+3HaH3bd9p+ktRcfqUDlvzsY6LNVd9GtQjXtd0CgOUKQ4JT omAFU= X-Received: by 2002:a05:7300:fb83:b0:2ed:ff78:2c12 with SMTP id 5a478bee46e88-303986b7f00mr9394483eec.34.1779169646379; Mon, 18 May 2026 22:47:26 -0700 (PDT) X-Received: by 2002:a05:7300:fb83:b0:2ed:ff78:2c12 with SMTP id 5a478bee46e88-303986b7f00mr9394456eec.34.1779169645860; Mon, 18 May 2026 22:47:25 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:25 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:16 -0700 Subject: [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-5-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=5256; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=MbaTZPbJ/JsKncMTk7duiSh2ZYiCvvSREcklhYtrLDc=; b=Dq3RCcs82o0H2virjARvXvlTSyqDuHN+lBQRphnHRjl/IthNFWB96EylAfdOP6gHzuQPubGCY 3RMr5wszk+1Ce83B2703ATv5W3RlvPKpcAXgRqGxLvicpvvGZAfXDtQ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX+Sy8ZUZ4Vy9/ i0JrU219yBrpPdrNKC8gitYn6lgH6chNwW0cRyBjn+paTNbfZ2hbBQ+Np+XIqVmD5ptjJSqGBs2 CjD3eijCDL6sY1AC8DWl6jWRpGvu5C+5JtJhBW5ITCTYK8ECVDtvrNQ7m007124O5V46of2ZX3A tNF+oYsmUPtigENA75GdxlgJvdZM1HR1yz6q3stGg5E3SJQYodaCF7OayVkoMdzEg8Ljhlm6WdN 8SFrF3Pnk8bZ20A/msDRsF5kpkZXNve/E07ZVnysscvKKpqWfcsJv/ZMZ7VsDTGaSEryLWsg/6u CfrnfWBet5LtFHiGoE4kuyBD8Cymi6Q55pfmcpQdtDWJv2eINyzpVwDqJz7jmAYBEbYkmKtH5qh O2Uni/9wBLYZSk7WOGVfWP9EFiLAEV/I9D5eUeUDC8xCnebeLcH4nnKkHBbCTQSeEeIc0QDv9/R JAvepX8VDD1w+IOZMDA== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0bf96f cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=2AX8zLxBezjo-DDFgScA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: piqffNbghgTw1x-k8Fs-i_VgmeH9F83a X-Proofpoint-ORIG-GUID: piqffNbghgTw1x-k8Fs-i_VgmeH9F83a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Some QMP PCIe PHY hardware blocks can be split into multiple sub-PHYs under a single DT node, each requiring its own pipe clock registration and DT resource mapping. The current helpers are tightly coupled to a single qmp_pcie instance, which prevents reuse across sub-PHY instances. Refactor __phy_pipe_clk_register() as a generic helper and reduce phy_pipe_clk_register() to a thin wrapper around it. Similarly, extract qmp_pcie_parse_dt_common() from qmp_pcie_parse_dt() to hold the register- mapping and pipe-clock setup that will be shared between sub-PHY instances, with pipe clock names parameterised per instance. This is a preparatory step before adding multi-PHY support. No functional change for existing platforms. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 76 ++++++++++++++++++----------= ---- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 1dee4733d4f2..6332f15f78ca 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -5116,32 +5116,34 @@ static void phy_clk_release_provider(void *res) * clk | +-------+ | +-----+ * +---------------+ */ -static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node = *np) +static int __phy_pipe_clk_register(struct device *dev, struct device_node = *np, + int clk_name_index, struct clk_fixed_rate *fixed) { - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; struct clk_init_data init =3D { }; int ret; =20 - ret =3D of_property_read_string_index(np, "clock-output-names", 0, &init.= name); + ret =3D of_property_read_string_index(np, "clock-output-names", clk_name_= index, + &init.name); if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + dev_err(dev, "%pOFn: No clock-output-names\n", np); return ret; } =20 init.ops =3D &clk_fixed_rate_ops; =20 - /* - * Controllers using QMP PHY-s use 125MHz pipe clock interface - * unless other frequency is specified in the PHY config. - */ - if (qmp->cfg->pipe_clock_rate) - fixed->fixed_rate =3D qmp->cfg->pipe_clock_rate; - else + /* Default to 125MHz if caller did not pre-populate a rate. */ + if (!fixed->fixed_rate) fixed->fixed_rate =3D 125000000; =20 fixed->hw.init =3D &init; =20 - return devm_clk_hw_register(qmp->dev, &fixed->hw); + return devm_clk_hw_register(dev, &fixed->hw); +} + +static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node = *np) +{ + qmp->pipe_clk_fixed.fixed_rate =3D qmp->cfg->pipe_clock_rate; + return __phy_pipe_clk_register(qmp->dev, np, 0, &qmp->pipe_clk_fixed); } =20 /* @@ -5336,26 +5338,18 @@ static int qmp_pcie_get_4ln_config(struct qmp_pcie = *qmp) return 0; } =20 -static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) +static int qmp_pcie_parse_dt_common(struct qmp_pcie *qmp, void __iomem *ba= se, + const char *pipe_clk_name, + const char *pipediv2_clk_name) { - struct platform_device *pdev =3D to_platform_device(qmp->dev); const struct qmp_phy_cfg *cfg =3D qmp->cfg; const struct qmp_pcie_offsets *offs =3D cfg->offsets; struct device *dev =3D qmp->dev; - void __iomem *base; int ret; =20 if (!offs) return -EINVAL; =20 - ret =3D qmp_pcie_get_4ln_config(qmp); - if (ret) - return ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - qmp->serdes =3D base + offs->serdes; qmp->pcs =3D base + offs->pcs; qmp->pcs_misc =3D base + offs->pcs_misc; @@ -5368,12 +5362,6 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->rx2 =3D base + offs->rx2; } =20 - if (qmp->cfg->lanes >=3D 4 && qmp->tcsr_4ln_config) { - qmp->port_b =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->port_b)) - return PTR_ERR(qmp->port_b); - } - qmp->txz =3D base + offs->txz; qmp->rxz =3D base + offs->rxz; =20 @@ -5381,17 +5369,41 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->ln_shrd =3D base + offs->ln_shrd; =20 qmp->num_pipe_clks =3D 2; - qmp->pipe_clks[0].id =3D "pipe"; - qmp->pipe_clks[1].id =3D "pipediv2"; + qmp->pipe_clks[0].id =3D pipe_clk_name; + qmp->pipe_clks[1].id =3D pipediv2_clk_name; =20 ret =3D devm_clk_bulk_get(dev, 1, qmp->pipe_clks); if (ret) return ret; =20 - ret =3D devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe= _clks + 1); + return devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, + qmp->pipe_clks + 1); +} + +static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) +{ + struct platform_device *pdev =3D to_platform_device(qmp->dev); + void __iomem *base; + int ret; + + ret =3D qmp_pcie_get_4ln_config(qmp); + if (ret) + return ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + ret =3D qmp_pcie_parse_dt_common(qmp, base, "pipe", "pipediv2"); if (ret) return ret; =20 + if (qmp->cfg->lanes >=3D 4 && qmp->tcsr_4ln_config) { + qmp->port_b =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->port_b)) + return PTR_ERR(qmp->port_b); + } + return 0; } =20 --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85C4E351C04 for ; Tue, 19 May 2026 05:47:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169650; cv=none; b=rrp25MAQUV28NdktuyMQ9TP1YbLdo5fFX/UGJ7+5MkMKQ30+ae2HIoKxzB2eFWZ/B6fAv0joWeoR8tgOPJvLSJ8i4WhvKbBImMCpXE0pTuKkoDswS/Gq+3tkQuc803y0XzsDz2EiE7ra+BU0KjkjFE5IfpW56Vmu/SDICwGrwPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169650; c=relaxed/simple; bh=6l47wGwpcdS+i8z+96tTAR26f2jAl5baUJvJx2wGmVk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aeylYTlZDBVPV/pIqFEU+P+ZNmcWRl4RLHODh/IKosDKnFGdSd6N4ubnm2dHmHCepd955DE1CfmFSEGvO5ICU/4GWfxPe71bZfc2EEgSwa373kQJfNoD0dVABMOaRwf6JRwVTjNY5IlTxynrW9CX6g51MJnguBcALatu5QFpX9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Rt//YA81; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=DxVOzOpM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Rt//YA81"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="DxVOzOpM" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J59ngA1251662 for ; Tue, 19 May 2026 05:47:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=Rt//YA81zM+mrLYi jU2KPCTCo3kLls912E+1OpCYhDqtb/zzUb77KReevcvVtq7JRi7xR2o3ZRTEZl0Z DkO+c3cFs0hPl/JNm+f61Y6OTYj1qxiRnTvhPN9RiI5AlaWaMuq6kMHno7FnXx5E jaT+V4jaYdiLdGWpambl9Hm1qbWk0VgsYee3RjEdfJj2Mu4fYzcdgNCJ9pfssbU7 CRiVhk33qWpNwW0RQ0QB6LWeniPuI5De+OLNTtnTSzslauBAbsPFaGqemYJnxRHA MqUln9ExXHVjvXHtnVv61N+1BiKgWg2BFarFWk5enb58IRi3T3Yv9o7MYaOe+S7D vf1trw== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e82c0kj97-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:27 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2c16233ee11so4319752eec.1 for ; Mon, 18 May 2026 22:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169647; x=1779774447; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=DxVOzOpMqUM+F7Q9L52rCSf+QUhYlTfVMjVUV4ZGgw/EUt8pWtLk9UULVBGHi1+SZF cV4k0A5W64YPN2wmeorhKpx5Oxggq9PmdNgIxTKGPftVMiihRQlXKCs1MwFWD5wnEyKb xwh099QUvCbHtVrdXEnPzmLyS/vgiePR7rVnhEdQUhGQQkdBWne0eZg5jZuo78bXyV7Z VuGlW8s+dmJrMvLduTdMG7EBdfFhiJzufpLpzbzecJdXp0E+46nVkzSAqhFIEo0N8PZI UEaMFiHWfZ3psEj5xJgen1XY5Yx8RSh9gqVzoOVv9vOczZGpIynetxb14y4+c9Exy4hH V4QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169647; x=1779774447; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=DvRd/GUOqw34VYHpgWgWdoNeiHq+TiO646QwmFknTzPtJO/l89M0mvPYQAeeTguymv tKeVE4ByGvAPH6Sa88YefU+q13YnOnq2V3LWBhSmmpkg+aeNCUoXzVz7tWFLKTU3hrT5 VddtkVrX6Hqnlt5GoMM00G8AnIMelbdy7v/zyZliF8J2TJZbPd/QRs990S3+ggCGQFWG VUxIVi9kg2dq0KW6MhaqHhx4YZdRKxuRLA3fbwYMqUk/qdD9PmlnmTQWoBCiOP/77Ztq sj15Mc658+DKlFvGHXVaB+YKfMqpRbwu7xYSViVT+NjvRwwxeHVDNatCN+D2WIAA+grf BynQ== X-Forwarded-Encrypted: i=1; AFNElJ+aFKPjYP1P5NFdMfPdn2peOjIvFuXIfz6nzkZvD74ncHrAisGub4/PMxY46jpMGbhal0WnzDwkKG+ab0U=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6rvK/EulrHavZpgDmxAVRJXhWuJXqKn8eN5j/1g0zNZmX9/36 isAEOW2VBxCdpT1zNJsYhymUa26wVc4OJny2bZy91qb8V++CJBsRtgaFBYIiy1jcGpRyb00GCsd qqWpX3B6k3vhsHeRxfvDWZKScjSVFow4QD3I1o9o8BgV+92a/pfCLydu3y6GcVBnKhb8= X-Gm-Gg: Acq92OFRxSedtDefm2B1Z59NcQMoeBQJLdasEBd9RqdEOIE5xXCGp8EdKxT6t68H5Ek T0iyaN4B/e0KVVuETI9n2R7Wb0uHWx+Rbjx625wECBYAxPc9WfIlSOdcCTfb+vajpgmx6HPhi3f 8OduD/5sT8llrAK36qHq8RuGsYF1vy+3d0mJVhynpZ+yGKz/+SLEGxz8KD4l86uD1HfH3X1arEj o9diM1L1lhpjbIFsSDCQZ1NIR1Ap2mIUfD+Qsl31ZzBtGE1G7X3UL0rlj/K05y1vMvlnT2obWoy P/mfyFhpkje7hATpdwK265rZ0DwEiZxWM1VxW/nXib76Pd/Y1Iizg3xy1i5zzuoM5z+1dOGq/Ki 3gQkgeP02nmQUkM5yO6xLbihnd8xga3nQbAHEE4SrENYY2HiXWVbphktn5krbSz4p7xI+ X-Received: by 2002:a05:7300:e7a2:b0:2ea:b85c:153d with SMTP id 5a478bee46e88-303986948camr7474789eec.27.1779169647145; Mon, 18 May 2026 22:47:27 -0700 (PDT) X-Received: by 2002:a05:7300:e7a2:b0:2ea:b85c:153d with SMTP id 5a478bee46e88-303986948camr7474764eec.27.1779169646587; Mon, 18 May 2026 22:47:26 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:26 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:17 -0700 Subject: [PATCH RFC v4 6/9] phy: qcom: qmp-pcie: Add clock and reset lists for secondary PHY selector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-6-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=4489; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=6l47wGwpcdS+i8z+96tTAR26f2jAl5baUJvJx2wGmVk=; b=tI+M9vo4rfmkJHBISreYDBHdrX+sGAXFh9++C+YnE/xQL8MIXjFsLioMqHH2TrO7750kRU3Nu H8j3v/bQPN/CNxaRDMTldfJKYU89Zz4ECL8idv4ADT7LCrZmQHTaRFf X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX+XSnYILJc3yT kysXvuwv2cK0jdeXquCyhP1b6g4fV8eoDNWZYQMqrCLNOdUhKCBfPoZbBQ69AHU0R8R1PsO4Lz3 W1pGWk44uLQu8w3fbpNno4T9OrsiqywWV6xStLZdbQkU0nOOC/nQfmdThISVJKl8iEsk/fiEZFu pphEQBzdZ9AuqkgpKdXcSvtfhSUl40DpklCKMhUgSXF5kZg1RHdmGHoNPGFW96hU1D3d/VKFSTQ fWtmKgpY6z6GjMJI+SSzuKE7Y6lGZJ+G6WU/gEVtPlNeXR1grBGmR56Vs8IuiDx2VvYMajAFORM 8C1XpcwoUQ+GqwYqGW8BqqrLL26PqCU9YDGFOOLq6vGB4YqX+yAqFUUf1ggOB18aNIzBOKYdTWs ZJLyAQDRpaH/XXwnIH10GxgzHGfCPtRIMApgfUw7mCXfHfVBwAzQofQuujznfkdYr91XTdkDv3i sYh1c3lPe5fAowth1pg== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0bf96f cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=ee-eAjM40MESQSg1XYEA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: F95QDSV4qq7b8lzotIt-gXZ_Jz4uLNEH X-Proofpoint-ORIG-GUID: F95QDSV4qq7b8lzotIt-gXZ_Jz4uLNEH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 PHY instances sharing a single DT node each need their own clocks and resets. The current driver uses a single hardcoded clock list with no way to select per-instance resources. Add the infrastructure needed before wiring up multi-PHY probe. qmp_pciephy_secondary_clk_l[] and qmp_pcie_get_clk_list(id) are added to select the appropriate clock list by PHY selector index. qmp_pcie_num_clks() replaces the hard-coded ARRAY_SIZE(qmp_pciephy_clk_l) in qmp_pcie_init(), qmp_pcie_exit(), and qmp_pcie_clk_init(). struct qmp_pcie::phy is replaced with an id field so each instance can identify its index within a multi-PHY provider. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++++++++++--= ---- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 6332f15f78ca..b100302be12a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3335,7 +3335,7 @@ struct qmp_pcie { struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; =20 - struct phy *phy; + u32 id; int mode; =20 struct clk_fixed_rate pipe_clk_fixed; @@ -3379,6 +3379,24 @@ static const char * const qmp_pciephy_clk_l[] =3D { "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", }; =20 +static const char * const qmp_pciephy_secondary_clk_l[] =3D { + "ref", "phy_b_aux", "cfg_ahb_b", "rchng_b", +}; + +static int qmp_pcie_get_clk_list(u32 id, const char * const **clk_list) +{ + switch (id) { + case QMP_PHY_SELECTOR_0: + *clk_list =3D qmp_pciephy_clk_l; + return ARRAY_SIZE(qmp_pciephy_clk_l); + case QMP_PHY_SELECTOR_1: + *clk_list =3D qmp_pciephy_secondary_clk_l; + return ARRAY_SIZE(qmp_pciephy_secondary_clk_l); + default: + return -EINVAL; + } +} + /* list of regulators */ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", @@ -4781,6 +4799,13 @@ static void qmp_pcie_init_registers(struct qmp_pcie = *qmp, const struct qmp_phy_c qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); } =20 +static int qmp_pcie_num_clks(const struct qmp_pcie *qmp) +{ + const char * const *clk_list; + + return qmp_pcie_get_clk_list(qmp->id, &clk_list); +} + static int qmp_pcie_init(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); @@ -4840,7 +4865,7 @@ static int qmp_pcie_init(struct phy *phy) } } =20 - ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + ret =3D clk_bulk_prepare_enable(qmp_pcie_num_clks(qmp), qmp->clks); if (ret) goto err_assert_reset; =20 @@ -4865,7 +4890,7 @@ static int qmp_pcie_exit(struct phy *phy) else reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 - clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + clk_bulk_disable_unprepare(qmp_pcie_num_clks(qmp), qmp->clks); =20 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -5079,16 +5104,21 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) =20 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) { + const char * const *clk_list; struct device *dev =3D qmp->dev; - int num =3D ARRAY_SIZE(qmp_pciephy_clk_l); + int num; int i; =20 + num =3D qmp_pcie_get_clk_list(qmp->id, &clk_list); + if (num < 0) + return num; + qmp->clks =3D devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); if (!qmp->clks) return -ENOMEM; =20 for (i =3D 0; i < num; i++) - qmp->clks[i].id =3D qmp_pciephy_clk_l[i]; + qmp->clks[i].id =3D clk_list[i]; =20 return devm_clk_bulk_get_optional(dev, num, qmp->clks); } @@ -5414,6 +5444,7 @@ static int qmp_pcie_probe(struct platform_device *pde= v) struct phy_provider *phy_provider; struct device_node *np; struct qmp_pcie *qmp; + struct phy *phy; int ret; =20 qmp =3D devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -5468,14 +5499,14 @@ static int qmp_pcie_probe(struct platform_device *p= dev) =20 qmp->mode =3D PHY_MODE_PCIE_RC; =20 - qmp->phy =3D devm_phy_create(dev, np, &qmp_pcie_phy_ops); - if (IS_ERR(qmp->phy)) { - ret =3D PTR_ERR(qmp->phy); + phy =3D devm_phy_create(dev, np, &qmp_pcie_phy_ops); + if (IS_ERR(phy)) { + ret =3D PTR_ERR(phy); dev_err(dev, "failed to create PHY: %d\n", ret); goto err_node_put; } =20 - phy_set_drvdata(qmp->phy, qmp); + phy_set_drvdata(phy, qmp); =20 of_node_put(np); =20 --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 165BA3563E9 for ; Tue, 19 May 2026 05:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169653; cv=none; b=QJyF2CphcHvIYQIoJf5qucHQBfd3B0z19oLCAo5ltOuy0ANNdKBGMK+AWCSng/Tzb6oqmCe2L7tVN3vTisChU7hPQl6F6CxP+6k/48LS8JDzITNnc3mHVBaMUfIbL2u0gu3NGbB+fNX4H69ZSBOJRgMgr7YXSIJHPrDmHUJ+6xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169653; c=relaxed/simple; bh=vvLE/XhynCZJFbiPcGP3BjnA7ZMMjJOYuddxQHOZH5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bf3X11297lpAUNLStiRzqcQC4xDxtXYiSSCAYvHrIVy4DFrFmD3Aj0OFvO9odiU46U6JfSCUl5cIIt3PiJnlicMIEjwslhCTnL2wLMbw4iojqHaHzsBiWKWWw1NDbaC1qd/iNCoGbJEBRatdxFX6lSaAnqEhrRDzZFtfWK+KA+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=d5/CphwL; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Nd40q6TS; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="d5/CphwL"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Nd40q6TS" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J1Rdh31146729 for ; Tue, 19 May 2026 05:47:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 45o0IW2ZWWFrwHOSmMY+tw+i50QrMnrRfwUfFW1n9HE=; b=d5/CphwL2QJdQUjg eTdNECiW1Pa1gWPGG0IeK/gM7UBZik3r4kLKzSKFW0wbkZRaQmfolW5QPe/jTy0G rAaZQKfkWZ19rhOYB6PL5+ve3ikxHE5UlSLLOdF25pu9NJy74Hd94oPm89r0is7T +MEFeiYqxkcGeUwdkERlDB9yUouillInAzBwAlMpjBK6Wr6srapxFfvYxRmhcZnJ r7109AIsmCv22mfG4/AcbeigQeeAJCntVc2FLjyXGPnPVH2I4zxlelAOzZKWCYAG cSCApMq/LTu1BpXU7r7Q1q/oWcru2/rOw+DAWKyyIeSiyFWD5YQuIp5rUxhobppL 3KVp7w== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e8e7egt08-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:29 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2efc342ef15so4359886eec.1 for ; Mon, 18 May 2026 22:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169649; x=1779774449; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=45o0IW2ZWWFrwHOSmMY+tw+i50QrMnrRfwUfFW1n9HE=; b=Nd40q6TSnrzddaA5NRNwTaFDMKhIaWAj9vbicoxFOFcdRsFbZMhk/Axo+AWJuxZOZj TJQd1+aOgnVWx0XaSE9pw5iYoEfF6WVx6ps7mPBs9AzBmCbfG+5mYqwfOTEX0/XPV30C lyIsoqxmX92ZHyZb2n/ieeIjFX17nqOnsEFJqRy9w+oQouepvVIjTpTRqTNsXHDTITvW tZKLZZikzW4ng7t1Aoe1IcBiUvjUzVhNZT75PPPrxfl4c0DPfV1vwgsIRqjMItgB1mIw UFbCQ8Svgkqa52Oikhd5eGDW4jk21kK4Sk8kuUj349lZocMOYh76KL4978IyFi8xJ4V+ uUlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169649; x=1779774449; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=45o0IW2ZWWFrwHOSmMY+tw+i50QrMnrRfwUfFW1n9HE=; b=FcH4uzIEElBD81bolr20LkWKnqbhlS0V3nE2MjIdTUUVlZFuQ+iAb89iK7pPah9eiK t+mVhdqsIznqMg1YqQUrDkohCiT93pY/UP8z9XigoIC3qeXusCPhmgTRDCGEavjh8VU6 uJRtpzFn9saH3SQl+3Zw8D2NtsTesM2Z0lG26lmxxF9w+Aozs95qq4XkSUf3a8QZQIxp aq4gbeRKnQ+mdpqtrk1AdWphqso07j3TGcZe8zb4TcSA+U5Mf0MQQB59VA9FZpV0JvhG HfKMnNgxdL5CoYekAbkA2/3iJgnYSTYXVQL/Ma9EnI2MSsSL5+8TvcEJb9kH12DPQJet qt9g== X-Forwarded-Encrypted: i=1; AFNElJ9xCoTdWKXnRdx5OhHnjaX9eZLe9OLIzp2PV4PYs2wkCmWHh4Z7kQUL8c0SM9cSeVc8/hOe2QcJDm3nRdg=@vger.kernel.org X-Gm-Message-State: AOJu0YycsDXbKqpgbBLVX8289/mEsRYid9tS/61X6FrsmEB5Rx4qCV0+ QdM4czhoIycbe9oODLTr3DzLJT6gn+D+dK/PJtDpIOuyJvbu54EHK/7a5k38XsfA7196gXyyCQv v6SoPx6nGjgD2nHhJ5Pr7y+UzjCPRanmIyUpJYaOSFu4DOHucdr1xIQcryZP42uAgmj9BNFKLIE iZ6/xy X-Gm-Gg: Acq92OHjRHehMSinaYGW/yD8PY2wSxs5BRx5ZLv+yPxcmr5SmTsbCVuPa0A/7SCutzL Xgsm/lUuN2efsn9lGMZOdFowFI2LVX2enAsVBNGaJ5pwixL6su8YSE1PkQSAvRZWDMeNRgLSLUT hFBkwlRs48UTFH61gf8+v7ya9EIUIx2FH2c22g4qNWZnFIP2G74Qd8YmDSPjXZYuKc2MOJakPlt F76UpDxHHhk+z1abGaJO9Vnpl19gIGwfV6cQTLDx/Gc+JPsD8u/9EqCO5BegWSr0lAZ08nVMk8x Fs04k20ZozXHCyjB8Q7Wpj1InzHetkAIZhkp5+MEpnrWRg7eodPrEyYO3J6sVQiJRbrg5jhL8eg HKQ8QVa+mJRFS65xk7X3l9jIR5a3TBubnd1vniNanw47aErQRz/95OtZfn9tj0QXov4nB X-Received: by 2002:a05:693c:20c4:10b0:303:f26f:df30 with SMTP id 5a478bee46e88-303f26ffa15mr1123783eec.23.1779169648366; Mon, 18 May 2026 22:47:28 -0700 (PDT) X-Received: by 2002:a05:693c:20c4:10b0:303:f26f:df30 with SMTP id 5a478bee46e88-303f26ffa15mr1123767eec.23.1779169647779; Mon, 18 May 2026 22:47:27 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:27 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:18 -0700 Subject: [PATCH RFC v4 7/9] phy: qcom: qmp-pcie: Add link-mode multi-PHY probe infrastructure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-7-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=13426; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=vvLE/XhynCZJFbiPcGP3BjnA7ZMMjJOYuddxQHOZH5Q=; b=/KJcR0PA7sjQCRfjoE4U1lYQ/PGkehpHN0m1t/Ui6fzkn5ylKL5VgzojWprlaWAfFw14EzrP3 /CkPizDX4A7ARt75s9oJUdgoQ7/8f3PAWX2jrGQ/nx09MqwU09SRPkZ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=Rt316imK c=1 sm=1 tr=0 ts=6a0bf971 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=qYxDVQDxpuus1MYIwLEA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: K5XHU3FJHoLJr7TFIFs94Z1Q4QumxOig X-Proofpoint-GUID: K5XHU3FJHoLJr7TFIFs94Z1Q4QumxOig X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXwszEDR+6gbSm UU3u51KxS+QkqyRHPnu6Ue2VWxeFK4scfc6h9M4a702Ae3kAP/KtKLWd69vn/xUbYlJF/sHBnat Ij/ZmgX2/xz+HB/US0dzWBWAK+P4Sc+CY/AL21kAvMnAoy46TqFFEMeZeVCYK/XM+b/99ZJN5ZK Wz1YARbo09ZpIELba5dVT2tgwpGpIcG04ICSmIniDq8yYY0F/0GF59li90UONEyoPojwiebhvUo M0rBQIl3mgnsDO8/DeyoUPuBzxYPbIoqFC+tPjGq4Aye+r50sOlE7ANnhhLHGOgM5kjA967pwiR jxUXa1p3adT+x6n/33mw6DqhwIFjGAwMTMCgxKaiDa0sf111Ctcy2X+6N0g5tdO8gpydKYdTVZ5 P09KVKhwOWVmuXerZS0VnYtUJ94XzGGL+TD+aqgHteC/HQNA/QFj2nUTp1+UUfhD2/2FCjmJjsU XJx9WH5IacuviJE5+GA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing probe path has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Introduce a link-mode probe path where match data carries a per-mode cfg table. At probe time the driver reads the DT-selected mode, looks up the corresponding cfg array, and instantiates only the sub-PHYs required by that mode. A #phy-cells =3D <1> provider is registered so consumers can address individual sub-PHYs by index. Three new data structures support this: qmp_pcie_data holds per-provider state including the phy array, active mode, and regmap for the mode register; qmp_pcie_link_mode_cfg maps a mode index to its per-PHY cfg array; qmp_pcie_match_data is the top-level match data for link-mode platforms. On the probe side, qmp_pcie_probe() is reworked to instantiate one qmp_pcie per active sub-PHY and register the appropriate clock and phy providers. Per-instance DT parsing and phy object creation are factored into helpers to keep the probe path clean. The active link mode is written to the TCSR register at power-on to handle re-initialisation after low-power transitions. Platforms without a "link-mode" property continue to use the existing single-cfg path and of_phy_simple_xlate unchanged. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 351 +++++++++++++++++++++++++++= ---- 1 file changed, 311 insertions(+), 40 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index b100302be12a..d78d57fb64d6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -3342,6 +3343,28 @@ struct qmp_pcie { struct clk_fixed_rate aux_clk_fixed; }; =20 +struct qmp_pcie_data { + struct phy **phys; + u32 active_link_mode; + int num_phys; + struct regmap *link_mode_map; + u32 link_mode_offset; + struct mutex link_mode_lock; + + int num_pipe_outputs; + struct clk_fixed_rate *pipe_out_clks; +}; + +struct qmp_pcie_link_mode_cfg { + const struct qmp_phy_cfg *cfgs[QMP_PHY_SELECTOR_1 + 1]; + u32 num_phys; +}; + +struct qmp_pcie_match_data { + const struct qmp_pcie_link_mode_cfg *mode_cfgs; + u32 num_modes; +}; + static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -4897,6 +4920,27 @@ static int qmp_pcie_exit(struct phy *phy) return 0; } =20 +static int qmp_pcie_config_link_mode(struct qmp_pcie *qmp) +{ + struct qmp_pcie_data *qmp_data =3D dev_get_drvdata(qmp->dev); + int ret; + + if (!qmp_data) + return 0; + + mutex_lock(&qmp_data->link_mode_lock); + + ret =3D regmap_write(qmp_data->link_mode_map, qmp_data->link_mode_offset, + qmp_data->active_link_mode); + if (ret) + goto out_unlock; + +out_unlock: + mutex_unlock(&qmp_data->link_mode_lock); + + return ret; +} + static int qmp_pcie_power_on(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); @@ -4907,6 +4951,10 @@ static int qmp_pcie_power_on(struct phy *phy) unsigned int mask, val; int ret; =20 + ret =3D qmp_pcie_config_link_mode(qmp); + if (ret) + return ret; + /* * Write CSR register for PHY that doesn't support no_csr reset or has not * been initialized. @@ -5229,6 +5277,20 @@ static struct clk_hw *qmp_pcie_clk_hw_get(struct of_= phandle_args *clkspec, void return ERR_PTR(-EINVAL); } =20 +static struct clk_hw *qmp_pcie_clk_hw_get_link_mode(struct of_phandle_args= *clkspec, void *data) +{ + struct qmp_pcie_data *qmp_data =3D data; + unsigned int idx =3D 0; + + if (clkspec->args_count) + idx =3D clkspec->args[0]; + + if (idx < (unsigned int)qmp_data->num_pipe_outputs) + return &qmp_data->pipe_out_clks[idx].hw; + + return ERR_PTR(-EINVAL); +} + static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_no= de *np) { int ret; @@ -5258,6 +5320,37 @@ static int qmp_pcie_register_clocks(struct qmp_pcie = *qmp, struct device_node *np return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } =20 +static int qmp_pcie_register_clocks_link_mode(struct device *dev, + struct device_node *np, + struct qmp_pcie_data *qmp_data) +{ + int num_pipe_outputs; + int i; + int ret; + + num_pipe_outputs =3D of_property_count_strings(np, "clock-output-names"); + if (num_pipe_outputs < 0) + num_pipe_outputs =3D 1; + + qmp_data->num_pipe_outputs =3D num_pipe_outputs; + qmp_data->pipe_out_clks =3D devm_kcalloc(dev, num_pipe_outputs, + sizeof(*qmp_data->pipe_out_clks), GFP_KERNEL); + if (!qmp_data->pipe_out_clks) + return -ENOMEM; + + for (i =3D 0; i < num_pipe_outputs; i++) { + ret =3D __phy_pipe_clk_register(dev, np, i, &qmp_data->pipe_out_clks[i]); + if (ret) + return ret; + } + + ret =3D of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get_link_mode, qmp_dat= a); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, phy_clk_release_provider, np); +} + static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_no= de *np) { struct platform_device *pdev =3D to_platform_device(qmp->dev); @@ -5437,36 +5530,102 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) return 0; } =20 -static int qmp_pcie_probe(struct platform_device *pdev) +static int qmp_pcie_read_link_mode(struct device *dev, struct regmap **mod= e_map, + u32 *mode_offset, + u32 *active_link_mode, + u32 *hw_link_mode) { - struct dev_pm_domain_list *pd_list; - struct device *dev =3D &pdev->dev; - struct phy_provider *phy_provider; - struct device_node *np; - struct qmp_pcie *qmp; - struct phy *phy; + struct regmap *map; + unsigned int args[2]; + unsigned int mode; int ret; =20 - qmp =3D devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); - if (!qmp) + map =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,link-mod= e", + ARRAY_SIZE(args), args); + if (IS_ERR(map)) + return PTR_ERR(map); + + ret =3D regmap_read(map, args[0], &mode); + if (ret) + return ret; + + *mode_map =3D map; + *mode_offset =3D args[0]; + *active_link_mode =3D args[1]; + *hw_link_mode =3D mode; + + return 0; +} + +static int qmp_pcie_validate_link_mode(struct device *dev, + const struct qmp_pcie_link_mode_cfg *mode_cfg, + u32 active_link_mode, u32 hw_link_mode) +{ + int i; + + if (active_link_mode =3D=3D hw_link_mode) + return 0; + + for (i =3D 0; i < mode_cfg->num_phys; i++) { + const struct qmp_phy_cfg *cfg =3D mode_cfg->cfgs[i]; + + if (!cfg || !cfg->tbls.serdes_num) { + dev_err(dev, + "missing phy settings for link-mode %u, logical-phy %d (hw=3D%u)\n", + active_link_mode, i, hw_link_mode); + return -EINVAL; + } + } + + return 0; +} + +static int qmp_pcie_parse_dt_non_primary(struct qmp_pcie *qmp) +{ + struct platform_device *pdev =3D to_platform_device(qmp->dev); + struct device *dev =3D qmp->dev; + char *pipe_clk_name; + char *pipediv2_clk_name; + void __iomem *base; + + base =3D devm_platform_ioremap_resource(pdev, qmp->id); + if (IS_ERR(base)) + return PTR_ERR(base); + + pipe_clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "pipe_%c", 'a' + qmp->i= d); + pipediv2_clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "pipediv2_%c", 'a' = + qmp->id); + if (!pipe_clk_name || !pipediv2_clk_name) return -ENOMEM; =20 - qmp->dev =3D dev; + return qmp_pcie_parse_dt_common(qmp, base, pipe_clk_name, pipediv2_clk_na= me); +} + +static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, struct device_node *np, + struct phy **out_phy) +{ + struct device *dev =3D qmp->dev; + struct device_node *phy_np; + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret; =20 - qmp->cfg =3D of_device_get_match_data(dev); - if (!qmp->cfg) + if (!cfg) return -EINVAL; =20 - WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); - WARN_ON_ONCE(!qmp->cfg->phy_status); + WARN_ON_ONCE(!cfg->pwrdn_ctrl); + WARN_ON_ONCE(!cfg->phy_status); =20 - ret =3D devm_pm_domain_attach_list(dev, NULL, &pd_list); - if (ret < 0 && ret !=3D -EEXIST) { - dev_err(dev, "Failed to attach power domain\n"); - return ret; - } + qmp->mode =3D PHY_MODE_PCIE_RC; =20 - ret =3D devm_pm_runtime_enable(dev); + if (qmp->id =3D=3D QMP_PHY_SELECTOR_0) { + phy_np =3D np; + if (np !=3D dev->of_node) + ret =3D qmp_pcie_parse_dt_legacy(qmp, np); + else + ret =3D qmp_pcie_parse_dt(qmp); + } else { + phy_np =3D dev->of_node; + ret =3D qmp_pcie_parse_dt_non_primary(qmp); + } if (ret) return ret; =20 @@ -5482,35 +5641,147 @@ static int qmp_pcie_probe(struct platform_device *= pdev) if (ret) return ret; =20 - /* Check for legacy binding with child node. */ - np =3D of_get_next_available_child(dev->of_node, NULL); - if (np) { - ret =3D qmp_pcie_parse_dt_legacy(qmp, np); - } else { - np =3D of_node_get(dev->of_node); - ret =3D qmp_pcie_parse_dt(qmp); + *out_phy =3D devm_phy_create(dev, phy_np, &qmp_pcie_phy_ops); + if (IS_ERR(*out_phy)) { + ret =3D PTR_ERR(*out_phy); + return ret; } - if (ret) - goto err_node_put; =20 - ret =3D qmp_pcie_register_clocks(qmp, np); + phy_set_drvdata(*out_phy, qmp); + + return 0; +} + +static struct phy *qmp_pcie_link_mode_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct qmp_pcie_data *qmp_data =3D dev_get_drvdata(dev); + unsigned int idx; + + if (!qmp_data) + return ERR_PTR(-EINVAL); + + if (args->args_count < 1) + return ERR_PTR(-EINVAL); + + idx =3D args->args[0]; + + if (idx < (unsigned int)qmp_data->num_phys) + return qmp_data->phys[idx] ?: ERR_PTR(-EINVAL); + + return ERR_PTR(-EINVAL); +} + +static int qmp_pcie_probe(struct platform_device *pdev) +{ + struct dev_pm_domain_list *pd_list; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D NULL; + struct phy_provider *phy_provider; + const struct qmp_phy_cfg *cfg =3D NULL; + const struct qmp_pcie_match_data *mode_data; + const struct qmp_pcie_link_mode_cfg *mode_cfg; + const void *match_data; + struct qmp_pcie_data *qmp_data =3D NULL; + struct regmap *link_mode_map =3D NULL; + struct qmp_pcie *qmp; + struct phy **phys; + u32 link_mode_offset =3D 0; + u32 hw_link_mode =3D 0; + u32 link_mode =3D 0; + bool use_link_mode =3D false; + int i; + int num_phys =3D 1; + int ret; + + ret =3D devm_pm_domain_attach_list(dev, NULL, &pd_list); + if (ret < 0 && ret !=3D -EEXIST) { + dev_err(dev, "Failed to attach power domain\n"); + return ret; + } + + ret =3D devm_pm_runtime_enable(dev); if (ret) - goto err_node_put; + return ret; =20 - qmp->mode =3D PHY_MODE_PCIE_RC; + match_data =3D of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + ret =3D qmp_pcie_read_link_mode(dev, &link_mode_map, &link_mode_offset, + &link_mode, &hw_link_mode); + if (ret =3D=3D -ENOENT) + cfg =3D match_data; + else if (ret) + return dev_err_probe(dev, ret, "failed to read qcom,link-mode\n"); + + if (!ret) { + use_link_mode =3D true; + mode_data =3D match_data; + if (link_mode >=3D mode_data->num_modes) { + dev_err(dev, "invalid qcom,link-mode: %u\n", link_mode); + return -EINVAL; + } =20 - phy =3D devm_phy_create(dev, np, &qmp_pcie_phy_ops); - if (IS_ERR(phy)) { - ret =3D PTR_ERR(phy); - dev_err(dev, "failed to create PHY: %d\n", ret); - goto err_node_put; + mode_cfg =3D &mode_data->mode_cfgs[link_mode]; + num_phys =3D mode_cfg->num_phys; + + ret =3D qmp_pcie_validate_link_mode(dev, mode_cfg, link_mode, hw_link_mo= de); + if (ret) + return ret; } =20 - phy_set_drvdata(phy, qmp); + qmp =3D devm_kcalloc(dev, num_phys, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; =20 - of_node_put(np); + phys =3D devm_kcalloc(dev, num_phys, sizeof(*phys), GFP_KERNEL); + if (!phys) + return -ENOMEM; + + if (use_link_mode) { + qmp_data =3D devm_kzalloc(dev, sizeof(*qmp_data), GFP_KERNEL); + if (!qmp_data) + return -ENOMEM; + qmp_data->phys =3D phys; + qmp_data->active_link_mode =3D link_mode; + qmp_data->link_mode_map =3D link_mode_map; + qmp_data->link_mode_offset =3D link_mode_offset; + qmp_data->num_phys =3D num_phys; + mutex_init(&qmp_data->link_mode_lock); + } + + np =3D of_get_next_available_child(dev->of_node, NULL); + if (!np) + np =3D of_node_get(dev->of_node); + + for (i =3D 0; i < num_phys; i++) { + const struct qmp_phy_cfg *phy_cfg =3D use_link_mode ? mode_cfg->cfgs[i] = : cfg; =20 - phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + qmp[i].dev =3D dev; + qmp[i].id =3D i; + qmp[i].cfg =3D phy_cfg; + ret =3D qmp_pcie_probe_phy(&qmp[i], np, &phys[i]); + if (ret) + goto err_node_put; + } + + if (use_link_mode) { + ret =3D qmp_pcie_register_clocks_link_mode(dev, np, qmp_data); + if (ret) + goto err_node_put; + + dev_set_drvdata(dev, qmp_data); + phy_provider =3D devm_of_phy_provider_register(dev, qmp_pcie_link_mode_x= late); + } else { + ret =3D qmp_pcie_register_clocks(qmp, np); + if (ret) + goto err_node_put; + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + } + + of_node_put(np); =20 return PTR_ERR_OR_ZERO(phy_provider); =20 --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80322358373 for ; Tue, 19 May 2026 05:47:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169652; cv=none; b=ld86g6OL2yYcrn8Kz79v8MTkDwJSN4oKrEGx6mylEXXnkhTIV3OI5arpfICFETqllnjnzUgsFkblWeOWuHk/KxHtGa5HTD6fivwpO4aPPTXkfQi1aQM/mgIFIdnniOeLS6bIcHnzge8jYEOHGFVPQ/6iz3cHNuju1Ax/BVdikgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169652; c=relaxed/simple; bh=e+ge6SFVDXSZrp9sZxMLj4iJXXQDEqpoi4+iUcg4R2M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UG1gWuoLr5SrV1RVHDsmJm940QbB43AVx0OumTU+yVSg+Kp1S8pkVDnHNO21EvGOL9JYl/6P741JOuXshqJuT/MJj9w5COEZLXtnAya2fIL/Hn/TmWAdc6aSo28+LGtNXvstTzKBJOb2AiA1hAVpVAgIZSC+jrxccZ5naPM+yPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=oqs38DJX; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=iGJ3L0Jf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="oqs38DJX"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="iGJ3L0Jf" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J0frTk2975577 for ; Tue, 19 May 2026 05:47:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C0GSTBL64LgRqeP391F8PGtCzro2cCQhAPnIDXVHDdk=; b=oqs38DJXyTSw93BZ EbEaCCLfC12gFHVmKLvkvbWmmOpe8suAJbK3mxC09bw4re1IJFyhZcDVCgQRX1J6 xsqATNXqVRkOIgRJSrm+fS7VL2RDpE+f3pqRyhPcI4hp9h7RJTlfwNMRf5hs63Yy 3pHJM4uwfMg0F3dE9UhmY3WbrKraeni2zdgnM4pTBBlLqMDjmnJnez1CBMrYKjXo TTmKnnBBsV+HHj57chjmlrPAiUd1fBhaj1uv2AEpOdZukdDeGirBnpIIFF6Gg7L7 0doke5M1hjTUJYqF2xvMDZw/REHOqDSBa5CVBIZ1ApLFuuC2wef5TXACNw/lyprX DHMHxg== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e84v4aske-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:29 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2ef37c3f773so3310820eec.1 for ; Mon, 18 May 2026 22:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169649; x=1779774449; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C0GSTBL64LgRqeP391F8PGtCzro2cCQhAPnIDXVHDdk=; b=iGJ3L0JfmSWUejuRhxftYAiCq0nToX1KQUzy/vaWgBdt+bJPNk+PT/43R6hNbqYqkq r9+FHngz1EYqqvxd8pQTrbTB/xwivKLiHvbbCuBfX/j/ujz7xASneE3CfhPiafLyHqkS e5wwkZUIIqdhESEQyjN//AWUfKFd+f2m752cb7lehurUDjG+rPcPo9gEfCuKH0jDuRGx HUK196JqDiEoB+wfD/IQs7+vC+hh0E6DKzDmVGA0KmxTC6ngDmtD6KxeWKKudqvFuov5 aeGqM9z/JAVa7g0Q1bD5FVqFm43IOOFW8AUWUO/VbbeyfsNnuqEG3g2X33rrOnRxpsXt iHnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169649; x=1779774449; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=C0GSTBL64LgRqeP391F8PGtCzro2cCQhAPnIDXVHDdk=; b=I8is7YUm9RYMynsGH0mQGuUCd8048T4LDmjFObicq1uRVdAI6k37MJ3aWjmnLtGwOL U8EKXi+RYNQkCzBmIxGrtaJwBThYlO0FhrXF8QtKLPAneaKF5tY9xoXWX0zA/cdY+I+O R3fQU4sf5hNrcJXE1MkroYpBZUPHYcDgotPuq1xdTu4jBeEWkvHdjAh0KKFzkVCekA7K j1cVJB7yE3ZspXeBFPrAkQ/O2S1U2sbS0areE5/vWxus4IaIdBhjI6AWD2gu0C87O6B2 w3Tj2lWGhUcQSpnxyVl/aKjg9+trK7GgxpLhYku8fwMk7CgiKFOJvDyi2g2lDUZ//ICy 8Tjg== X-Forwarded-Encrypted: i=1; AFNElJ/YjB2EM0MLlHm6CGro7mSkMKWli/HFy45vvQqRjg9JV3Cs6kKPT9MN6zFv9Yc74K1RjebIZ7QP8L3+bPg=@vger.kernel.org X-Gm-Message-State: AOJu0YwcgswvJooqXBG9tMOrMSJ4HLj8saEVorgroi+iMV7NIu+n7wtE V1xhtL0HyHO8TmwwXKlJtSKiIPFOV15sIwQTXL3g3tGJIOBMVijSbTaykXt+KzAqhFMEZ8/AUkf VOU4lv8C8xbi2U2CvIfPk1L3fslXCgOtxcquSFGdfZpCCW4v3lRN2Nr1MgJa9KioJ7Yk= X-Gm-Gg: Acq92OET/Ch3D1EiY8DFoIegRYtcjL4ya801xUGJQwir8rhMvec51yyAyuoL4dhDC6r 9XJI0KHnpJmXeCLHCcaM3lGvMLrsQ+Ex4tEJYGdXmX/70tZFyGsXVgBn8b6dF08sLp+bgtev/NP iEAOqLMoB/ndBhcyUg7aVCOQzu7SIZcbmA3yT03GaG8NMhDvFEzvzQDD0HrYMl2AYSmWheF93w+ /aqj2pZnNRKB+wLoR9sfhUVPqIPr+ruU7dZU7VHB/ijVS29s0q9cpLUkEHoerhsJtUdNeDdy6l/ E7wtSf/VbmGrMfnoY/cv0mkmOXNIHVbJDg6MRMPFRvRI9fx8N2+N7mezt+bxXjmHbkPqlh6rQju U1YP0iTUJe/gyI6uANnsk1k4yFkbTWS0gT9olz+QY57Wcp8heUmSjII9gwuTXhRGs6pqCSt98Nh xaMUs= X-Received: by 2002:a05:7301:198e:b0:2dd:144b:6c2 with SMTP id 5a478bee46e88-303986a03b9mr7271845eec.27.1779169649088; Mon, 18 May 2026 22:47:29 -0700 (PDT) X-Received: by 2002:a05:7301:198e:b0:2dd:144b:6c2 with SMTP id 5a478bee46e88-303986a03b9mr7271826eec.27.1779169648521; Mon, 18 May 2026 22:47:28 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:28 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:19 -0700 Subject: [PATCH RFC v4 8/9] phy: qcom: qmp-pcie: Add Glymur Gen5x8 PHY config and match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-8-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=4238; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=e+ge6SFVDXSZrp9sZxMLj4iJXXQDEqpoi4+iUcg4R2M=; b=mPxErfRhw0SH57/BJgIP8D86VgsLj1bdZiVnh04jQhF6OAk+fnKRRhEMolsLD2qde6UVaDqBo SkCs2S9qWw1CzU1HreTkO/PN8p+uPl5URL/DPRfsbUMGdNFK/BnPWqv X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=VJPtWdPX c=1 sm=1 tr=0 ts=6a0bf971 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=O3x3ihak103vsextEXgA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: msZYB9HAJnyksWWkr0mdIK8-q3Uj0UXv X-Proofpoint-GUID: msZYB9HAJnyksWWkr0mdIK8-q3Uj0UXv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXxCXE90LkJaSi EbY53eI1Z4VVmmeJpf4A57gXC9DO4NkE0+UILl7Q5MKmYRuivRdWQWOIq41gbW43LevqeC+Uf69 4U9y/palIWRhEmpjjj7dUcNaNvtxXlJLaJmQBx0KfMYnUm+oYdJvwyIfnzkHHncxIlI9xSR94Ot WW28tfjcbW8do5nXeA4U/KDKWHGlald0AiiZSshy5hnOSj92nfTmq+QOHGPnP8gC0cW+54glHpu xgPmlxOIt9joB5tshOMijObyyXkBVJmb3VLgAbAuDtaKwZly3ky/ASFEmYPDTC3E8ddRCcFY8OF DnmQNHJi9Dz1yNUnXaD5zMRZeli/rTz1785i7Pj2St/W04JETWNXwdIg29qMekOX/BXvTfXL1fU ki2UWsT5Ymp1uz9E6/npijPtoKj2G91hXJ33R+v3yWxfOe/bWbL6d+HHXujKuiGktpbZ4VW2ecf tkgy8wbBOWQq+KNdxdw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 On Glymur, PCIe3 uses a single Gen5x8 QMP PHY hardware block that can operate in two link topologies: x8 as one 8-lane PHY, or x4+x4 as two independent 4-lane PHYs. Both topologies are served by the same DT node since they share the same hardware block and TCSR mode register. Per-topology reset and clock lists are introduced alongside the PHY configs to reflect the different resource ownership in each mode. The per-mode PHY configurations and match data are then added to wire the two topologies into the link-mode infrastructure introduced in the previous patch. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 80 ++++++++++++++++++++++++++++= +++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index d78d57fb64d6..d4aeb3e00955 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3399,7 +3399,7 @@ static inline void qphy_clrbits(void __iomem *base, u= 32 offset, u32 val) =20 /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] =3D { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "phy_b_aux", }; =20 static const char * const qmp_pciephy_secondary_clk_l[] =3D { @@ -4746,6 +4746,81 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pc= iephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const char * const qmp_pciephy_secondary_reset_l[] =3D { + "phy_b", +}; + +static const char * const qmp_pciephy_secondary_nocsr_reset_l[] =3D { + "phy_b_nocsr", +}; + +static const char * const glymur_pciephy_reset_l[] =3D { + "phy", "phy_b" +}; + +static const char * const glymur_pciephy_nocsr_reset_l[] =3D { + "phy_nocsr", "phy_b_nocsr", +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x4_secondary_pciephy_cfg = =3D { + .lanes =3D 4, + + .offsets =3D &qmp_pcie_offsets_v8_50, + + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .reset_list =3D qmp_pciephy_secondary_reset_l, + .num_resets =3D ARRAY_SIZE(qmp_pciephy_secondary_reset_l), + .nocsr_reset_list =3D qmp_pciephy_secondary_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(qmp_pciephy_secondary_nocsr_reset_l), + + .regs =3D pciephy_v8_50_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS_4_20, +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg =3D { + .lanes =3D 8, + + .offsets =3D &qmp_pcie_offsets_v8_50, + + .reset_list =3D glymur_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(glymur_pciephy_reset_l), + .nocsr_reset_list =3D glymur_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + + .regs =3D pciephy_v8_50_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS_4_20, +}; + +static const struct qmp_pcie_link_mode_cfg glymur_qmp_gen5x8_mode_cfgs[] = =3D { + [QMP_PCIE_GLYMUR_MODE_X8] =3D { + /* x8 */ + .cfgs =3D { + [QMP_PHY_SELECTOR_0] =3D &glymur_qmp_gen5x8_pciephy_cfg, + }, + .num_phys =3D 1, + }, + [QMP_PCIE_GLYMUR_MODE_X4X4] =3D { + /* x4 + x4 */ + .cfgs =3D { + [QMP_PHY_SELECTOR_0] =3D &glymur_qmp_gen5x4_pciephy_cfg, + [QMP_PHY_SELECTOR_1] =3D &glymur_qmp_gen5x4_secondary_pciephy_cfg, + }, + .num_phys =3D 2, + }, +}; + +static const struct qmp_pcie_match_data glymur_qmp_gen5x8_match_data =3D { + .mode_cfgs =3D glymur_qmp_gen5x8_mode_cfgs, + .num_modes =3D ARRAY_SIZE(glymur_qmp_gen5x8_mode_cfgs), +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -5797,6 +5872,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy", + .data =3D &glymur_qmp_gen5x8_match_data, }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, --=20 2.34.1 From nobody Mon May 25 03:55:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FC9A3537CD for ; Tue, 19 May 2026 05:47:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169657; cv=none; b=nnspnqpAvESFBZagkQ/V3MflWY3YYS3NFTu2ES/ovHC8RMFU8OEzz9soiCxwtGKpUFedWRvebZ48SYut/xZUN/a5aqBOjBGpZvxefHkvSMR6/p/6z/QRn9U4ipOJej1pEBGBfKE0kg5KafaQvrppWkpI4kPcm0FPxpAKHdUbwQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169657; c=relaxed/simple; bh=bW+/hvA+Pca7K41++Idj5IJ3xMCsvbz/R0Wz9A6pciE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nG2V8NvuC2Y01HvYCu0GViN3Rz5zgTd7VmEykaHz1Vau2IYHosxWx6uiKK92FYF4Hdr38JhiiTbrAvq7BM/cvBh3AuqocKt80+BwM6IK97mhP8IDXVK+z9oKZ2ahnY8lGQRoT/ASG1yjfib/Zc1q8MByUIlW3lZGzf1zyWMoXfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cyeOhdOW; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MBsFB0Kf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cyeOhdOW"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MBsFB0Kf" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J59ngD1251662 for ; Tue, 19 May 2026 05:47:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c5z2BAfF7u/3eYBoDRRCGBrxkUNywNEGnlBXzSLGwNk=; b=cyeOhdOWp6otu7eQ 5E1rjcikwJvifydOLrPNvh8uyUcq51oquMvvAtCBAikQzcencPJciSO+kKpf9y4S xPSsyuHucAa+JwquIsnz575lIrJqeA/baUDMmAKa7qOXgJRGMh6O2FxTQ9qr0O6P 4dVzqzGBnXdUmw6ZWMQqwLQ6m6L3c+0Y2T+ilAzjVajO+EatCtywqrywWVYXO4wX MBQmL0i1lUA+q/JumqT0QAq/B7LLsh1/Np7OEmz1FDTSQXDQ3fGfPAuNisZk1h86 rwJDQTKldVcxMGCYLhYHQVWbf09R7TZ6NeiFwI1rCRB5lechvFuEWhNLO2AoGyl6 IQTy5A== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e82c0kj9r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:31 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2efc342ef15so4359901eec.1 for ; Mon, 18 May 2026 22:47:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169650; x=1779774450; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c5z2BAfF7u/3eYBoDRRCGBrxkUNywNEGnlBXzSLGwNk=; b=MBsFB0KftWUFd9hIYFa8hoFKKbC7natGwx2FP4U8vGwn/zv7cOYJrthHurekZfyNgF /Vql64llOBWYzOwg4eoADKNOTnxRQ9tsTTs5ihkT1X5w0X9enlOPVfB8H0IL4ttfWClq UumyZByDfDTEz//JrZRaJqPsVvQr15HNffk2T1izSCZWPOMEBco6cLDcV6rSBOPuMz3U cGj9YLMvoXJa414BNXne2SL3EGQg4NUjIvvA4GrMI0QUmYVLToxg58htVo0Y/ua0+qMv w7dG3cwn8qWDsJgZxilXF/wTohsQq8rdqVCiilsWc7aocgVfTz7YPMAlEy+NpnWmVfbT VZkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169650; x=1779774450; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=c5z2BAfF7u/3eYBoDRRCGBrxkUNywNEGnlBXzSLGwNk=; b=NWJ21VDIU3PvaSVfkRNF8RrqskcmWm4Zm4EPllDtV3nsHvyOtxt3TGcG0LWphjABkN EnuCK+jdVWSn2pxIhoqJqxQSONiFwYo3bTUlocKAkQquq2jHzo1Nxd9eAu9+9eF2haxg 8tznN/+kNHPCir0z583QitSopOAS1s8lq71Y832An/zN40EdDzu6rLktb/mrobFd096Y NtUSvwX4GOW0ZFg+U12O5dKs2qH3Q/jE5YAIWYSR8TFoXc883oco/6IuSUp9PgH79yqv Y/EiAbwWjVJ6z9Cnmb/yqlhgt5omXnZV4qIh0a0LwMoogzCHKVE8aiX5eqojPPQaBXKp 5RMQ== X-Forwarded-Encrypted: i=1; AFNElJ8Tt9ao98HGrObYEQAr0ZaJF/yGGymlQsQzfMtYc9dsxQJi8GpBrqvyaursL4gWIQfp6iiS0NGGvuycPL8=@vger.kernel.org X-Gm-Message-State: AOJu0Yy13HNKJgsdgXDxPyp3a9yBKuPjmbbyiiSQrt5CeLxpCARNoQkH i2oKtoxrulMmtdq6FUbP2/uURfa16rzsrqRO71Erp32x/J+nqeU2bkBOtdId+6gPpltNEpl6qxP mH1pFObPdwuHG+tej2d2N2npn7C/XwGM87fURSSfPju1CBtCbzSxl33+z5f2sXCNjU7A= X-Gm-Gg: Acq92OF9b6iTNQ4xyOn7hLA4AChTlUrtaRfVXJ4o7pgh2t3/B+uCRHdq8luMOB9pMfH fmU6OSKDMGmj8jWbbKIAp6Rq7bi+lXnSpMzvrr8Q3yUMHihsqnaQpvQ1/Evrc8Geq3mB6YQP8qJ UYmSjD00I0t6By+FmcdJWMv5ZVG8Feumn9n7bykd94v7pPxh4vn2CD+iB31SicTv6Cklcslg1mj I/9vL5g6OHX14W3eq5vT+iu9yycBrQ1/4VejUBWFKFQ5derAz42IK+hZ8HF5PY5t/yGq3c9Apwl Dzfo9W8jjILXatfhuDPD7hFxKkRdfwGMbrXXc5aGJTbRuxI5/S7F3TJYfmQUeW0zX5QM5oj75y2 HzN9Rct3txrwJAdYW48ratJFdP4aFAkA9/tMno2pbceMcCPQuEz9ULGl5Fd6ZV02/yxFM X-Received: by 2002:a05:7301:688:b0:2e6:ff79:e356 with SMTP id 5a478bee46e88-303982bf6a8mr7850206eec.11.1779169649992; Mon, 18 May 2026 22:47:29 -0700 (PDT) X-Received: by 2002:a05:7301:688:b0:2e6:ff79:e356 with SMTP id 5a478bee46e88-303982bf6a8mr7850186eec.11.1779169649356; Mon, 18 May 2026 22:47:29 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:28 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:20 -0700 Subject: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-link_mode_0519-v4-9-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=11412; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=bW+/hvA+Pca7K41++Idj5IJ3xMCsvbz/R0Wz9A6pciE=; b=Gc3x6Yj04vzFPxwg9xMR5HbWgn4tBQNvte92tobbGvtxvLZHz43eBWpWc6QyQJgjyzlfCyFOy 67J3rYRXSnWCxCuQlIN64vxIIN7JJXQnQUyRDx4kFj+bMvE3lhpQpv4 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX1XiPDmiZh5lN ABbyKRkkK8LrQenoxd17q/sKSJyQ8U+J4ciCq6zeMN8LUVDqqO8eze1oM4htqt1vsWeWN6hsR+l ectvT4LIAdEc8e/2V7+rDMtPvLE5E/n96RwPLXhYasqllSrttHLKLP9fjTjb+St07WBtsNqzFDf QGzDHhJWcnOx7HOBOtG9R/lYBKB84F2GitAr3lJXWOBLCIGdkjQnBcXPl28s+cuxeSYWuTwxvgM sbVTw6CYpPtbnT/MUmTOB5A9kDv0FuN9vLeKIhZDZhKq1X+SLfb10MmFxPgajzTbJDRrhnf2vRY Q4bhXECMPsjaXbvt3JDLx8Fr6HUhmSwtryz0gUPe5uPME37FPPh9Kf94C2SD7s15BP+a8OpT7J2 dmGRneAG3jX5DX0Q7Q816krvkAfBpJpeXPUoCV9B/RcNl0Ie6uv3T0xAI5s5gojSDMnA5614sIL nJlJAngzoMABc8yS40A== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0bf973 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=XVFuNizlLJlILrWKUTkA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: HuMsVroQGFElMGINPa2x-bIZRm5AuruY X-Proofpoint-ORIG-GUID: HuMsVroQGFElMGINPa2x-bIZRm5AuruY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and PCIe3b as consumers of that shared PHY provider instead of separate PHY nodes. Update the DTS wiring to: - point GCC PCIe3A/3B pipe parents to the shared PHY clock outputs - add PCIe3a controller node and route PCIe3a/PCIe3b port phys to &pcie3_phy using two-cell PHY arguments - configure the shared PHY node with link-mode and dual pipe outputs Use QMP_PCIE_GLYMUR_MODE_* dt-binding macros for mode selection. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 + arch/arm64/boot/dts/qcom/glymur.dtsi | 333 +++++++++++++++++++++++++++= +++- 2 files changed, 336 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts= /qcom/glymur-crd.dtsi index 6e2e06ae6c8a..72a86881d36c 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -451,6 +451,11 @@ &pcie3b { pinctrl-names =3D "default"; }; =20 +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; +}; + &pcie3b_port0 { reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 9ea297588d07..87530c233050 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -757,8 +757,8 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ - <0>, /* PCIe 3b */ + <&pcie3_phy 0>, /* PCIe 3a pipe */ + <&pcie3_phy 1>, /* PCIe 3b pipe */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -2285,6 +2285,59 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; =20 + pcie3_phy: phy@f00000 { + compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg =3D <0x0 0x00f00000 0x0 0x10000>, + <0x0 0x00f10000 0x0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "pipediv2_b"; + + resets =3D <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr", + "phy_b", + "phy_b_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>, <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + + qcom,link-mode =3D <&tcsr 0x5000 QMP_PCIE_GLYMUR_MODE_X4X4>; + + #clock-cells =3D <1>; + clock-output-names =3D "pcie3a_pipe_clk", + "pcie3b_pipe_clk"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + usb_hs_phy: phy@fa0000 { compatible =3D "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -3647,6 +3700,282 @@ pcie3b_port0: pcie@0 { reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 + phys =3D <&pcie3_phy 1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie3a: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; + + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <3>; + num-lanes =3D <8>; + + operating-points-v2 =3D <&pcie3a_opp_table>; + + msi-map =3D <0x0 &gic_its 0xb0000 0x10000>; + iommu-map =3D <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3a_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3_phy 0>; + #address-cells =3D <3>; #size-cells =3D <2>; ranges; --=20 2.34.1