From nobody Mon May 25 05:58:56 2026 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1FA737BE9A; Mon, 18 May 2026 02:58:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779073139; cv=none; b=ubyy2/NF5i9Czd5ZtkkP98wFWnzqAQA11Yu4HOlsZl2gj/tJCpvAiF54FdxA3DJmrCNjai7TxlRM5frrpRqoao5t0016Quya3J9Bnn0Je4dXSIkAp3MEJus0lgC3fmqJILIAz1CU54U0y6aE3wgL0ocLMi3nBMb1vqXle/karok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779073139; c=relaxed/simple; bh=9GQNv2wGSWkbfAUHwoF9Hs8KSZtunAO9+Pncvtb1r5A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q3yXLCa3LyX/kVaS4/wK5A4Xb9X9aV0YQ3GueJHEJJ3Ch7izuiToca1Q+AGmqs11zqSbrIyrZjtvfWn3jhrG2QQ77YjnW4TlKjyhVsf4y18JZuyOur7CQKRXXZLbeLli48DCq2F4HGv4TQSIocOXIz9HJ3A7RuV2GxYxzda7AnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6E0A4201203; Mon, 18 May 2026 04:58:55 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 36EA92011A8; Mon, 18 May 2026 04:58:55 +0200 (CEST) Received: from lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com (lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com [10.52.9.99]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id EA507180217B; Mon, 18 May 2026 10:58:52 +0800 (+08) From: Joseph Guo Date: Mon, 18 May 2026 11:58:19 +0900 Subject: [PATCH v4 1/2] dt-bindings: arm: fsl: Add i.MX95 19x19 FRDM PRO board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-imx95_frdm_pro-v4-1-975346555a9b@nxp.com> References: <20260518-imx95_frdm_pro-v4-0-975346555a9b@nxp.com> In-Reply-To: <20260518-imx95_frdm_pro-v4-0-975346555a9b@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, xinyu.chen@nxp.com, qijian.guo@oss.nxp.com, justin.jiang@nxp.com, Joseph Guo , Daniel Baluta , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779073130; l=1080; i=qijian.guo@nxp.com; s=20250519; h=from:subject:message-id; bh=9GQNv2wGSWkbfAUHwoF9Hs8KSZtunAO9+Pncvtb1r5A=; b=ifZjH5AbvLyD0FuomB604p0HFCt20GtUi1uva/Kxe5I4PlVKAhJNNJ+GWAXQ65kGdgRFqqcfQ xJIYQF2gPhwCS0lY5YZ0/q6Fva52LCG5j1u19tboczSGgruANefVql3 X-Developer-Key: i=qijian.guo@nxp.com; a=ed25519; pk=VRjOOFhVecTRwBzK4mt/k3JBnHoYfuXKCm9FM+hHQhs= X-Virus-Scanned: ClamAV using ClamSMTP Add the i.MX95 19x19 FRDM PRO board in the binding document. Reviewed-by: Daniel Baluta Acked-by: Conor Dooley Signed-off-by: Joseph Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index f5d3c08369b92987b2cb01e36c26f9f72937f557..9f50b4bf67bc2c0b0e11b1ae615= 151aa4d5f0d09 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1485,6 +1485,7 @@ properties: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - fsl,imx95-19x19-frdm-pro # i.MX95 19x19 FRDM PRO Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation= Kit (EVK) - const: fsl,imx95 =20 --=20 2.34.1 From nobody Mon May 25 05:58:56 2026 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ECAF37C103; Mon, 18 May 2026 02:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779073150; cv=none; b=OmawHsQKJ1FGIZ+EAy6qGbscZlSjp7WCYK7Acw2gI/70MW5kS7G/owtiqzvIfNahw6T3IOM/GrMueu14XNHYBCJpp3fsxGq816c0yHZAhSxtE5aUUn3b3vciMhT7ap+fl2y/g8eTvDass95RdASBDTCuqW0cxz0PHAqQUSSBSpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779073150; c=relaxed/simple; bh=x7biwEgDWiJrYROWh9FkqxsbpxvgvZTRP7Xpz+VwYT0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i7zvwEiUrfBZE2eXgho02kU07i4RPr/fRq4X9BXDQoGzAKghUjZ87pMirIg6HBybOLM8zPOsJ+kbRDrN6gEuUd/6BanW2hSrFer35xyf/BPIovVDenoX6SiBKWEXMbmDSgB10RATX+VGrfbfm7UdIeYDz5JpyP6PaFDrZDOzRhg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 529A01A1213; Mon, 18 May 2026 04:58:57 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E6E751A1136; Mon, 18 May 2026 04:58:56 +0200 (CEST) Received: from lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com (lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com [10.52.9.99]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C2332180009C; Mon, 18 May 2026 10:58:54 +0800 (+08) From: Joseph Guo Date: Mon, 18 May 2026 11:58:20 +0900 Subject: [PATCH v4 2/2] arm64: dts: freescale: add i.MX95 19x19 FRDM PRO board dts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-imx95_frdm_pro-v4-2-975346555a9b@nxp.com> References: <20260518-imx95_frdm_pro-v4-0-975346555a9b@nxp.com> In-Reply-To: <20260518-imx95_frdm_pro-v4-0-975346555a9b@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, xinyu.chen@nxp.com, qijian.guo@oss.nxp.com, justin.jiang@nxp.com, Joseph Guo X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779073130; l=29172; i=qijian.guo@nxp.com; s=20250519; h=from:subject:message-id; bh=x7biwEgDWiJrYROWh9FkqxsbpxvgvZTRP7Xpz+VwYT0=; b=8fvwb27aN1BtCltEAwL7O2f3lnEVGyej2vgLRT8vVza8/Swwd8u1N2lkN/OOyIl6fwlHFWr+E UZpdsE98GfNABq4lhT3Bgj4ecdwiS7a1k1oExkieVqhtEKo9qbYO0P2 X-Developer-Key: i=qijian.guo@nxp.com; a=ed25519; pk=VRjOOFhVecTRwBzK4mt/k3JBnHoYfuXKCm9FM+hHQhs= X-Virus-Scanned: ClamAV using ClamSMTP NXP i.MX95 19x19 FRDM PRO is cost-effective with extensive expansion capabilities based on the i.MX95 19x19 SoC. It is designed for AI and robotic situation. Difference with i.MX95 15x15 FRDM: - Use i.MX95 19x19 package - Support 2 KEY-M M.2 PCIE - 10G ETH interface - Secure Element interface Add device tree for this board. Including: - LPUART1 and LPUART5 - NETC - USB - 2 M-Key M.2 PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN1 and FlexCAN3 (CAN1 is reserved by M7) - LPI2C3, LPI2C4 and their child nodes - Watchdog3 - SAI, MQS, MICFIL Signed-off-by: Joseph Guo --- Changes in v2: - Run dt-format to reformat the node order - Change compatible of mqs to audio-graph-card2 - Add imx95-19x19-frdm-pro in Makefile Changes in v3: - Change status of CAN1 to reserved - Remove unused pinctrl - Explain difference with i.MX95 15x15 FRDM in message Changes in v4: - Correct underscores in node names - Correct 'silent-gpio' of can_phy to GPIO_ACTIVE_HIGH - Fix typo in pinctrl_pcal6416 - Change 'reg_ext_12v' to 'reg_exp_12v' --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-19x19-frdm-pro.dts | 1021 ++++++++++++++++= ++++ 2 files changed, 1022 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index a6fe56bb93aa12040d184aa576623951515a8469..af22a5aa3e96fa24ebf2766a98f= ea4d0948c50f4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -462,6 +462,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk-sof.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-frdm-pro.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-tqma9596sa-mb-smarc-2.dtb =20 diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts b/arch/= arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts new file mode 100644 index 0000000000000000000000000000000000000000..b87a26b0d7fcf5790a8cb616833= c6f27d633bca0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-frdm-pro.dts @@ -0,0 +1,1021 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include +#include +#include "imx95.dtsi" + +#define FALLING_EDGE 1 +#define RISING_EDGE 2 + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + model =3D "NXP FRDM-IMX95-PRO"; + compatible =3D "fsl,imx95-19x19-frdm-pro", "fsl,imx95"; + + aliases { + ethernet0 =3D &enetc_port0; + ethernet1 =3D &enetc_port1; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + gpio4 =3D &gpio5; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart1; + serial4 =3D &lpuart5; + }; + + bt_sco_codec: bt-sco-codec { + compatible =3D "linux,bt-sco"; + #sound-dai-cells =3D <1>; + }; + + flexcan1_phy: can-phy0 { + compatible =3D "nxp,tja1057"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + silent-gpios =3D <&i2c4_gpio_expander_22 11 GPIO_ACTIVE_HIGH>; + }; + + flexcan3_phy: can-phy2 { + compatible =3D "nxp,tja1057"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + silent-gpios =3D <&i2c4_gpio_expander_22 13 GPIO_ACTIVE_HIGH>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + stdout-path =3D &lpuart1; + }; + + reg_vref_1v8: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V1.8_SW"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V3.3_SW"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "DCDC_3V3"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <®_dcdc_5v>; + gpio =3D <&i2c4_gpio_expander_22 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_dcdc_5v: regulator-dcdc-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "DCDC_5V"; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&i2c4_gpio_expander_22 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_1v8: regulator-exp-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "EXP_1V8"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + gpio =3D <&i2c4_gpio_expander_22 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_3v3: regulator-exp-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "EXP_3V3"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <®_dcdc_3v3>; + gpio =3D <&i2c4_gpio_expander_22 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_5v: regulator-exp-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "EXP_5V"; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + vin-supply =3D <®_dcdc_5v>; + gpio =3D <&i2c4_gpio_expander_22 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_exp_12v: regulator-exp-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCCEXP_12V"; + regulator-always-on; + regulator-max-microvolt =3D <12000000>; + regulator-min-microvolt =3D <12000000>; + gpio =3D <&i2c4_gpio_expander_22 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_1_pwr: regulator-m2-mkey-1-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "M.2-power-mkey-1"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&i2c3_gpio_expander_20 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_2_pwr: regulator-m2-mkey-2-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "M.2-power-mkey-2"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&i2c3_gpio_expander_20 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "M.2-power-ekey"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&i2c4_gpio_expander_22 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_SD2_3V3"; + off-on-delay-us =3D <12000>; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "WLAN_EN"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <®_m2_ekey_pwr>; + gpio =3D <&i2c4_gpio_expander_22 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us =3D <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB_VBUS"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&i2c4_gpio_expander_22 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7F000000>; + reusable; + size =3D <0 0x3c000000>; + linux,cma-default; + }; + }; + + sound-bt-sco { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master =3D <&btcpu>; + simple-audio-card,format =3D "dsp_a"; + simple-audio-card,frame-master =3D <&btcpu>; + simple-audio-card,name =3D "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai =3D <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num =3D <2>; + dai-tdm-slot-width =3D <16>; + sound-dai =3D <&sai5>; + }; + }; + + sound-micfil { + compatible =3D "fsl,imx-audio-card"; + model =3D "micfil-audio"; + + pri-dai-link { + format =3D "i2s"; + link-name =3D "micfil hifi"; + + cpu { + sound-dai =3D <&micfil>; + }; + }; + }; + + sound-mqs { + compatible =3D "audio-graph-card2"; + links =3D <&sai1_port1>; + label =3D "mqs-audio"; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&i2c4_gpio_expander_22 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg =3D <0x0 0x80000000 0 0x80000000>; + device_type =3D "memory"; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&enetc_port0 { + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc0>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&enetc_port1 { + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&flexcan1 { + phys =3D <&flexcan1_phy>; + pinctrl-0 =3D <&pinctrl_flexcan1>; + pinctrl-names =3D "default"; + status =3D "reserved"; +}; + +&flexcan3 { + phys =3D <&flexcan3_phy>; + pinctrl-0 =3D <&pinctrl_flexcan3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpi2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-names =3D "default"; + status =3D "okay"; + + i2c3_gpio_expander_20: i2c3-gpio-expander@20 { + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&gpio5>; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells =3D <2>; + gpio-controller; + pinctrl-0 =3D <&pinctrl_pcal6416>; + pinctrl-names =3D "default"; + }; + + ptn5110: tcpc@50 { + compatible =3D "nxp,ptn5110", "tcpci"; + reg =3D <0x50>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_ptn5110>; + pinctrl-names =3D "default"; + + typec_con: connector { + compatible =3D "usb-c-connector"; + data-role =3D "dual"; + label =3D "USB-C"; + op-sink-microwatt =3D <0>; + power-role =3D "dual"; + self-powered; + sink-pdos =3D ; + source-pdos =3D ; + try-power-role =3D "sink"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + typec_con_hs: endpoint { + remote-endpoint =3D <&usb3_data_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + typec_con_ss: endpoint { + remote-endpoint =3D <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c4>; + pinctrl-names =3D "default"; + status =3D "okay"; + + i2c4_gpio_expander_22: i2c4-gpio-expander@22 { + compatible =3D "nxp,pcal6524"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + gpio-line-names =3D "USB2 Power Enable", + "DCDC5V Enable", + "", + "SE Enable", + "", + "EXP 5V Enable", + "EXP 3V3 Enable", + "WIFI Power Enable", + "M2 DIS1 B", + "WIFI SD3 Reset", + "EXP 1V8 Enable", + "CAN1 Standby", + "M2 DIS2", + "CAN2 Standby", + "ETH 10G IO4", + "ETH 10G IO3", + "SPI3/GPIO select", + "EXP 12V Enable", + "DCDC 3V3 Enable", + "PCIE1 Reset", + "", + "ETH 10G CLK Enable", + "LVDS to HDMI converter IT6263 reset", + ""; + + /* When high, select lpspi; When low, select gpio. */ + lpspi-gpio-sel-hog { + gpios =3D <16 GPIO_ACTIVE_HIGH>; + gpio-hog; + output-high; + }; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_pdm>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mqs1 { + clocks =3D <&scmi_clk IMX95_CLK_SAI1>; + clock-names =3D "mclk"; + pinctrl-0 =3D <&pinctrl_mqs1>; + pinctrl-names =3D "default"; + status =3D "okay"; + + mqs1_port: port { + mqs1_ep: endpoint { + dai-format =3D "left_j"; + remote-endpoint =3D <&sai1_port1_ep>; + }; + }; +}; + +&netc_blk_ctrl { + status =3D "okay"; +}; + +&netc_emdio { + pinctrl-0 =3D <&pinctrl_emdio>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethphy0: ethernet-phy@1 { + reg =3D <1>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&i2c3_gpio_expander_20 1 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg =3D <2>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&i2c3_gpio_expander_20 2 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status =3D "okay"; +}; + +&netcmix_blk_ctrl { + status =3D "okay"; +}; + +&pcie0 { + pinctrl-0 =3D <&pinctrl_pcie0>; + pinctrl-names =3D "default"; + reset-gpio =3D <&i2c4_gpio_expander_22 19 GPIO_ACTIVE_LOW>; + vpcie-supply =3D <®_m2_mkey_1_pwr>; + status =3D "okay"; +}; + +&pcie1 { + pinctrl-0 =3D <&pinctrl_pcie1>; + pinctrl-names =3D "default"; + reset-gpio =3D <&i2c3_gpio_expander_20 9 GPIO_ACTIVE_LOW>; + vpcie-supply =3D <®_m2_mkey_2_pwr>; + status =3D "okay"; +}; + +&sai1 { + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll1= 1k"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, + <3612672000>, <393216000>, + <361267200>, <24576000>; + #sound-dai-cells =3D <0>; + fsl,sai-mclk-direction-output; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* leave unconnected - no RX in the context of MQS */ + port@0 { + reg =3D <0>; + + endpoint { + }; + }; + + sai1_port1: port@1 { + reg =3D <1>; + mclk-fs =3D <512>; + + sai1_port1_ep: endpoint { + dai-format =3D "left_j"; + system-clock-direction-out; + bitclock-master; + frame-master; + remote-endpoint =3D <&mqs1_ep>; + }; + }; + }; +}; + +&sai5 { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_sai5>; + pinctrl-names =3D "default"; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&scmi_iomuxc { + pinctrl-0 =3D <&pinctrl_hog>; + pinctrl-names =3D "default"; + + pinctrl_emdio: emdiogrp { + fsl,pins =3D < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins =3D < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins =3D < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x39e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins =3D < + IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e + IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins =3D < + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins =3D < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins =3D < + IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins =3D < + IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e + IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x31e + IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x31e + IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids =3D ; +}; + +&thermal_zones { + pf09-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf09_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device =3D <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip =3D <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5301_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5302_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; + +&usb3 { + status =3D "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode =3D "otg"; + hnp-disable; + role-switch-default-mode =3D "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status =3D "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint =3D <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db =3D <17>; + fsl,phy-pcs-tx-swing-full-percent =3D <100>; + fsl,phy-tx-preemp-amp-tune-microamp =3D <600>; + fsl,phy-tx-vboost-level-microvolt =3D <1156>; + fsl,phy-tx-vref-tune-percent =3D <100>; + status =3D "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint =3D <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width =3D <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc1>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + status =3D "okay"; +}; + +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc2_vmmc>; + status =3D "okay"; +}; + +&usdhc3 { + bus-width =3D <4>; + keep-power-in-suspend; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc3>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc3_vmmc>; + wakeup-source; + status =3D "okay"; +}; + +&wdog3 { + status =3D "okay"; +}; --=20 2.34.1