From nobody Mon May 25 05:14:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82EB1410D3E for ; Mon, 18 May 2026 12:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779107814; cv=none; b=Ls4AC4bvpeCY8erIUNhLMTHYg6kaQ6/hmvQBLS8v+3BOBzGCYHMalk2+45qI7BPciZuCqOpHjg2Ue+DvRS/uWPhV6zeNdJAopiOARpye98tu5o58/WMSaX2Mau0tSVQdUglAjoCDP2viEFtemlbLcQV4hwIdLx+plpkP82T5ytE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779107814; c=relaxed/simple; bh=JBidQyToPgq/Heh6FBQEZB0gs8rurptz/JSX5ZuMLF0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jni+GGa3ZF/uJ1inEXeZH7X/71cDSTJ2ExIuQKY4ZcM6SDizkdy54GIZo3qT/L3/JxNisE3swZADMMIUtnzE4SNgSxh6y7CkeCcFFRh5FkUcZKiHwfRUQh/noK61aeUysuOG3t0gIIwlgB/WLGSDUSaveHF32nNn1Q1AAVwt9Fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=PAR/TuTs; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="PAR/TuTs" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 1D408C2B9E8 for ; Mon, 18 May 2026 12:37:44 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 58FBC5FFA3; Mon, 18 May 2026 12:36:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1B49F11AF87C6; Mon, 18 May 2026 14:36:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1779107810; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=HUM3MhDA3LMO5Vhb5PmHnSmyWsfq2kjj/K5Qlgk4b2Q=; b=PAR/TuTsx+7xlo3FFO7hDQiKNGvDgBSfkd3Ox4kCDH/4X4ZCmdmvEGO2D6qXt80JbPubBb 0Yb8DXDxQjsqyQDJi9Ja5FI7QyEeP2qJVxQ1+lhjkEibqVwCcUcfxRMvVZHhlqCPZdz+PW uzQuFudRSC2GihNSbDoQILNnMUaio2xvaMf9QzfuWUTx2LBXNCN3Pg67hnVRXrrN56QPR8 PWNf/TpQsiBIQzjvkWDR/bV6cfNDY1A7p4f8i4dhoXuxl2Tm57+ihFevTLAiwduobNRIB/ deXForTxtIS3N5cK2xevgGrHOyjDmYXuFdawWzSP+jwXHiwXsbh8rCxZwpz7QA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 18 May 2026 14:36:44 +0200 Subject: [PATCH v4 1/2] dmaengine: fsl-edma: Implement device_prep_peripheral_dma_vec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-fsl-edma-dyn-sg-v4-1-8ce7d95b1ce9@bootlin.com> References: <20260518-fsl-edma-dyn-sg-v4-0-8ce7d95b1ce9@bootlin.com> In-Reply-To: <20260518-fsl-edma-dyn-sg-v4-0-8ce7d95b1ce9@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Add implementation of .device_prep_peripheral_dma_vec() callback to setup a scatter/gather DMA transfer from an array of dma_vec structures. Setup a cyclic transfer if the DMA_PREP_REPEAT flag is set. Reviewed-by: Frank Li Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 109 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/dma/fsl-edma-common.h | 4 ++ drivers/dma/fsl-edma-main.c | 2 + 3 files changed, 115 insertions(+) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index bb7531c456df..c10190164926 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -673,6 +673,115 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyc= lic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 +struct dma_async_tx_descriptor * +fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan, const struct dma_v= ec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); + dma_addr_t src_addr, dst_addr, last_sg; + struct fsl_edma_desc *fsl_desc; + u16 soff, doff, iter; + u32 nbytes; + int i; + + if (!is_slave_direction(direction)) + return NULL; + + if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) + return NULL; + + fsl_desc =3D fsl_edma_alloc_desc(fsl_chan, nb); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic =3D flags & DMA_PREP_REPEAT; + fsl_desc->dirn =3D direction; + + if (direction =3D=3D DMA_MEM_TO_DEV) { + if (!fsl_chan->cfg.src_addr_width) + fsl_chan->cfg.src_addr_width =3D fsl_chan->cfg.dst_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.dst_addr_width * fsl_chan->cfg.dst_maxburst; + } else { + if (!fsl_chan->cfg.dst_addr_width) + fsl_chan->cfg.dst_addr_width =3D fsl_chan->cfg.src_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.src_addr_width * fsl_chan->cfg.src_maxburst; + } + + for (i =3D 0; i < nb; i++) { + if (direction =3D=3D DMA_MEM_TO_DEV) { + src_addr =3D vecs[i].addr; + dst_addr =3D fsl_chan->dma_dev_addr; + soff =3D fsl_chan->cfg.dst_addr_width; + doff =3D 0; + } else if (direction =3D=3D DMA_DEV_TO_MEM) { + src_addr =3D fsl_chan->dma_dev_addr; + dst_addr =3D vecs[i].addr; + soff =3D 0; + doff =3D fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr =3D fsl_chan->cfg.src_addr; + dst_addr =3D fsl_chan->cfg.dst_addr; + soff =3D 0; + doff =3D 0; + } + + /* + * Choose the suitable burst length if dma_vec length is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (vecs[i].len % nbytes) { + u32 width =3D (direction =3D=3D DMA_DEV_TO_MEM) ? doff : soff; + u32 burst =3D (direction =3D=3D DMA_DEV_TO_MEM) ? + fsl_chan->cfg.src_maxburst : + fsl_chan->cfg.dst_maxburst; + int j; + + for (j =3D burst; j > 1; j--) { + if (!(vecs[i].len % (j * width))) { + nbytes =3D j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j =3D=3D 1) + nbytes =3D width; + } + + iter =3D vecs[i].len / nbytes; + if (i < nb - 1) { + last_sg =3D fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + false, false, true); + } else { + if (fsl_desc->iscyclic) { + last_sg =3D fsl_desc->tcd[0].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, false, true); + } else { + last_sg =3D 0; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, true, false); + } + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 205a96489094..0d028048701d 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -496,6 +496,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cycl= ic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags); +struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( + struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 36155ab1602a..6693b4270a1a 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -841,6 +841,8 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.device_free_chan_resources =3D fsl_edma_free_chan_resources; fsl_edma->dma_dev.device_tx_status =3D fsl_edma_tx_status; + fsl_edma->dma_dev.device_prep_peripheral_dma_vec + =3D fsl_edma_prep_peripheral_dma_vec; fsl_edma->dma_dev.device_prep_slave_sg =3D fsl_edma_prep_slave_sg; fsl_edma->dma_dev.device_prep_dma_cyclic =3D fsl_edma_prep_dma_cyclic; fsl_edma->dma_dev.device_prep_dma_memcpy =3D fsl_edma_prep_memcpy; --=20 2.54.0 From nobody Mon May 25 05:14:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1C94413226 for ; Mon, 18 May 2026 12:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779107815; cv=none; b=Mq5109j5pBiPLlBsT+2yx7LkYw3w92ZfFSCqEQSy+GyHFo0tkv5q+pv9MZu5gEECpbU/QKN4IqFD4ihFBM6OYd+EP9mwC2FDZTzUV/JNQEw9b/2n6kraWnegrWCJQkvgeRLkexoj1y7WJP2H+3UCCdvhTs8Ej2ZZgbuyEPIG268= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779107815; c=relaxed/simple; bh=G7RMPyishAieeB8BYJsbiqtbGJJSNDe3OdP3a3YfKMA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i6Hrzry6bysci7VzgHrFLNJ2WO+a6bbqCImeXaBfOfwgJaXSUY12c9ULBW3tatuaxWMY0Fb3hytr0o5JNeKF6m+WAMxWCL3vXfbQ1lrEA3r/wJ6SiI2Il5ZKDnCkDeQst2M0GvQ6YdHTtgXy76H6mohC2IDGgIvEyZ/O5p8hSzo= ARC-Authentication-Results: i=1; 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Mon, 18 May 2026 14:36:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1779107811; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fS5jED2APYID6ACtGXnR88TqQ9pgAD4ONbbk9HSWgmM=; b=2opEB9CiqtgfLj2wA73JbNFxid9Q1IS4772mMWybrumJib0vh//fq+1e2dkBn7Dm1ZaEUL hOeClOiJkfc/g4pJE/r4gaqN201xgC67FU78qJDzfPdEHmWfClw8f3Yp0JyaGqYQMVLRoq VQao6pXpKbl5momtsQjLnYdUqBcEIUhE0szEqE4cWKJkTLc7Vsso215EaNSLetepfagv7I FEJeTTRtI6TPw9OQ3ogmbIjZDQuDnPz6+sabL0rAO8G/2hcsVtitwENCfkRiWFH0/Xxl2a obH9SWE2vSVHkqAKxk24J6zi0/nRBiNFLnk/IJvHDRRBq8k+XN5q+yyxBHMUFA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 18 May 2026 14:36:45 +0200 Subject: [PATCH v4 2/2] dmaengine: fsl-edma: Support dynamic scatter/gather chaining Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-fsl-edma-dyn-sg-v4-2-8ce7d95b1ce9@bootlin.com> References: <20260518-fsl-edma-dyn-sg-v4-0-8ce7d95b1ce9@bootlin.com> In-Reply-To: <20260518-fsl-edma-dyn-sg-v4-0-8ce7d95b1ce9@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Implement dynamic linking of scatter/gather transfers to enable chaining multiple DMA descriptors without stopping the channel. This avoids waiting for the channel to go idle if there is another transaction already issued. Add fsl_edma_link_sg() to dynamically link the last TCD of a previously submitted descriptor to the first TCD of a new descriptor by setting the scatter/gather address and the E_SG flag, and keeping the channel active by clearing the DREQ bit. Linking is done when the transaction is submitted by fsl_edma_tx_submit(). To do so, the .tx_submit() callback is overridden for non-cyclic transactions prepared by fsl_edma_prep_peripheral_dma_vec() and fsl_edma_prep_slave_sg(). This ensures that transactions are linked in the order they are submitted. Update fsl_edma_xfer_desc() to avoid re-initializing the hardware when a transfer is already in progress, allowing seamless chaining of descriptors. Modify the transfer completion handler to check the DONE flag in the channel CSR before marking the transfer complete. Since this flag is only available on SoC with the split registers layout, we only link transactions for DMA controllers flagged with FSL_EDMA_DRV_SPLIT_REG. Add trace event for scatter/gather linking operations. Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 90 +++++++++++++++++++++++++++++++++++++++= ---- drivers/dma/fsl-edma-trace.h | 5 +++ 2 files changed, 88 insertions(+), 7 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index c10190164926..6e5820051f29 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -58,7 +58,10 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_= chan) list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc =3D NULL; - fsl_chan->status =3D DMA_COMPLETE; + if (!(fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) || + (edma_readl_chreg(fsl_chan, ch_csr) & EDMA_V3_CH_CSR_DONE)) { + fsl_chan->status =3D DMA_COMPLETE; + } } else { vchan_cyclic_callback(&fsl_chan->edesc->vdesc); } @@ -673,6 +676,68 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cycl= ic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fsl_ed= ma_desc *fsl_desc) +{ + u32 flags =3D fsl_edma_drvflags(fsl_chan); + struct fsl_edma_hw_tcd *last_tcd; + struct fsl_edma_desc *prev_desc; + struct virt_dma_desc *vdesc; + u16 csr; + + lockdep_assert_held(&fsl_chan->vchan.lock); + + if (!(flags & FSL_EDMA_DRV_SPLIT_REG)) + return; + + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_submitted, + struct virt_dma_desc, node); + if (!vdesc) + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_issued, + struct virt_dma_desc, node); + if (!vdesc) + return; + + prev_desc =3D to_fsl_edma_desc(vdesc); + last_tcd =3D prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; + + csr =3D fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); + if (!(csr & EDMA_TCD_CSR_D_REQ)) + return; + + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dlast_s= ga); + + csr &=3D ~EDMA_TCD_CSR_D_REQ; + csr |=3D EDMA_TCD_CSR_E_SG; + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, csr, csr); + + if (prev_desc =3D=3D fsl_chan->edesc && prev_desc->n_tcds =3D=3D 1) { + if (flags & FSL_EDMA_DRV_CLEAR_DONE_E_SG) + edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); + + edma_cp_tcd_to_reg(fsl_chan, last_tcd, dlast_sga); + edma_cp_tcd_to_reg(fsl_chan, last_tcd, csr); + } + + trace_edma_link_sg(fsl_chan, last_tcd); +} + +static dma_cookie_t fsl_edma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct virt_dma_desc *vd =3D container_of(tx, struct virt_dma_desc, tx); + struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(tx->chan); + struct fsl_edma_desc *fsl_desc =3D to_fsl_edma_desc(vd); + struct virt_dma_chan *vc =3D to_virt_chan(tx->chan); + dma_cookie_t cookie; + + guard(spinlock_irqsave)(&fsl_chan->vchan.lock); + + fsl_edma_link_sg(fsl_chan, fsl_desc); + cookie =3D dma_cookie_assign(tx); + list_move_tail(&vd->node, &vc->desc_submitted); + + return cookie; +} + struct dma_async_tx_descriptor * fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan, const struct dma_v= ec *vecs, size_t nb, enum dma_transfer_direction direction, @@ -680,6 +745,7 @@ fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan,= const struct dma_vec *ve { struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); dma_addr_t src_addr, dst_addr, last_sg; + struct dma_async_tx_descriptor *tx; struct fsl_edma_desc *fsl_desc; u16 soff, doff, iter; u32 nbytes; @@ -779,7 +845,10 @@ fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan= , const struct dma_vec *ve } } =20 - return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + tx =3D vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + if (!fsl_desc->iscyclic) + tx->tx_submit =3D fsl_edma_tx_submit; + return tx; } =20 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( @@ -788,9 +857,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( unsigned long flags, void *context) { struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); + dma_addr_t src_addr, dst_addr, last_sg; + struct dma_async_tx_descriptor *tx; struct fsl_edma_desc *fsl_desc; struct scatterlist *sg; - dma_addr_t src_addr, dst_addr, last_sg; u16 soff, doff, iter; u32 nbytes; int i; @@ -882,7 +952,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( } } =20 - return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + tx =3D vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + tx->tx_submit =3D fsl_edma_tx_submit; + + return tx; } =20 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan, @@ -924,9 +997,12 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) if (!vdesc) return; fsl_chan->edesc =3D to_fsl_edma_desc(vdesc); - fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); - fsl_edma_enable_request(fsl_chan); - fsl_chan->status =3D DMA_IN_PROGRESS; + + if (fsl_chan->status !=3D DMA_IN_PROGRESS) { + fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma_enable_request(fsl_chan); + fsl_chan->status =3D DMA_IN_PROGRESS; + } } =20 void fsl_edma_issue_pending(struct dma_chan *chan) diff --git a/drivers/dma/fsl-edma-trace.h b/drivers/dma/fsl-edma-trace.h index d3541301a247..ac319d2dbb90 100644 --- a/drivers/dma/fsl-edma-trace.h +++ b/drivers/dma/fsl-edma-trace.h @@ -119,6 +119,11 @@ DEFINE_EVENT(edma_log_tcd, edma_fill_tcd, TP_ARGS(chan, tcd) ); =20 +DEFINE_EVENT(edma_log_tcd, edma_link_sg, + TP_PROTO(struct fsl_edma_chan *chan, void *tcd), + TP_ARGS(chan, tcd) +); + #endif =20 /* this part must be outside header guard */ --=20 2.54.0