From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A300433ADAD; Mon, 18 May 2026 11:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103795; cv=none; b=PtOjoq9J0WHO7S0CuZ9iCoxsCqV6mnEEVVqSPOcK+z/jsF6GzOMIOQykqk+HVaWyspPRO3JKqHxxw+CE5PhiVzcfvCGYGReHa7jbsVY51DR43gRBXBmnIDtQGKXEJ0FDZvTgRcmj7wEmMs7dpCm2eL7y1uzJeSTOCDdFEC9HOjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103795; c=relaxed/simple; bh=+bDa60wNtgw5ZkxVhKiwLfuDt6fHkP58C4HJF2lBzDs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dOnjgTjG10Z9mrv8ChKFfp0OiOvqftCX3KpRCCz3/OMkJn3IRSColNpiYEBKycfPduWTqMsvxwg0Kr2FsmMlqKl+mDdCrJ9T4Vbkpb6r3Jp2YxfeZrUcBWW1kVdYwLBGZVp4isYhrKvKH9NmCJQWMNZHqmuG0kPvYsTP8egCPQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Rp08nDHA; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Rp08nDHA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779103793; x=1810639793; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=+bDa60wNtgw5ZkxVhKiwLfuDt6fHkP58C4HJF2lBzDs=; b=Rp08nDHAs/fvA7xH/iQ5mLstk3Ig6Q8CJniXk1Okiy/7wFYmp8HdsUfO 33GbmBsyLgMM5CYXuh3N1SpfK5XyiXxH1aZ2IDRigkcGxl8MS0aGpU0IJ BKYwRrtd9NWHQnjh82uQSv/pC3ZGCFnUPu76qwG3+W/Q30hIkkD6ruTCG 941nH2k6F4v15Mz7iLRdakJHc6o8ixL0d0PGQ09uqY6cDx9LzqZ9+1Lgk h61mNhR6EzB5aU7t/iaJTxJIKM97lIjMzBUn40AM29Q6UWDx+qXPxmXUx fc2uyUPdvrZzKJNQjIUIqZXpD7F1EtpvHaCqy1gTy+5cb9SZE2eZrMm8K g==; X-CSE-ConnectionGUID: 8gjqCgtnTUKW+SeJOeKvlg== X-CSE-MsgGUID: HhrNaQ/hSwe/+h/dDOzGAA== X-IronPort-AV: E=Sophos;i="6.23,241,1770620400"; d="scan'208";a="57659227" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 04:29:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 18 May 2026 04:29:49 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:29:45 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:39 +0530 Subject: [PATCH v4 01/12] media: microchip-isc: fix SBGGR10 Bayer pattern Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-1-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , X-Mailer: b4 0.14.3 SBGGR10 was mapped to ISC_BAY_CFG_RGRG instead of ISC_BAY_CFG_BGBG, causing red/blue channel swap. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev --- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index b0302dfc3278..ca23e8adecbd 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -156,7 +156,7 @@ static struct isc_format sama7g5_formats_list[] =3D { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg =3D ISC_BAY_CFG_RGRG, + .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBC563F58F3; Mon, 18 May 2026 11:29:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103799; cv=none; b=KqA21/i6mZrETIbVGVflpExLEqAABuRv4IFkAusi0c/HOfJb3k1bVfFH0brdSzbTqJKsdnrpq8FKYMdWnk7VaKJM8hx3Q9KIY3LmOZFnH56ZpLYj3J3r5p8aydOVWCecZEwXwhiotyI2wkXYyXKRTd3WRlJUoR1HceuPDPrFWQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103799; c=relaxed/simple; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mVBJnXGNm5m6Rs9nWZcMGdP33t/o0yHhi9+Y1Pfl9ReN3px2fBaZty4ePooMLFLlM5Iy3cmJQzg+EdezZEzOV1ogW1Nsjxa0Spo7OsXIMkM5lSQZLk6ZzV8LzR1P/mNheApRZh49CPwHTfr4SBp1oYldHPinwVP5ve67S1PbQvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=KlRRwiGy; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KlRRwiGy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779103798; x=1810639798; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=gvdrgbWAjTx1CGi+PD6csR2l/AwBIyyRN8PqO/RwaYE=; b=KlRRwiGyIWEAGh0NKGnqMybHfeEV3FNf1PG7CNsdTzlKO86XiRwUBZuX zqFBMekIDcv8EycmMB7CsL9Rz8sK6bk9FKyiWVgzmHsn7u2gcxIzBfE4a t3p9WgSDZ/Gz74FiGkzLg/RHfvCTVU6IavwSXsz+8muvUDk3osRaHv/eb w15jW+FdRk8U39x8YhehaDKLIHUnGmc9Ti5SgOJ50iRl+q34LvxeRrakP f1HDqgGdUcNJdrvj3r+8er3jpTnkCK+564EYnm+KG2WPFI37ha7jQH8i5 Q2gZGQ3ucaMDe3fG/P6iHO4p4WGkbcX9nU8NuZq6gO9lr3sQfQV1EQym6 Q==; X-CSE-ConnectionGUID: McQheJilRZ2djUWa0gKEtA== X-CSE-MsgGUID: BU/mtQk+TyO06ys8r0i12g== X-IronPort-AV: E=Sophos;i="6.23,241,1770620400"; d="scan'208";a="57659229" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 May 2026 04:29:56 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 18 May 2026 04:29:55 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:29:50 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:40 +0530 Subject: [PATCH v4 02/12] media: microchip-isc: mask WB offset and gain register fields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-2-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , X-Mailer: b4 0.14.3 ISC_WB_O_* and ISC_WB_G_* pack two 13-bit fields per register. Sign extension from negative offsets corrupts the upper field. Mask both fields to 13 bits before packing. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 21 +++++++++++++----= ---- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45b94f1e89d8 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -61,18 +61,23 @@ static inline void isc_update_awb_ctrls(struct isc_devi= ce *isc) =20 /* In here we set our actual hw pipeline config */ =20 + /* + * Mask offset fields to 13 bits. Sign extension of negative s32 + * values would otherwise corrupt the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); + /* Gains are 13-bit unsigned fields [12:0] and [28:16] */ regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); 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Mon, 18 May 2026 04:29:59 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:29:55 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:41 +0530 Subject: [PATCH v4 03/12] media: microchip-isc: fix race condition on stream stop Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-3-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , X-Mailer: b4 0.14.3 Disable histogram and drain AWB work queue before releasing DMA buffers to prevent use-after-free if histogram IRQ fires during stream stop. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 19 +++++++++++++++= ++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 45b94f1e89d8..b19c5a63b4bd 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -427,6 +427,14 @@ static void isc_stop_streaming(struct vb2_queue *vq) =20 mutex_unlock(&isc->awb_mutex); =20 + /* + * Disable the histogram so the ISR stops firing HISREQ, then drain + * any work that was already queued before returning. This must happen + * after releasing awb_mutex because isc_awb_work also takes it. + */ + isc_set_histogram(isc, false); + cancel_work_sync(&isc->awb_work); + /* Disable DMA interrupt */ regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); =20 @@ -1519,10 +1527,17 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) } mutex_unlock(&isc->awb_mutex); =20 - /* if we have autowhitebalance on, start histogram procedure */ + /* + * If AWB auto mode is requested and we are streaming RAW, + * start the histogram procedure, but only if it is not + * already running. Repeated enable requests would reset + * hist_id, preventing the 4-channel Bayer cycle from + * completing. + */ if (ctrls->awb =3D=3D ISC_WB_AUTO && vb2_is_streaming(&isc->vb2_vidq) && - ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code) && + ctrls->hist_stat !=3D HIST_ENABLED) isc_set_histogram(isc, true); =20 /* --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85B133F7860; Mon, 18 May 2026 11:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103815; cv=none; b=PCE7ymw3FmNUkDaDj9C8NTvCjKyXQ8F8p4b7b0PxjbbhI7EvwZM99TEMiXf2k6TYY6gAYBYsZxVfaol5Sx4nA7y8+pbwdfX2YAb1vq8r/7IWXtWXGgeKwoj5A4dvyKp7bw+FX5oXWnFRZU6AQKt/QAfintnVhKILByGDX+pQ6FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103815; c=relaxed/simple; bh=Twnhndhk/I+hM9JdMgDlMxxxoumz64llnmr2+0oOHdI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=At/t9AAcHl4H7dAfVbbMrzFghwW6yRThtADQKo30iL+8oSgyhWLu20m2HesaaKAKmYk2kBdc5g6Pijd6mEQDWzcBtvrnFAdeYwHr2ptIpgyDfBaVMtbQnQamMN0Wq0rh6UfJKCP5VY5Ki3jXyZlBe0/BvvRZPi2DXBBpnZGSi1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=BW7abmFO; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BW7abmFO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779103812; x=1810639812; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Twnhndhk/I+hM9JdMgDlMxxxoumz64llnmr2+0oOHdI=; b=BW7abmFOWjVfWhJAvxjrFNwKYB2SnQ9e5imW8VEf4URfHWRLgHFWL2oH afhbqobHDov62tfc4zkCZZpqR03jW3Ec0QhyvUCH6eVX9scwFtQisxPYa QoIwcdZV+QWkiEdpVF3dSwg/teHnNK5irO84Wz3F6skao7ahNx34Y1ryw w7QhHt3Px7+4j/1PbG4EIk26WRDEPXo3yGsgTIqilau6vT5szK19n8JcX dY/no4NJEwrhfPhmaFuQ6dlTfHjX5CnYoMBpz/VgLK8PIN0+EuoLcjhSv 5fL5ggtrXEoqS3TJRieIfJ3yKkfTVRkqp7Ef0UhGyoLF7DfDzDObiPbRB g==; X-CSE-ConnectionGUID: U29+au9+SJSGO6+GxSoUFg== X-CSE-MsgGUID: dNBEj8r7QHisal6EarrYng== X-IronPort-AV: E=Sophos;i="6.23,241,1770620400"; d="scan'208";a="58070978" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 04:30:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 18 May 2026 04:30:03 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:29:59 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:42 +0530 Subject: [PATCH v4 04/12] media: microchip-isc: fix PM runtime leak in AWB work handler Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-4-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , X-Mailer: b4 0.14.3 Early return when streaming stops skips pm_runtime_put_sync(), leaking the reference and preventing runtime suspend. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev --- drivers/media/platform/microchip/microchip-isc-base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index b19c5a63b4bd..f61a5d5a3e04 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1429,7 +1429,7 @@ static void isc_awb_work(struct work_struct *w) /* streaming is not active anymore */ if (isc->stop) { mutex_unlock(&isc->awb_mutex); - return; + goto out_pm_put; } =20 isc_update_profile(isc); @@ -1440,6 +1440,7 @@ static void isc_awb_work(struct work_struct *w) if (ctrls->awb) regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); =20 +out_pm_put: pm_runtime_put_sync(isc->dev); } =20 --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 481F13F6C5C; Mon, 18 May 2026 11:30:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103812; cv=none; b=oYyPU7aj0SHsuOvmfgx7XJA334rZYdE7Ew/6bXF/rP3XFozePI+sJPG5+9ivNO8SXwDsREc/iHqsChFDocAInRJjVwNS0jQ/W/xyaLP9qKiDN6E6dOZj/Cqh0RZLrGOlpHJJYvRO1r+u5V1YiKiHRBP3TnF1n9PhjWk2EH1VSFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103812; c=relaxed/simple; bh=tIPzbHjktUKJyUNaMWj69c6dOkLPHyPZt6qx4G/J1iM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rp64K0SzNvFjzf9oUvbTMr5E35KOZFIolJmdkEZRIavE89rKn9n61SLqhvEqzDaOE6/pBD0hKAAMshf9Ewhu49hZATMncItl8TzWRiofk6wa572v3TD8zijFu383tM4bGEiFKbW0kT3f8DQc35sbk/OJDCMwPBtNq3iffK6UIW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=A802PHY9; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="A802PHY9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779103809; x=1810639809; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=tIPzbHjktUKJyUNaMWj69c6dOkLPHyPZt6qx4G/J1iM=; b=A802PHY9yLfY3NrQDOJwHmh/B3P5BVuudWoPMUkd51S9mhBjDo9R31kF LdaaKF0zBfgHljL0ewpcwFQRCHgufiSRUB7dYrVfLvmUeXvpcVVBulEJy RIf9gPa08LLVOPr7jQztuOQ/u13lkMwOp6cX/8EmNKgr/tJYe2hWiDkl8 wSI4t6cnRoe3/1IhEg5J8N02XmVDH0p3D3pP3YN7VLoEANwFPOgZoe7TY yM91FGHlbQqOI7EYjpzTehS4W4NnxyHTlAx6HkrDpf49G2w8wt+MKOZS0 3LtQMkwmCG6iMYTIdSo7R62dp1icZBw/28fMvLO8ODg5+Tl5aiK6zg7+W Q==; X-CSE-ConnectionGUID: uTzkBJghSh2aWlyoa4M9MQ== X-CSE-MsgGUID: Kf8P9f0tQ9i0jccudbh9cQ== X-IronPort-AV: E=Sophos;i="6.23,241,1770620400"; d="scan'208";a="289025038" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 04:30:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 18 May 2026 04:30:07 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:30:03 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:43 +0530 Subject: [PATCH v4 05/12] media: microchip-isc: add driver documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-5-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus X-Mailer: b4 0.14.3 Document V4L2 controls and pipeline modes for ISC/XISC camera interface on SAMA5D2, SAMA7G5, and SAM9X7. Signed-off-by: Balakrishnan Sambath --- .../userspace-api/media/drivers/index.rst | 1 + .../userspace-api/media/drivers/microchip-isc.rst | 66 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 68 insertions(+) diff --git a/Documentation/userspace-api/media/drivers/index.rst b/Document= ation/userspace-api/media/drivers/index.rst index 02967c9b18d6..65ef6ba3523e 100644 --- a/Documentation/userspace-api/media/drivers/index.rst +++ b/Documentation/userspace-api/media/drivers/index.rst @@ -34,6 +34,7 @@ For more details see the file COPYING in the source distr= ibution of Linux. imx-uapi mali-c55 max2175 + microchip-isc npcm-video omap3isp-uapi thp7312 diff --git a/Documentation/userspace-api/media/drivers/microchip-isc.rst b/= Documentation/userspace-api/media/drivers/microchip-isc.rst new file mode 100644 index 000000000000..e065ae009595 --- /dev/null +++ b/Documentation/userspace-api/media/drivers/microchip-isc.rst @@ -0,0 +1,66 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Microchip ISC/XISC Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +The Image Sensor Controller (ISC) on SAMA5D2 and eXtended ISC (XISC) on +SAMA7G5/SAM9X7 provide camera capture with hardware image processing. + +Supported Hardware +------------------ + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SoC Controller Max Resolution Interface Hue/Saturation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SAMA5D2 ISC 2592x1944 12-bit parallel No +SAMA7G5 XISC 3264x2464 12-bit + CSI-2 Yes +SAM9X7 XISC 2560x1920 12-bit + CSI-2 Yes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +SAM9X7 shares the XISC pipeline with SAMA7G5 but has a smaller internal +line buffer, limiting horizontal resolution to 2560 pixels. + +Controls +-------- + +Standard V4L2 controls: + +* ``V4L2_CID_BRIGHTNESS``: -1024..1023, default 0 +* ``V4L2_CID_CONTRAST``: -2048..2047, default 256 (1.0x) +* ``V4L2_CID_GAMMA``: 0..2 selects curve (0=3D2.4, 1=3D2.2, 2=3D1.8) +* ``V4L2_CID_AUTO_WHITE_BALANCE``: Enable kernel Grey World AWB +* ``V4L2_CID_DO_WHITE_BALANCE``: Trigger one-shot AWB + +SAMA7G5/SAM9X7 add: + +* ``V4L2_CID_HUE``: -180..180 degrees +* ``V4L2_CID_SATURATION``: 0..255, default 16 + +Custom controls (defined in ``atmel-isc-media.h``): + +* ``ISC_CID_R_GAIN``, ``ISC_CID_B_GAIN``, ``ISC_CID_GR_GAIN``, + ``ISC_CID_GB_GAIN``: WB gains, 0..8191, Q2.9 (512 =3D 1.0x) +* ``ISC_CID_R_OFFSET``, ``ISC_CID_B_OFFSET``, ``ISC_CID_GR_OFFSET``, + ``ISC_CID_GB_OFFSET``: WB offsets, -4096..4095 + +Pipeline +-------- + +Pipeline modules: DPC -> WB -> CFA -> CC -> GAM -> CBHS/CBC -> CSC -> SUB + +* DPC: Defective Pixel Correction (XISC only), black level subtraction + to sensor bit depth, green disparity correction +* WB: White Balance gains/offsets +* CFA: Color Filter Array interpolation (demosaic) +* CC: Color Correction matrix +* GAM: Gamma correction (preset) +* CBHS: Contrast/Brightness/Hue/Saturation (XISC only) +* CBC: Contrast/Brightness (ISC only) +* CSC: Color Space Conversion (RGB to YCbCr) +* SUB: Chroma subsampling (4:2:2, 4:2:0) + +Pipeline usage depends on input and output formats: + +* Raw Bayer input, RGB output: DPC, WB, CFA, CC, GAM +* Raw Bayer input, YUV output: Full pipeline including CSC, CBHS/CBC, SUB +* Non-RAW input (YUV/RGB sensor): Pipeline bypassed diff --git a/MAINTAINERS b/MAINTAINERS index e08767323763..d4aa7e86e2bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17057,6 +17057,7 @@ L: linux-media@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/media/atmel,isc.yaml F: Documentation/devicetree/bindings/media/microchip,xisc.yaml +F: Documentation/userspace-api/media/drivers/microchip-isc.rst F: drivers/media/platform/microchip/microchip-isc* F: drivers/media/platform/microchip/microchip-sama*-isc* F: drivers/staging/media/deprecated/atmel/atmel-isc* --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60EDA3F5BD6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-6-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , Balamanikandan Gunasundar X-Mailer: b4 0.14.3 SAM9X7 XISC uses the same image processing pipeline as SAMA7G5 but has a smaller internal line buffer. The reduced RAM constrains the maximum horizontal resolution to 2560 pixels (compared to 3264 on SAMA7G5), resulting in a maximum capture resolution of 2560x1920. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index ca23e8adecbd..4119cfe12cdf 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -55,6 +55,9 @@ #define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 #define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 =20 +#define ISC_SAM9X7_MAX_SUPPORT_WIDTH 2560 +#define ISC_SAM9X7_MAX_SUPPORT_HEIGHT 1920 + #define ISC_SAMA7G5_PIPELINE \ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) @@ -432,8 +435,13 @@ static int microchip_xisc_probe(struct platform_device= *pdev) isc->gamma_table =3D isc_sama7g5_gamma_table; isc->gamma_max =3D 0; =20 - isc->max_width =3D ISC_SAMA7G5_MAX_SUPPORT_WIDTH; - isc->max_height =3D ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + if (of_machine_is_compatible("microchip,sam9x7")) { + isc->max_width =3D ISC_SAM9X7_MAX_SUPPORT_WIDTH; + isc->max_height =3D ISC_SAM9X7_MAX_SUPPORT_HEIGHT; + } else { + isc->max_width =3D ISC_SAMA7G5_MAX_SUPPORT_WIDTH; + isc->max_height =3D ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + } =20 isc->config_dpc =3D isc_sama7g5_config_dpc; isc->config_csc =3D isc_sama7g5_config_csc; --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C88B33F5BD5; Mon, 18 May 2026 11:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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18 May 2026 04:30:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 18 May 2026 04:30:32 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:30:12 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:45 +0530 Subject: [PATCH v4 07/12] media: microchip-isc: configure DPC and pipeline for SAMA7G5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-7-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , Balamanikandan Gunasundar X-Mailer: b4 0.14.3 Enable DPC_GDCENABLE for RGB output. Disable pipeline for raw Bayer passthrough to provide unmodified sensor data for software ISP. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 7 ++----- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 3 ++- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index f61a5d5a3e04..23a09ed12946 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -800,7 +800,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | - CC_ENABLE; + DPC_GDCENABLE | CC_ENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -850,10 +850,7 @@ static int isc_try_configure_pipeline(struct isc_devic= e *isc) } break; default: - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) - isc->try_config.bits_pipeline =3D WB_ENABLE | DPC_BLCENABLE; - else - isc->try_config.bits_pipeline =3D 0x0; + isc->try_config.bits_pipeline =3D 0x0; } =20 /* Tune the pipeline to product specific */ diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 4119cfe12cdf..04930aa0f289 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -59,7 +59,8 @@ #define ISC_SAM9X7_MAX_SUPPORT_HEIGHT 1920 =20 #define ISC_SAMA7G5_PIPELINE \ - (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + (DPC_DPCENABLE | DPC_GDCENABLE | DPC_BLCENABLE | \ + WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) =20 /* This is a list of the formats that the ISC can *output* */ --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED343EFFDB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-8-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , Balamanikandan Gunasundar X-Mailer: b4 0.14.3 Add gamma 1.8 and 2.4 curves alongside the existing 2.2 (sRGB). V4L2_CID_GAMMA selects preset curves: 0=3D2.4, 1=3D2.2, 2=3D1.8. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 3 +- .../platform/microchip/microchip-sama7g5-isc.c | 54 ++++++++++++++++--= ---- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 23a09ed12946..ae2a0c6ba566 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1647,8 +1647,7 @@ static int isc_ctrl_init(struct isc_device *isc) ctrls->brightness =3D 0; =20 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, - isc->gamma_max); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, 1); isc->awb_ctrl =3D v4l2_ctrl_new_std(hdl, &isc_awb_ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 04930aa0f289..8b73b625d92b 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -320,21 +320,47 @@ static void isc_sama7g5_adapt_pipeline(struct isc_dev= ice *isc) isc->try_config.bits_pipeline &=3D ISC_SAMA7G5_PIPELINE; } =20 -/* Gamma table with gamma 1/2.2 */ +/* Gamma tables with gamma values 0.42, 0.45(Default), 0.56 */ static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] =3D { - /* index 0 --> gamma bipartite */ + /* index 0 --> gamma bipartite 1/2.4(=3D0.42) */ { - 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, - 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, - 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, - 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, - 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, - 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, - 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, - 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, - 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, - 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, - 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, + 0x940, 0x4b0310, 0x630250, 0x7601d0, 0x840190, 0x910170, + 0x9d0150, 0xa80110, 0xb10110, 0xba0110, 0xc300f0, 0xcb00f0, + 0xd300e0, 0xda00e0, 0xe100c0, 0xe800c0, 0xee00c0, 0xf400c0, + 0xfa00a0, 0x10000a0, 0x10500a0, 0x10b00a0, 0x11000a0, 0x11500a0, + 0x11a0080, 0x11f0080, 0x1240080, 0x1290080, 0x12e0080, 0x1330070, + 0x1380070, 0x13c0070, 0x1410070, 0x17a0060, 0x1aa0052, 0x1d40046, + 0x1f90042, 0x21b003c, 0x23a0038, 0x2570034, 0x2720030, 0x28b002e, + 0x2a3002c, 0x2ba002a, 0x2d0002a, 0x2e60028, 0x2fa0026, 0x30e0026, + 0x3210024, 0x3330022, 0x3450022, 0x3560020, 0x3670020, 0x3770020, + 0x387001e, 0x396001e, 0x3a5001c, 0x3b3001c, 0x3c1001c, 0x3cf001a, + 0x3dd001a, 0x3eb0018, 0x3f90018, 0x4070016 }, + /* index 1 --> gamma bipartite 1/2.2(=3D0.45) */ + { + 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, + 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, + 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, + 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, + 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, + 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, + 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, + 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, + 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, + 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, + 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, + /* index 2 --> gamma bipartite 1/1.8(=3D0.56) */ + { + 0xa62, 0x4f0350, 0x680280, 0x7e0200, 0x8d01c0, 0x9a01a0, + 0xa50180, 0xb00140, 0xb90140, 0xc20120, 0xcb0120, 0xd30100, + 0xdb0100, 0xe300e0, 0xea00e0, 0xf100e0, 0xf700c0, 0xfd00c0, + 0x10300c0, 0x10900a0, 0x10e00a0, 0x11400a0, 0x11900a0, 0x11e00a0, + 0x12300a0, 0x12800a0, 0x12d0080, 0x1320080, 0x1370080, 0x13c0080, + 0x1410080, 0x1460080, 0x14a0070, 0x1830060, 0x1b40052, 0x1df0048, + 0x2040042, 0x2250040, 0x2440038, 0x2600036, 0x27b0032, 0x2940030, + 0x2ac002e, 0x2c4002c, 0x2da002a, 0x2f0002a, 0x3050028, 0x3190026, + 0x32c0026, 0x33e0024, 0x3500024, 0x3610022, 0x3720020, 0x3820020, + 0x3920020, 0x3a2001e, 0x3b1001e, 0x3c0001c, 0x3ce001c, 0x3dc001c, + 0x3ea001a, 0x3f8001a, 0x4060018, 0x4130018 }, }; =20 static int xisc_parse_dt(struct device *dev, struct isc_device *isc) @@ -434,7 +460,7 @@ static int microchip_xisc_probe(struct platform_device = *pdev) } =20 isc->gamma_table =3D isc_sama7g5_gamma_table; - isc->gamma_max =3D 0; + isc->gamma_max =3D 2; =20 if (of_machine_is_compatible("microchip,sam9x7")) { isc->max_width =3D ISC_SAM9X7_MAX_SUPPORT_WIDTH; --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75D5E3D5241; Mon, 18 May 2026 11:30:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779103850; cv=none; b=bE8JUyETfU6y1tJbUYwImM9RCGuEDL79SWpdOHdzlwz/xlRyjIla+8kQOai7RqhIjfaxKoHp7zzqlaU+hxb7BsEwZEjss6yutN3X1aqjQvz2OEwA9oSBntJV/fToXjrRSaFkYfK/DPaWuKS/UayIroVI8KoiDMqDLIiDJL0y1no= ARC-Message-Signature: i=1; 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Mon, 18 May 2026 04:30:42 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:30:38 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:47 +0530 Subject: [PATCH v4 09/12] media: microchip-isc: add SAMA7G5 hue and saturation controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-9-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus , Balamanikandan Gunasundar X-Mailer: b4 0.14.3 SAMA7G5 extends CBC with hue and saturation. Add V4L2_CID_HUE and V4L2_CID_SATURATION controls. Disable CBHS for RGB output since it operates in YCbCr domain. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 87 ++++++++++++++++++= +++- .../media/platform/microchip/microchip-isc-regs.h | 11 ++- drivers/media/platform/microchip/microchip-isc.h | 5 +- .../platform/microchip/microchip-sama5d2-isc.c | 2 +- .../platform/microchip/microchip-sama7g5-isc.c | 8 +- 5 files changed, 99 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index ae2a0c6ba566..1727c98665d1 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -810,7 +810,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | GAM_ENABLES | WB_ENABLE | - SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | + SUB420_ENABLE | SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; @@ -821,7 +821,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -833,7 +833,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -844,7 +844,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - CBC_ENABLE | DPC_BLCENABLE; + CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -859,6 +859,56 @@ static int isc_try_configure_pipeline(struct isc_devic= e *isc) return 0; } =20 +static bool isc_format_has_chroma(u32 fourcc) +{ + switch (fourcc) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + return true; + default: + return false; + } +} + +/* + * isc_update_cbc_ctrl_activity() - Activate/deactivate CBC controls + * + * Called from isc_set_fmt(), isc_link_validate(), and isc_ctrl_init(). + * At isc_ctrl_init() time isc->config.bits_pipeline is zero (no format + * has been negotiated yet), so all CBC controls are initially marked + * inactive. They become active once a format that includes CBHS in the + * pipeline is configured via VIDIOC_S_FMT or link validation. + */ +static void isc_update_cbc_ctrl_activity(struct isc_device *isc) +{ + struct v4l2_ctrl_handler *hdl =3D &isc->ctrls.handler; + struct v4l2_ctrl *brightness; + struct v4l2_ctrl *contrast; + struct v4l2_ctrl *hue; + struct v4l2_ctrl *saturation; + bool cbc_active =3D isc->config.bits_pipeline & CBHS_ENABLE; + bool chroma_active =3D cbc_active && isc_format_has_chroma(isc->config.fo= urcc); + + brightness =3D v4l2_ctrl_find(hdl, V4L2_CID_BRIGHTNESS); + if (brightness) + v4l2_ctrl_activate(brightness, cbc_active); + + contrast =3D v4l2_ctrl_find(hdl, V4L2_CID_CONTRAST); + if (contrast) + v4l2_ctrl_activate(contrast, cbc_active); + + hue =3D v4l2_ctrl_find(hdl, V4L2_CID_HUE); + if (hue) + v4l2_ctrl_activate(hue, chroma_active); + + saturation =3D v4l2_ctrl_find(hdl, V4L2_CID_SATURATION); + if (saturation) + v4l2_ctrl_activate(saturation, chroma_active); +} + static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f) { struct v4l2_pix_format *pixfmt =3D &f->fmt.pix; @@ -902,6 +952,7 @@ static int isc_set_fmt(struct isc_device *isc, struct v= 4l2_format *f) /* make the try configuration active */ isc->config =3D isc->try_config; isc->fmt =3D isc->try_fmt; + isc_update_cbc_ctrl_activity(isc); =20 dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n", (char *)&f->fmt.pix.pixelformat, @@ -989,6 +1040,7 @@ static int isc_link_validate(struct media_link *link) return ret; =20 isc->config =3D isc->try_config; + isc_update_cbc_ctrl_activity(isc); =20 dev_dbg(isc->dev, "New ISC configuration in place\n"); =20 @@ -1446,6 +1498,7 @@ static int isc_s_ctrl(struct v4l2_ctrl *ctrl) struct isc_device *isc =3D container_of(ctrl->handler, struct isc_device, ctrls.handler); struct isc_ctrls *ctrls =3D &isc->ctrls; + struct regmap *regmap =3D isc->regmap; =20 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) return 0; @@ -1453,9 +1506,30 @@ static int isc_s_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: ctrls->brightness =3D ctrl->val & ISC_CBC_BRIGHT_MASK; + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, ctrls->brightnes= s); break; case V4L2_CID_CONTRAST: ctrls->contrast =3D ctrl->val & ISC_CBC_CONTRAST_MASK; + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, ctrls->contras= t); + break; + case V4L2_CID_HUE: + if (isc->has_cbhs) { + ctrls->hue =3D ctrl->val & ISC_CBHS_HUE_MASK; + regmap_write(regmap, ISC_CBHS_HUE, ctrls->hue); + } + break; + case V4L2_CID_SATURATION: + if (isc->has_cbhs) { + /* + * The ISC CBHS SAT register holds a Q4 fixed-point + * coefficient: 0 =3D grayscale, 16 =3D 1.0 (no change), + * values above 16 boost saturation. The V4L2 range + * 0-100 (default 16) maps directly to this hardware + * value; no unit conversion is applied. + */ + ctrls->saturation =3D ctrl->val & ISC_CBHS_SAT_MASK; + regmap_write(regmap, ISC_CBHS_SAT, ctrls->saturation); + } break; case V4L2_CID_GAMMA: ctrls->gamma_index =3D ctrl->val; @@ -1647,6 +1721,10 @@ static int isc_ctrl_init(struct isc_device *isc) ctrls->brightness =3D 0; =20 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); + if (isc->has_cbhs) { + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE, -180, 180, 1, 0); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, 0, 100, 1, 16); + } v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, 1); isc->awb_ctrl =3D v4l2_ctrl_new_std(hdl, &isc_awb_ops, V4L2_CID_AUTO_WHITE_BALANCE, @@ -1664,6 +1742,7 @@ static int isc_ctrl_init(struct isc_device *isc) } =20 v4l2_ctrl_activate(isc->do_wb_ctrl, false); + isc_update_cbc_ctrl_activity(isc); =20 isc->r_gain_ctrl =3D v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); isc->b_gain_ctrl =3D v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/driver= s/media/platform/microchip/microchip-isc-regs.h index e77e1d9a1db8..2fd8916abf21 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -268,10 +268,13 @@ #define ISC_CBC_CONTRAST 0x000003c0 #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) =20 -/* Hue Register */ -#define ISC_CBCHS_HUE 0x4e0 -/* Saturation Register */ -#define ISC_CBCHS_SAT 0x4e4 +/* Hue Register: signed 9-bit two's complement, covers -180 to +180 degree= s */ +#define ISC_CBHS_HUE 0x4e0 +#define ISC_CBHS_HUE_MASK GENMASK(8, 0) + +/* Saturation Register: unsigned Q4 fixed-point (1.0 =3D 16, V4L2 range 0-= 100) */ +#define ISC_CBHS_SAT 0x4e4 +#define ISC_CBHS_SAT_MASK GENMASK(6, 0) =20 /* Offset for SUB422 register specific to sama5d2 product */ #define ISC_SAMA5D2_SUB422_OFFSET 0 diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index ad4e98a1dd8f..2c8bcaaa26ea 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -88,7 +88,7 @@ struct isc_format { #define GAM_RENABLE BIT(9) #define VHXS_ENABLE BIT(10) #define CSC_ENABLE BIT(11) -#define CBC_ENABLE BIT(12) +#define CBHS_ENABLE BIT(12) #define SUB422_ENABLE BIT(13) #define SUB420_ENABLE BIT(14) =20 @@ -139,6 +139,8 @@ struct isc_ctrls { =20 u32 brightness; u32 contrast; + u32 hue; + u32 saturation; u8 gamma_index; #define ISC_WB_NONE 0 #define ISC_WB_AUTO 1 @@ -342,6 +344,7 @@ struct isc_device { /* pointer to the defined gamma table */ const u32 (*gamma_table)[GAMMA_ENTRIES]; u32 gamma_max; + bool has_cbhs; =20 u32 max_width; u32 max_height; diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 66d3d7891991..239aac170472 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -54,7 +54,7 @@ =20 #define ISC_SAMA5D2_PIPELINE \ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + CBHS_ENABLE | SUB422_ENABLE | SUB420_ENABLE) =20 /* This is a list of the formats that the ISC can *output* */ static const struct isc_format sama5d2_controller_formats[] =3D { diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 8b73b625d92b..6705011edc2a 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -61,7 +61,7 @@ #define ISC_SAMA7G5_PIPELINE \ (DPC_DPCENABLE | DPC_GDCENABLE | DPC_BLCENABLE | \ WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + CBHS_ENABLE | SUB422_ENABLE | SUB420_ENABLE) =20 /* This is a list of the formats that the ISC can *output* */ static const struct isc_format sama7g5_controller_formats[] =3D { @@ -257,9 +257,8 @@ static void isc_sama7g5_config_cbc(struct isc_device *i= sc) /* Configure what is set via v4l2 ctrls */ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.bright= ness); regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.cont= rast); - /* Configure Hue and Saturation as neutral midpoint */ - regmap_write(regmap, ISC_CBCHS_HUE, 0); - regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); + regmap_write(regmap, ISC_CBHS_HUE, isc->ctrls.hue); + regmap_write(regmap, ISC_CBHS_SAT, isc->ctrls.saturation); } =20 static void isc_sama7g5_config_cc(struct isc_device *isc) @@ -461,6 +460,7 @@ static int microchip_xisc_probe(struct platform_device = *pdev) =20 isc->gamma_table =3D isc_sama7g5_gamma_table; isc->gamma_max =3D 2; + isc->has_cbhs =3D true; =20 if (of_machine_is_compatible("microchip,sam9x7")) { isc->max_width =3D ISC_SAM9X7_MAX_SUPPORT_WIDTH; --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C7993002BB; Mon, 18 May 2026 11:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="56879094" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 May 2026 04:30:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 18 May 2026 04:30:46 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:30:43 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:48 +0530 Subject: [PATCH v4 10/12] media: microchip-isc: use weighted averages for Grey World AWB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-10-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus X-Mailer: b4 0.14.3 Replace pixel counts with intensity-weighted averages. Add 2% outlier rejection at histogram tails. Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 167 +++++++++++++++--= ---- drivers/media/platform/microchip/microchip-isc.h | 2 + 2 files changed, 125 insertions(+), 44 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 1727c98665d1..67c2999ae5b5 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -39,6 +39,12 @@ (((mbus_code) =3D=3D MEDIA_BUS_FMT_Y10_1X10) | \ (((mbus_code) =3D=3D MEDIA_BUS_FMT_Y8_1X8))) =20 +/* 4.0 in Q9 fixed-point: cap grey-world correction at 4x. */ +#define ISC_AWB_GW_GAIN_MAX (4u << 9) + +/* Outlier rejection: skip darkest/brightest 2% of histogram. */ +#define ISC_AWB_OUTLIER_DIV 50 + static inline void isc_update_v4l2_ctrls(struct isc_device *isc) { struct isc_ctrls *ctrls =3D &isc->ctrls; @@ -1286,6 +1292,11 @@ static void isc_hist_count(struct isc_device *isc, u= 32 *min, u32 *max) u32 *hist_count =3D &ctrls->hist_count[ctrls->hist_id]; u32 *hist_entry =3D &ctrls->hist_entry[0]; u32 i; + u32 total_pixels; + u32 dark_threshold, bright_threshold; + u32 cumulative; + u64 weighted_sum; + u32 pixel_count; =20 *min =3D 0; *max =3D HIST_ENTRIES; @@ -1293,44 +1304,103 @@ static void isc_hist_count(struct isc_device *isc,= u32 *min, u32 *max) regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, hist_entry, HIST_ENTRIES); =20 - *hist_count =3D 0; - /* - * we deliberately ignore the end of the histogram, - * the most white pixels - */ + /* Calculate total pixels */ + total_pixels =3D 0; + for (i =3D 0; i < HIST_ENTRIES; i++) + total_pixels +=3D hist_entry[i]; + + /* Handle empty histogram case */ + if (total_pixels =3D=3D 0) { + *hist_count =3D 0; + ctrls->channel_avg[ctrls->hist_id] =3D 256; /* Default middle value */ + ctrls->total_pixels[ctrls->hist_id] =3D 0; + *min =3D 1; + *max =3D HIST_ENTRIES - 1; + dev_dbg(isc->dev, + "isc wb: no pixels in histogram for channel %u\n", + ctrls->hist_id); + return; + } + + /* Outlier rejection: skip darkest/brightest 2% of histogram */ + dark_threshold =3D total_pixels / ISC_AWB_OUTLIER_DIV; + bright_threshold =3D total_pixels / ISC_AWB_OUTLIER_DIV; + cumulative =3D 0; + + /* Find effective minimum (skip dark noise) */ + *min =3D 1; for (i =3D 1; i < HIST_ENTRIES; i++) { - if (*hist_entry && !*min) + cumulative +=3D hist_entry[i]; + if (cumulative > dark_threshold) { *min =3D i; - if (*hist_entry) + break; + } + } + + /* Find effective maximum (skip bright saturation) */ + cumulative =3D 0; + *max =3D HIST_ENTRIES - 1; + for (i =3D HIST_ENTRIES - 1; i > *min; i--) { + cumulative +=3D hist_entry[i]; + if (cumulative > bright_threshold) { *max =3D i; - *hist_count +=3D i * (*hist_entry++); + break; + } } =20 + /* Ensure reasonable range */ + if (*max <=3D *min) { + *min =3D HIST_ENTRIES / 4; + *max =3D (HIST_ENTRIES * 3) / 4; + } + + /* Calculate both pixel count and weighted average for useful range */ + *hist_count =3D 0; + weighted_sum =3D 0; + + for (i =3D *min; i <=3D *max; i++) { + pixel_count =3D hist_entry[i]; + *hist_count +=3D pixel_count; + weighted_sum +=3D (u64)i * pixel_count; + } + + /* Store total useful pixels for this channel */ + ctrls->total_pixels[ctrls->hist_id] =3D *hist_count; + + /* Calculate channel average */ + if (*hist_count > 0) + ctrls->channel_avg[ctrls->hist_id] =3D + div64_u64(weighted_sum, *hist_count); + else + /* Default middle value */ + ctrls->channel_avg[ctrls->hist_id] =3D 256; + if (!*min) *min =3D 1; =20 - dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u", - ctrls->hist_id, *hist_count); + dev_dbg(isc->dev, + "isc wb: hist_id %u, avg %u, count %u, range [%u,%u], total %u\n", + ctrls->hist_id, ctrls->channel_avg[ctrls->hist_id], + *hist_count, *min, *max, total_pixels); } =20 static void isc_wb_update(struct isc_ctrls *ctrls) { struct isc_device *isc =3D container_of(ctrls, struct isc_device, ctrls); - u32 *hist_count =3D &ctrls->hist_count[0]; u32 c, offset[4]; u64 avg =3D 0; - /* We compute two gains, stretch gain and grey world gain */ - u32 s_gain[4], gw_gain[4]; + u32 gain, gw_gain, s_gain; + u32 min_pixels; + u32 frame_pixels; =20 /* * According to Grey World, we need to set gains for R/B to normalize * them towards the green channel. - * Thus we want to keep Green as fixed and adjust only Red/Blue - * Compute the average of the both green channels first + * Thus we want to keep Green as fixed and adjust only Red/Blue. + * Compute the average of the both green channels first. */ - avg =3D (u64)hist_count[ISC_HIS_CFG_MODE_GR] + - (u64)hist_count[ISC_HIS_CFG_MODE_GB]; - avg >>=3D 1; + avg =3D (ctrls->channel_avg[ISC_HIS_CFG_MODE_GR] + + ctrls->channel_avg[ISC_HIS_CFG_MODE_GB]) >> 1; =20 dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg); =20 @@ -1338,7 +1408,23 @@ static void isc_wb_update(struct isc_ctrls *ctrls) if (!avg) return; =20 + /* + * Require a minimum pixel count for both black-level offset and + * grey-world gain: 1/64 of the frame area, which equals ~6.25% of + * one Bayer channel's expected pixel count. This scales with sensor + * resolution and prevents noise-dominated histograms (from very small + * crops or a nearly-empty frame) from producing wild corrections. + * A floor of 64 ensures the guard is non-zero for tiny crops. + */ + frame_pixels =3D isc->fmt.fmt.pix.width * isc->fmt.fmt.pix.height; + min_pixels =3D frame_pixels ? max(frame_pixels >> 6, 64u) : 64u; + for (c =3D ISC_HIS_CFG_MODE_GR; c <=3D ISC_HIS_CFG_MODE_B; c++) { + u32 hist_min =3D ctrls->hist_minmax[c][HIST_MIN_INDEX]; + u32 hist_max =3D ctrls->hist_minmax[c][HIST_MAX_INDEX]; + u32 channel_avg =3D ctrls->channel_avg[c]; + u32 total_pixels =3D ctrls->total_pixels[c]; + /* * the color offset is the minimum value of the histogram. * we stretch this color to the full range by substracting @@ -1364,40 +1450,33 @@ static void isc_wb_update(struct isc_ctrls *ctrls) ctrls->offset[c] =3D -ctrls->offset[c]; =20 /* - * the stretch gain is the total number of histogram bins - * divided by the actual range of color component (Max - Min) - * If we compute gain like this, the actual color component - * will be stretched to the full histogram. - * We need to shift 9 bits for precision, we have 9 bits for - * decimals + * Stretch gain: scale the histogram range [hist_min, hist_max] + * to the full 512-bin span. Result is in Q9 fixed-point + * (1.0 =3D 512). */ - s_gain[c] =3D (HIST_ENTRIES << 9) / - (ctrls->hist_minmax[c][HIST_MAX_INDEX] - - ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); + s_gain =3D (HIST_ENTRIES << 9) / (hist_max - hist_min + 1); =20 /* - * Now we have to compute the gain w.r.t. the average. - * Add/lose gain to the component towards the average. - * If it happens that the component is zero, use the - * fixed point value : 1.0 gain. + * Grey-world gain: scale each channel towards the green + * average. Require a minimum pixel count so noise-dominated + * channels do not produce wild corrections. */ - if (hist_count[c]) - gw_gain[c] =3D div_u64(avg << 9, hist_count[c]); + if (channel_avg > 0 && total_pixels >=3D min_pixels) + gw_gain =3D div64_u64((avg << 9), channel_avg); else - gw_gain[c] =3D 1 << 9; + gw_gain =3D 1 << 9; =20 - dev_dbg(isc->dev, - "isc wb: component %d, s_gain %u, gw_gain %u\n", - c, s_gain[c], gw_gain[c]); - /* multiply both gains and adjust for decimals */ - ctrls->gain[c] =3D s_gain[c] * gw_gain[c]; - ctrls->gain[c] >>=3D 9; + /* Cap grey-world correction at 4x to avoid over-amplification. */ + gw_gain =3D min_t(u32, gw_gain, ISC_AWB_GW_GAIN_MAX); =20 - /* make sure we are not out of range */ - ctrls->gain[c] =3D clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); + /* Combine stretch and grey-world gains; result stays in Q9. */ + gain =3D (s_gain * gw_gain) >> 9; =20 - dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n", - c, ctrls->gain[c]); + ctrls->gain[c] =3D clamp_val(gain, 0, GENMASK(12, 0)); + + dev_dbg(isc->dev, + "isc wb: c=3D%u black=3D%u avg=3D%u s_gain=3D%u gw_gain=3D%u gain=3D%u", + c, hist_min, channel_avg, s_gain, gw_gain, gain); } } =20 diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index 2c8bcaaa26ea..fccd7ff4846b 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -158,6 +158,8 @@ struct isc_ctrls { #define HIST_MIN_INDEX 0 #define HIST_MAX_INDEX 1 u32 hist_minmax[HIST_BAYER][2]; + u32 channel_avg[HIST_BAYER]; + u32 total_pixels[HIST_BAYER]; }; =20 #define ISC_PIPE_LINE_NODE_NUM 15 --=20 2.34.1 From nobody Mon May 25 05:14:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7EF63F8EB9; Mon, 18 May 2026 11:30:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="56879107" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 04:30:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 18 May 2026 04:30:50 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 18 May 2026 04:30:47 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:49 +0530 Subject: [PATCH v4 11/12] media: microchip-isc: smooth AWB gains with EMA filter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-11-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus X-Mailer: b4 0.14.3 Apply exponential moving average (alpha=3D0.25) to reduce per-frame flicker from sensor noise. Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 19 +++++++++++++++= +--- drivers/media/platform/microchip/microchip-isc.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 67c2999ae5b5..82eff6012527 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -93,6 +93,7 @@ static inline void isc_reset_awb_ctrls(struct isc_device = *isc) for (c =3D ISC_HIS_CFG_MODE_GR; c <=3D ISC_HIS_CFG_MODE_B; c++) { /* gains have a fixed point at 9 decimals */ isc->ctrls.gain[c] =3D 1 << 9; + isc->ctrls.gain_smooth[c] =3D 1 << 9; /* offsets are in 2's complements */ isc->ctrls.offset[c] =3D 0; } @@ -1472,11 +1473,23 @@ static void isc_wb_update(struct isc_ctrls *ctrls) /* Combine stretch and grey-world gains; result stays in Q9. */ gain =3D (s_gain * gw_gain) >> 9; =20 - ctrls->gain[c] =3D clamp_val(gain, 0, GENMASK(12, 0)); + /* + * Smooth gain updates with an exponential weighted average + * to suppress per-frame flicker: + * smooth[n] =3D (3 * smooth[n-1] + gain) / 4 + * Clamp to the hardware register width to prevent unbounded + * accumulation under degenerate (near-empty histogram) inputs. + */ + ctrls->gain_smooth[c] =3D (3 * ctrls->gain_smooth[c] + gain) / 4; + ctrls->gain_smooth[c] =3D min_t(u32, ctrls->gain_smooth[c], + GENMASK(12, 0)); + + ctrls->gain[c] =3D ctrls->gain_smooth[c]; =20 dev_dbg(isc->dev, - "isc wb: c=3D%u black=3D%u avg=3D%u s_gain=3D%u gw_gain=3D%u gain=3D%u", - c, hist_min, channel_avg, s_gain, gw_gain, gain); + "isc wb: c=3D%u black=3D%u avg=3D%u s_gain=3D%u gw_gain=3D%u gain=3D%u = smooth=3D%u\n", + c, hist_min, channel_avg, s_gain, gw_gain, gain, + ctrls->gain_smooth[c]); } } =20 diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index fccd7ff4846b..4503fcbfdce8 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -149,6 +149,7 @@ struct isc_ctrls { =20 /* one for each component : GR, R, GB, B */ u32 gain[HIST_BAYER]; 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Mon, 18 May 2026 04:30:51 -0700 From: Balakrishnan Sambath Date: Mon, 18 May 2026 16:59:50 +0530 Subject: [PATCH v4 12/12] media: microchip-isc: scale DPC black level to sensor bit depth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260518-balki-isc-series1-v4-v4-12-97f189185b7e@microchip.com> References: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> In-Reply-To: <20260518-balki-isc-series1-v4-v4-0-97f189185b7e@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: , , "Laurent Pinchart" , Kieran Bingham , Balakrishnan Sambath , Sakari Ailus X-Mailer: b4 0.14.3 Scale the nominal 10-bit black level (64 counts) to match 8/10/12-bit sensor bus width. Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-sama7g5-isc.c | 19 +++++++++++++++= +++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 6705011edc2a..d978466aa489 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -26,6 +26,7 @@ * HIS: Histogram module performs statistic counters on the frames */ =20 +#include #include #include #include @@ -289,9 +290,25 @@ static void isc_sama7g5_config_dpc(struct isc_device *= isc) { u32 bay_cfg =3D isc->config.sd_format->cfa_baycfg; struct regmap *regmap =3D isc->regmap; + u32 bps, bloff; + + /* + * Scale the nominal 10-bit black level offset (64 counts) to the + * actual sensor bus width. + * ISC_PFE_CFG0_BPS encodes (12 - bit_depth) / 2 in bits[30:28]: + * BPS_EIGHT =3D 4 -> 8-bit -> bloff =3D 64 >> 2 =3D 16 + * BPS_TEN =3D 2 -> 10-bit -> bloff =3D 64 + * BPS_TWELVE =3D 0 -> 12-bit -> bloff =3D min(64 << 2, 255) =3D 255 + * The BLOFF hardware field is 8-bit so values are clamped to 255. + */ + bps =3D FIELD_GET(ISC_PFE_CFG0_BPS_MASK, isc->config.sd_format->pfe_cfg0_= bps); + if (bps >=3D 2) + bloff =3D 64u >> (bps - 2); + else + bloff =3D min(64u << (2 - bps), 255u); =20 regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, - (64 << ISC_DPC_CFG_BLOFF_SHIFT)); + (bloff << ISC_DPC_CFG_BLOFF_SHIFT)); regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); } --=20 2.34.1