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Sun, 17 May 2026 08:40:22 -0700 (PDT) Received: from localhost.localdomain ([82.215.118.79]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45d9e768acesm32328981f8f.7.2026.05.17.08.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 08:40:21 -0700 (PDT) From: Stepan Ionichev To: andy@kernel.org Cc: mika.westerberg@linux.intel.com, linusw@kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, sozdayvek@gmail.com Subject: [PATCH v2] pinctrl: intel: move PWM base computation past feature check Date: Sun, 17 May 2026 20:40:02 +0500 Message-Id: <20260517154002.1994-1-sozdayvek@gmail.com> X-Mailer: git-send-email 2.33.0.windows.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" intel_pinctrl_probe_pwm() computes the PWM register base unconditionally at the start of the function: void __iomem *base =3D community->regs + capability_offset + 4; if (!(community->features & PINCTRL_FEATURE_PWM)) return 0; if (!IS_REACHABLE(CONFIG_PWM_LPSS)) return 0; chip =3D devm_pwm_lpss_probe(pctrl->dev, base, &info); For communities without CAPLIST_ID_PWM, capability_offset is the uninitialised value left in the per-community array on the stack; forming base =3D regs + capability_offset + 4 from that value reads indeterminate state even though the result is never dereferenced (the feature check returns first). Split the declaration from the assignment so the value is only computed after PINCTRL_FEATURE_PWM and the CONFIG_PWM_LPSS reachability check have passed. base is then the same single use that devm_pwm_lpss_probe() already consumes, so no other call sites are affected. Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/linux-gpio/aglu5jy5SbW9Wjwj@ashevche-desk.loc= al/ Signed-off-by: Stepan Ionichev --- Changes since v1: - Drop the array zero-initialisation approach. - Move the base assignment past the PINCTRL_FEATURE_PWM and CONFIG_PWM_LPSS checks instead, per Andy's review. - Drop the Fixes: tag (per Andy: this is a cleanup, not a fix). v1: https://lore.kernel.org/linux-gpio/20260515150049.33761-1-sozdayvek@gma= il.com/ drivers/pinctrl/intel/pinctrl-intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/= pinctrl-intel.c index 97bf5ec78..2e2526e01 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1556,13 +1556,13 @@ static int intel_pinctrl_probe_pwm(struct intel_pin= ctrl *pctrl, struct intel_community *community, unsigned short capability_offset) { - void __iomem *base =3D community->regs + capability_offset + 4; static const struct pwm_lpss_boardinfo info =3D { .clk_rate =3D 19200000, .npwm =3D 1, .base_unit_bits =3D 22, }; struct pwm_chip *chip; + void __iomem *base; =20 if (!(community->features & PINCTRL_FEATURE_PWM)) return 0; @@ -1570,6 +1570,7 @@ static int intel_pinctrl_probe_pwm(struct intel_pinct= rl *pctrl, if (!IS_REACHABLE(CONFIG_PWM_LPSS)) return 0; =20 + base =3D community->regs + capability_offset + 4; chip =3D devm_pwm_lpss_probe(pctrl->dev, base, &info); return PTR_ERR_OR_ZERO(chip); } --=20 2.43.0