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Sat, 16 May 2026 18:49:17 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , Christian Bruel , Vincent Guittot , Senchuan Zhang , Alex Elder , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v2 1/5] PCI: spacemit-k1: Add device data support Date: Sun, 17 May 2026 09:48:36 +0800 Message-ID: <20260517014841.254085-2-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517014841.254085-1-inochiama@gmail.com> References: <20260517014841.254085-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reuse the K1 PCIe driver logic for K3 PCIe controller, add device data to handle the K1 specific logic and make room for the incoming logic for K3. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index be20a520255b..1b519d49dcc0 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -57,6 +57,12 @@ struct k1_pcie { u32 pmu_off; }; =20 +struct k1_pcie_device_data { + const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); +}; + #define to_k1_pcie(dw_pcie) \ platform_get_drvdata(to_platform_device((dw_pcie)->dev)) =20 @@ -278,10 +284,15 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) =20 static int k1_pcie_probe(struct platform_device *pdev) { + const struct k1_pcie_device_data *data; struct device *dev =3D &pdev->dev; struct k1_pcie *k1; int ret; =20 + data =3D device_get_match_data(dev); + if (!data) + return -ENODEV; + k1 =3D devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); if (!k1) return -ENOMEM; @@ -299,11 +310,11 @@ static int k1_pcie_probe(struct platform_device *pdev) "failed to map \"link\" registers\n"); =20 k1->pci.dev =3D dev; - k1->pci.ops =3D &k1_pcie_ops; + k1->pci.ops =3D data->ops; k1->pci.pp.num_vectors =3D MAX_MSI_IRQS; dw_pcie_cap_set(&k1->pci, REQ_RES); =20 - k1->pci.pp.ops =3D &k1_pcie_host_ops; + k1->pci.pp.ops =3D data->host_ops; =20 /* Hold the PHY in reset until we start the link */ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, @@ -320,7 +331,7 @@ static int k1_pcie_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, k1); =20 - ret =3D k1_pcie_parse_port(k1); + ret =3D data->parse_port(k1); if (ret) return dev_err_probe(dev, ret, "failed to parse root port\n"); =20 @@ -338,8 +349,14 @@ static void k1_pcie_remove(struct platform_device *pde= v) dw_pcie_host_deinit(&k1->pci.pp); } =20 +static const struct k1_pcie_device_data k1_pcie_device_data =3D { + .host_ops =3D &k1_pcie_host_ops, + .ops =3D &k1_pcie_ops, + .parse_port =3D k1_pcie_parse_port, +}; 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Sat, 16 May 2026 18:49:19 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , Christian Bruel , Vincent Guittot , Senchuan Zhang , Alex Elder , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v2 2/5] PCI: spacemit-k1: Add multiple PHY handles support Date: Sun, 17 May 2026 09:48:37 +0800 Message-ID: <20260517014841.254085-3-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517014841.254085-1-inochiama@gmail.com> References: <20260517014841.254085-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCIe controller on Spacemit K3 may use multiple PHYs at the same time. The feature is not support by the current driver. So extend the PHY definition to support multiple PHY handles. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index 1b519d49dcc0..7f6f1df31cd8 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -51,7 +51,8 @@ =20 struct k1_pcie { struct dw_pcie pci; - struct phy *phy; + struct phy **phy; + int phy_count; void __iomem *link; struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ u32 pmu_off; @@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) */ regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); =20 - ret =3D phy_init(k1->phy); + ret =3D phy_init(k1->phy[0]); if (ret) { k1_pcie_disable_resources(k1); =20 @@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct k1_pcie *k1 =3D to_k1_pcie(pci); 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Sat, 16 May 2026 18:49:22 -0700 (PDT) Received: from localhost ([2001:19f0:8001:1b2d:5400:5ff:fefa:a95d]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19f7cc8bsm10511314b3a.55.2026.05.16.18.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2026 18:49:22 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , Christian Bruel , Vincent Guittot , Senchuan Zhang , Alex Elder , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v2 3/5] dt-bindings: PCI: snps,dw-pcie: Add msi-parent for MSI handle check Date: Sun, 17 May 2026 09:48:38 +0800 Message-ID: <20260517014841.254085-4-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517014841.254085-1-inochiama@gmail.com> References: <20260517014841.254085-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The IMSIC device on RISC-V based system does not require ID remapping for MSI. So this device only needs "msi-parent" property for IMSIC-based SoC, and the "msi-map" is not a necessary property. Add new condition for MSI handling on IMSIC based SoC. Signed-off-by: Inochi Amaoto Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Docu= mentation/devicetree/bindings/pci/snps,dw-pcie.yaml index b3216141881c..91bbbc8924f6 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -27,8 +27,11 @@ allOf: - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - if: not: - required: - - msi-map + anyOf: + - required: + - msi-map + - required: + - msi-parent then: properties: interrupt-names: --=20 2.54.0 From nobody Wed Jun 10 08:03:56 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDBD0298CA5 for ; Sun, 17 May 2026 01:49:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, with some extra link and reset state control. Signed-off-by: Inochi Amaoto --- .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-= host.yaml diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.ya= ml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml new file mode 100644 index 000000000000..46147a37a9ce --- /dev/null +++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K3 PCI Express Host Controller + +maintainers: + - Inochi Amaoto + +description: + The SpacemiT K3 SoC PCIe host controller is based on the Synopsys + DesignWare PCIe IP. The controller uses the external MSI interrupt + controller. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: spacemit,k3-pcie + + reg: + items: + - description: DesignWare PCIe registers + - description: Data Bus Interface (DBI) shadow registers + - description: ATU address space + - description: PCIe configuration space + - description: Link control registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: config + - const: link + + clocks: + items: + - description: DWC PCIe Data Bus Interface (DBI) clock + - description: DWC PCIe application AXI-bus master interface clock + - description: DWC PCIe application AXI-bus slave interface clock + + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + + resets: + items: + - description: DWC PCIe Data Bus Interface (DBI) reset + - description: DWC PCIe application AXI-bus master interface reset + - description: DWC PCIe application AXI-bus slave interface reset + + reset-names: + items: + - const: dbi + - const: mstr + - const: slv + + msi-parent: true + + phys: + description: + PHY phandle from the Combo PHY, the lane number does not depends + on this, since the number of lanes provided by Combo PHY can be + 1 or 2. + minItems: 1 + maxItems: 6 + + phy-names: + minItems: 1 + maxItems: 6 + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle that refers to the APMU system controller, whose regmap is + used in managing resets and link state, along with and offset of its + reset control register. + items: + - items: + - description: phandle to APMU system controller + - description: register offset + +required: + - clocks + - clock-names + - resets + - reset-names + - msi-parent + - spacemit,apmu + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@80000000 { + compatible =3D "spacemit,k3-pcie"; + reg =3D <0x0 0x80000000 0x0 0x00001000>, + <0x0 0x80100000 0x0 0x00001000>, + <0x0 0x80300000 0x0 0x00003f20>, + <0x11 0x00000000 0x0 0x00010000>, + <0x0 0x82900000 0x0 0x00001000>; + reg-names =3D "dbi", "dbi2", "atu", "config", "link"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + clocks =3D <&syscon_apmu 89>, + <&syscon_apmu 56>, + <&syscon_apmu 57>; + clock-names =3D "dbi", "mstr", "slv"; + msi-parent =3D <&simsic>; + ranges =3D <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100= 000>, + <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef000= 0>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x0000000= 0>; + resets =3D <&syscon_apmu 76>, + <&syscon_apmu 78>, + <&syscon_apmu 77>; + reset-names =3D "dbi", "mstr", "slv"; + linux,pci-domain =3D <0>; + spacemit,apmu =3D <&syscon_apmu 0x1f0>; + }; + }; + --=20 2.54.0 From nobody Wed Jun 10 08:03:56 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9AF2FFDD6 for ; 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Sat, 16 May 2026 18:49:27 -0700 (PDT) Received: from localhost ([2001:19f0:8001:1b2d:5400:5ff:fefa:a95d]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-369512424c2sm6853019a91.4.2026.05.16.18.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2026 18:49:27 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , Christian Bruel , Vincent Guittot , Senchuan Zhang , Alex Elder , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v2 5/5] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support Date: Sun, 17 May 2026 09:48:40 +0800 Message-ID: <20260517014841.254085-6-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517014841.254085-1-inochiama@gmail.com> References: <20260517014841.254085-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCIe controller on Spacemit K3 is almost a standard Synopsys DesignWare PCIe IP with extra link and reset control. Unlike the PCIe controller on K1, this controller supports external MSI interrupt controller and can use multiple PHYs at the same time. Add driver to support PCIe controller on Spacemit K3 PCIe. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/Kconfig | 4 +- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 169 ++++++++++++++++++ 2 files changed, 171 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index f2fde13107f2..fae971ecd876 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -439,7 +439,7 @@ config PCIE_SOPHGO_DW Sophgo SoCs. =20 config PCIE_SPACEMIT_K1 - tristate "SpacemiT K1 PCIe controller (host mode)" + tristate "SpacemiT K1/K3 PCIe controller (host mode)" depends on ARCH_SPACEMIT || COMPILE_TEST depends on HAS_IOMEM select PCIE_DW_HOST @@ -447,7 +447,7 @@ config PCIE_SPACEMIT_K1 default ARCH_SPACEMIT help Enables support for the DesignWare based PCIe controller in - the SpacemiT K1 SoC operating in host mode. Three controllers + the SpacemiT K1/K3 SoC operating in host mode. Three controllers are available on the K1 SoC; the first of these shares a PHY with a USB 3.0 host controller (one or the other can be used). =20 diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index 7f6f1df31cd8..7854d26220a9 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -23,6 +23,7 @@ =20 #define PCI_VENDOR_ID_SPACEMIT 0x201f #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 +#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 =20 /* Offsets and field definitions for link management registers */ #define K1_PHY_AHB_IRQ_EN 0x0000 @@ -32,8 +33,20 @@ #define SMLH_LINK_UP BIT(1) #define RDLH_LINK_UP BIT(12) =20 +#define INTR_STATUS 0x0010 + #define INTR_ENABLE 0x0014 #define MSI_CTRL_INT BIT(11) +#define RDLH_LINK_UP_INT BIT(20) + +#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 + +#define K3_ADDR_INTR_STATUS1 0x0018 + +#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) +#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf + +#define K3_MAX_PHY_NUMBER 6 =20 /* Some controls require APMU regmap access */ #define SYSCON_APMU "spacemit,apmu" @@ -48,6 +61,9 @@ =20 #define PCIE_CONTROL_LOGIC 0x0004 #define PCIE_SOFT_RESET BIT(0) +#define PCIE_PERSTN_OE BIT(24) +#define PCIE_PERSTN_OUT BIT(25) +#define PCIE_IGNORE_PERSTN BIT(31) =20 struct k1_pcie { struct dw_pcie pci; @@ -262,6 +278,152 @@ static const struct dw_pcie_ops k1_pcie_ops =3D { .stop_link =3D k1_pcie_stop_link, }; =20 +static int k3_pcie_enable_phy(struct k1_pcie *pcie) +{ + int i, ret; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret) + goto err_phy; + } + + return 0; + +err_phy: + while (--i >=3D 0) + phy_exit(pcie->phy[i]); + + return ret; +} + +static int k3_pcie_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 =3D to_k1_pcie(pci); + u32 reset_ctrl =3D k1->pmu_off + PCIE_CLK_RESET_CONTROL; + u32 val; + int ret; + + regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); + + k1_pcie_toggle_soft_reset(k1); + + ret =3D k1_pcie_enable_resources(k1); + if (ret) + return ret; + + regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); + regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); + + ret =3D k3_pcie_enable_phy(k1); + if (ret) { + k1_pcie_disable_resources(k1); + return ret; + } + + /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, + PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); + usleep_range(1000, 2000); + regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_= OUT); + + msleep(PCIE_T_PVPERL_MS); + + /* + * Put the controller in root complex mode, and indicate that + * Vaux (3.3v) is present. + */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, + PCIE_PERSTN_OUT | PCIE_PERSTN_OE); + + val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); + val =3D u32_replace_bits(val, GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE, + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); + + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K3); + dw_pcie_dbi_ro_wr_dis(pci); + + /* Finally, as a workaround, disable ASPM L1 */ + k1_pcie_disable_aspm_l1(k1); + + return 0; +} + +static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val =3D dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); + val |=3D u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, + K3_CACHE_MSTR_AWCACHE_MODE); + dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static const struct dw_pcie_host_ops k3_pcie_host_ops =3D { + .init =3D k3_pcie_init, + .deinit =3D k1_pcie_deinit, + .msi_init =3D k3_pcie_msi_host_init, +}; + +static const struct dw_pcie_ops k3_pcie_ops =3D { + .link_up =3D k1_pcie_link_up, + .start_link =3D k1_pcie_start_link, + .stop_link =3D k1_pcie_stop_link, +}; + +static void k3_pcie_clear_irq_status(struct k1_pcie *k1, + u32 *status0, u32 *status1, u32 *status2) +{ + *status0 =3D readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); + *status1 =3D readl_relaxed(k1->link + INTR_STATUS); + *status2 =3D readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); + + writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); + writel_relaxed(*status1, k1->link + INTR_STATUS); + writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); +} + +static int k3_pcie_parse_port(struct k1_pcie *k1) +{ + struct device *dev =3D k1->pci.dev; + u32 status0, status1, status2; + int i; + + k1->phy =3D devm_kmalloc_array(dev, K3_MAX_PHY_NUMBER, sizeof(*k1->phy), + GFP_KERNEL); + if (!k1->phy) + return -ENOMEM; + + for (i =3D 0; i < K3_MAX_PHY_NUMBER; i++) { + k1->phy[i] =3D devm_of_phy_get_by_index(dev, dev->of_node, i); + if (IS_ERR(k1->phy[i])) { + if (PTR_ERR(k1->phy[i]) =3D=3D -ENODEV) + break; + + return PTR_ERR(k1->phy[i]); + } + } + + k1->phy_count =3D i; + if (k1->phy_count =3D=3D 0) + return -EINVAL; + + k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); + + return 0; +} + static int k1_pcie_parse_port(struct k1_pcie *k1) { struct device *dev =3D k1->pci.dev; @@ -363,8 +525,15 @@ static const struct k1_pcie_device_data k1_pcie_device= _data =3D { .parse_port =3D k1_pcie_parse_port, }; =20 +static const struct k1_pcie_device_data k3_pcie_device_data =3D { + .host_ops =3D &k3_pcie_host_ops, + .ops =3D &k3_pcie_ops, + .parse_port =3D k3_pcie_parse_port, +}; + static const struct of_device_id k1_pcie_of_match_table[] =3D { { .compatible =3D "spacemit,k1-pcie", .data =3D &k1_pcie_device_data}, + { .compatible =3D "spacemit,k3-pcie", .data =3D &k3_pcie_device_data}, { } }; =20 --=20 2.54.0