From nobody Mon May 25 08:12:01 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A25743A6EED; Sat, 16 May 2026 23:39:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974799; cv=none; b=WBGxvgzrrFRCnQKNFHzmvDe3o+oc+CBB5JnY94bdg5eLwhMJgsb6oTpggwG4JTklcVTG1NUjg7ERQVAD3EtZTmiBaoNS+aTqA8EnDaBaZwnDfWg4GuJFM6RernK+HxKbriS7gMvlNeWoDiydqXX1a+tFOxz+5bo3KmdRP/r7b7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974799; c=relaxed/simple; bh=Ze4Nv8y680E6FSf/un9hYJUthpJ2COzdxd+LB34Yb2I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VIxeOy/gTaBi/diB4rPXxfIO9d9ZMscTXS4MYvaKkKZx97tdIC1+5ARXLg5M1P1nQ/zktPYMty5KEq/J9/pj/cR3545KloLnby/Cfpy9tmjaNS8WUL3G/VSA9DuyBmBSouw0Xdw/wEikywy4fdYZ9+W7f4OEmGcUIO3n97nrGCk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=wPXkhVXA; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="wPXkhVXA" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7BAB33FB12A; Sun, 17 May 2026 01:39:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778974794; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=X5WYmjC+W1XLRGqsI2xwQZ9HsjRo/iUHSgzYnXKRgcw=; b=wPXkhVXAahxm9HQdVkD87Smm79dyYjhf6Jw7WF/EqAPw8Zfj1JxRQO7W6rfRQ6tfE4/jnO mKovkOckLSCLdZC2ClU04hk4UwwhjjVesav/eGYmFU6gRf/zvmMH5ht1rFqx7IiBqdMoQr 32t/4+z+k1DeEZbZXYOrdmBaxdmLc6cwcSj/JBgdSuO/JTcGrWxx/CIoCRYS8af9sAB4JB qdU7PYVxLMzR84znXVcRT9yzIz+HNWLJO0ElGc5DQ8fdf5Zb9qegg9jD+YpEvnTNtQr2Ic 0qzQyrNvXf5I6zKgYIwIDubgOhytk1PYgnHPjscyt5jy6QvlOdVH6CYjkv37bQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle , Conor Dooley Subject: [PATCH v5 1/4] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Date: Sat, 16 May 2026 23:39:40 +0000 Message-Id: <20260516233943.49502-2-cjd@cjdns.fr> In-Reply-To: <20260516233943.49502-1-cjd@cjdns.fr> References: <20260516233943.49502-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This hardware is found in the EN751221 SoC family as well as the EN751627. The former uses a percpu IRQ for all timers while the latter uses an individual IRQ number per timer. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/timer/econet,en751221-timer.yaml | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.= yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml index c1e7c2b6afde..ac25785ecfdf 100644 --- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -12,24 +12,23 @@ maintainers: description: The EcoNet High Precision Timer (HPT) is a timer peripheral found in var= ious EcoNet SoCs, including the EN751221 and EN751627 families. It provides p= er-VPE - count/compare registers and a per-CPU control register, with a single in= terrupt - line using a percpu-devid interrupt mechanism. + count/compare registers and a per-CPU control register. On EN751221 it u= ses a + single interrupt line using a percpu-devid interrupt mechanism, and on + EN751627 it uses an interrupt per VPE. =20 properties: compatible: - oneOf: - - const: econet,en751221-timer - - items: - - const: econet,en751627-timer - - const: econet,en751221-timer + enum: + - econet,en751221-timer + - econet,en751627-timer =20 reg: minItems: 1 maxItems: 2 =20 interrupts: - maxItems: 1 - description: A percpu-devid timer interrupt shared across CPUs. + minItems: 1 + maxItems: 4 =20 clocks: maxItems: 1 @@ -52,21 +51,31 @@ allOf: items: - description: VPE timers 0 and 1 - description: VPE timers 2 and 3 + interrupts: + description: An interrupt for each timer (one per VPE) + minItems: 4 else: properties: reg: items: - description: VPE timers 0 and 1 + interrupts: + description: A percpu-devid timer interrupt shared across timers + maxItems: 1 =20 additionalProperties: false =20 examples: - | + #include timer@1fbf0400 { - compatible =3D "econet,en751627-timer", "econet,en751221-timer"; + compatible =3D "econet,en751627-timer"; reg =3D <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; interrupt-parent =3D <&intc>; - interrupts =3D <30>; + interrupts =3D , + , + , + ; clocks =3D <&hpt_clock>; }; - | --=20 2.39.5 From nobody Mon May 25 08:12:01 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC623A874D; Sat, 16 May 2026 23:40:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974802; cv=none; b=qrgSnovQUUkHLfuBWRk4X2z/hlEbtFuKHLwPcA0UjjdKHk9K3YvXdPwBxtsPNX1QSBDKNEX1Qs54LKWBmaYW0n0iew4eKC+oBjKVFb5PEJsnQf6ZVh7eVXD691iA5ZIieRo/0BLNdLNufmSgsY8B5h1KwbEZmqz5AKp+NSEXXLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974802; c=relaxed/simple; bh=7wxpOJISV76f+OA+eUJDFOYKOmSTMyJ0sT0aUgy6Jx0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZePUXrZ4qXzIJb2jrkZwLNluBY8agcjHDEG2eohvOZaPoy+ysBAzOolImy0Koj1RMONnXWZzcLrh4CIDbBMeGuz4zhbw3IJMLJ1M49lVI5/52z6Rbb2tB0UEZLldpd+lASJfQZ+i9ZfluzjVvqyH5juScJDXClK7+/WNyRdgLLk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Jq4zVsD8; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Jq4zVsD8" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9FA113FAC40; Sun, 17 May 2026 01:39:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778974797; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Q0h8RiPN75sqVf0my0iCAciaGj/g/mvtHx8ng9fbWfM=; b=Jq4zVsD8e0BoFIIYFf8lYAjLcgbG0puDieh05PSN6imsbiq4NaAyVcYPlcBDS445F/tzeT 1U5xgcEe4uygS9H+hPYIjGUABEMBhusnsEzoV588TPqGa7wtHvE3Ujgx5i0SyrWhHCMknS BNEnE01tOl5js/sQ7V1oAN/2zU3lENneNPhTgZnPP4TdlPxVsWPF6bnPnKvtDF9r07OZvJ D5QMmtrUMnnwWq7WLA2ByF8WQ5k7fNA2wJcM9EEASpudb7rD2DyvqHUT2u4KbukrN61SYR +1tQLQnMRrUAv4rA7vchhW2isMKVTck3KAe2ED0Pu8C6h3i425oQ+XwhjDWAvg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v5 2/4] clocksource/timer-econet-en751221: Init teardown on error if possible Date: Sat, 16 May 2026 23:39:41 +0000 Message-Id: <20260516233943.49502-3-cjd@cjdns.fr> In-Reply-To: <20260516233943.49502-1-cjd@cjdns.fr> References: <20260516233943.49502-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" As a clocksource, much of the initialization process is irreversible and the impact of a failure to initialize is a failure to boot. That said, good practice is to attempt a clean exit if probing fails, and supporting this pattern will reduce the likelihood that future contributions introduce a bug by trying to teardown after it is no longer possible to do so. Convert the init process into two clearly delineated phases, one which is reverted in case of error, and the other which can't be. Move all IRQ and address resource mapping before that point, and add teardown logic in case of error before the point of no return. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 82 ++++++++++++--------- 1 file changed, 48 insertions(+), 34 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 4008076b1a21..155471f68e6f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -24,6 +24,7 @@ =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; + int irq; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -126,22 +127,9 @@ static void __init cevt_dev_init(uint cpu) iowrite32(U32_MAX, reg_compare(cpu)); } =20 -static int __init cevt_init(struct device_node *np) +static void __init cevt_init(struct device_node *np) { - int i, irq, ret; - - irq =3D irq_of_parse_and_map(np, 0); - if (irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed", np); - return -EINVAL; - } - - ret =3D request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_p= cpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret); - goto err_unmap_irq; - } + int i; =20 for_each_possible_cpu(i) { struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, i); @@ -151,21 +139,12 @@ static int __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D irq; + cd->irq =3D econet_timer.irq; cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 cevt_dev_init(i); } - - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, - "clockevents/econet/timer:starting", - cevt_init_cpu, NULL); - return 0; - -err_unmap_irq: - irq_dispose_mapping(irq); - return ret; } =20 static int __init timer_init(struct device_node *np) @@ -186,22 +165,45 @@ static int __init timer_init(struct device_node *np) econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); - return -ENXIO; + ret =3D -ENXIO; + goto out_membase; } } =20 + econet_timer.irq =3D irq_of_parse_and_map(np, 0); + if (econet_timer.irq <=3D 0) { + pr_err("%pOFn: irq_of_parse_and_map failed\n", np); + ret =3D -EINVAL; + goto out_membase; + } + + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, + &econet_timer_pcpu); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, + econet_timer.irq, ret); + goto out_irq_mapping; + } + + cevt_init(np); + + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "clockevents/econet/timer:starting", + cevt_init_cpu, NULL); + if (ret < 0) { + pr_err("%pOFn: cpuhp setup failed (%d)\n", np, ret); + goto out_irq_free; + } + + /* Point of no return, do not attempt to tear down after this. */ + /* For clocksource purposes always read clock zero, whatever the CPU */ ret =3D clocksource_mmio_init(reg_count(0), np->name, econet_timer.freq_hz, 301, ECONET_BITS, clocksource_mmio_readl_up); - if (ret) { - pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret); - return ret; - } - - ret =3D cevt_init(np); - if (ret < 0) - return ret; + if (ret) + pr_err("%pOFn: clocksource_mmio_init failed: %d\n", np, ret); =20 sched_clock_register(sched_clock_read, ECONET_BITS, econet_timer.freq_hz); @@ -211,6 +213,18 @@ static int __init timer_init(struct device_node *np) (econet_timer.freq_hz / 1000) % 1000); =20 return 0; + +out_irq_free: + free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); +out_irq_mapping: + irq_dispose_mapping(econet_timer.irq); +out_membase: + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + if (econet_timer.membase[i]) + iounmap(econet_timer.membase[i]); + } + + return ret; } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); --=20 2.39.5 From nobody Mon May 25 08:12:01 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 068683A9615; Sat, 16 May 2026 23:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="im+d7sab" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7C8CE3FA5BD; Sun, 17 May 2026 01:39:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778974800; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=m+6v+hjQch8RJ+bE8KqFuX68S8nN6mY6vSXBtyBFUJQ=; b=im+d7sabMBnhQoS+rqoqCCwFWauBvt9EsOD+XZKmzDWMKrpA8zhrZoF3Dg0QzYtKjXn5gE w+Q9y42PZR54daYLOO8DH1oQvvEQXN6vrX43kQ+sLuXBGCuIgCURdW3GZ/M432PAEwAgzC H96hw7d2ClEX7bdxHiI4VxFod4rihCXgJEGdEV+crWworPjJLzkIjT541N326vrzQ137Cy buf4li9Qv2IUR2+IkQ/B+OhrL9FCGpYpsnbZLS2qZtmoO5rGMmyei8RWiQQ0qaCVoDae6k Ao56lKsizdovlIpRq8UMI1/CP400T5RYRttphvCZNJvQYm9R+5bBbMd/829DYQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v5 3/4] clocksource/timer-econet-en751221: Disable IRQ until cevt registered Date: Sat, 16 May 2026 23:39:42 +0000 Message-Id: <20260516233943.49502-4-cjd@cjdns.fr> In-Reply-To: <20260516233943.49502-1-cjd@cjdns.fr> References: <20260516233943.49502-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Eliminate a race condition where cevt_interrupt may trigger before clockevents_config_and_register has been called, and dev->event_handler is at that point NULL. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 155471f68e6f..ed750e39cc4f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -104,12 +104,11 @@ static int cevt_init_cpu(uint cpu) reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); iowrite32(reg, reg_ctl(cpu)); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); - - /* Do this last because it synchronously configures the timer */ clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + return 0; } =20 @@ -177,6 +176,8 @@ static int __init timer_init(struct device_node *np) goto out_membase; } =20 + irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, &econet_timer_pcpu); =20 --=20 2.39.5 From nobody Mon May 25 08:12:01 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6B323A9D90; Sat, 16 May 2026 23:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974807; cv=none; b=f5XnUcv1rxg0Xr6MMJXD7u0FymyvW0Ll2JpDh2cA9tvpZZs4eoDluokKtrWc0L5EamNr13HCbNPkeDdG2L63FBoXvR1IzmizkgOaSl2WbmgRDjFIuGe+WuoaSUMTFdWpZL+3lQLqvVHnaNMy5587j7A32w7TSdc7ENRyj7yClHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778974807; c=relaxed/simple; bh=yu4fJ8ulO9mDA5fJi1f5Oh17QSzsgloHDbdia6qHACE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BrsdjSeajVpV5Wh4Vc8r2xM6jwjqh52HeUgc8SUlvcWkogRFfJVXfUsjwfvyuuCzCc20qekkm7RE8rQWyJBM1D0K1McD2a7Ux4duFQMZw8l3hGixVReaYBYwcFlQWiBcPk95nNPbnxJIGWzdAqHb5+jAlD70LA6evBgAA1XjuiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=GuBhxufv; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="GuBhxufv" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 323D03F9160; Sun, 17 May 2026 01:40:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778974803; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=evFEwSByBmS71IrMaroencfJpe45Jcdgsf/YM1lBbTw=; b=GuBhxufvHyYvUzc5oDgTciZtLhUCUmzgZg43g7OvtTKMM8vAwiRvQ2JUD7SwPARbnNG5pX r68QnJG2PCK3VNefXvk74XYBbLj7ZquUNHDE3P2fbUf0LktdJc7sTrdfAGALPfkGWQKHeJ BNpAzFhNH6UoiElqnxkyv87GknbVY6OiD9qHH5/ExIQ3FtW//LWAoiN9rsFth78qPkM7jV 9wPEya5u0m0zqb1xev7dNe5pYc/hsMAtA7TukWDFxvX6elz40CWfwgI0mbEU/D7YFxwQ2Q kLnblnpbcgDlA2JkM4HKBFpOVWMKrTeNYQIthxWcjqw8OwcBFL7h9ZxEy69Klw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v5 4/4] clocksource/timer-econet-en751221: Support EN751627 without percpu IRQ Date: Sat, 16 May 2026 23:39:43 +0000 Message-Id: <20260516233943.49502-5-cjd@cjdns.fr> In-Reply-To: <20260516233943.49502-1-cjd@cjdns.fr> References: <20260516233943.49502-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751627 is based on the 1004Kc which uses a different interrupt number for each CPU timer. Support both this and the EN751221 which uses a single percpu interrupt. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 120 ++++++++++++++++---- 1 file changed, 96 insertions(+), 24 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index ed750e39cc4f..529f81118eef 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -21,10 +21,12 @@ #define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) /* 34Kc hardware has 1 block and 1004Kc has 2. */ #define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) +#define ECONET_NUM_IRQS NR_CPUS =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; - int irq; + int irqs[ECONET_NUM_IRQS]; + bool is_percpu; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -99,6 +101,25 @@ static int cevt_init_cpu(uint cpu) struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, cpu); u32 reg; =20 + if (!reg_ctl(cpu)) { + pr_err("%s: missing address resource for CPU %d\n", cd->name, + cpu); + return -EINVAL; + } + if (cd->irq <=3D 0) { + pr_err("%s: missing IRQ for CPU %d\n", cd->name, cpu); + return -EINVAL; + } + if (!econet_timer.is_percpu) { + int ret =3D irq_force_affinity(cd->irq, cpumask_of(cpu)); + + if (ret) { + pr_err("%s: failed to set IRQ affinity to CPU %d: %pe\n", + cd->name, cpu, ERR_PTR(ret)); + return ret; + } + } + pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu); =20 reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); @@ -107,7 +128,10 @@ static int cevt_init_cpu(uint cpu) clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + if (econet_timer.is_percpu) + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + else + enable_irq(cd->irq); =20 return 0; } @@ -138,19 +162,48 @@ static void __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D econet_timer.irq; + + if (econet_timer.is_percpu) + cd->irq =3D econet_timer.irqs[0]; + else + cd->irq =3D econet_timer.irqs[i]; + cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 - cevt_dev_init(i); + /* + * Tolerate CPUs that could exist but don't. + * Fail in cevt_init_cpu when they try to start. + */ + if (reg_ctl(i)) + cevt_dev_init(i); } } =20 static int __init timer_init(struct device_node *np) { - int num_blocks =3D DIV_ROUND_UP(num_possible_cpus(), 2); + int num_blocks =3D of_address_count(np); + int num_irqs =3D of_irq_count(np); struct clk *clk; - int ret; + int ret, i; + + econet_timer.is_percpu =3D of_device_is_compatible(np, "econet,en751221-t= imer"); + + if (econet_timer.is_percpu && num_irqs !=3D 1) { + pr_err("%pOFn: EN751221 clock must have 1 IRQ not %d\n", np, + num_irqs); + return -EINVAL; + } + if (num_irqs > ARRAY_SIZE(econet_timer.irqs)) { + pr_err("%pOFn: Too many IRQs max %d got %d\n", np, + ARRAY_SIZE(econet_timer.irqs), num_irqs); + return -EINVAL; + } + if (num_blocks > ARRAY_SIZE(econet_timer.membase)) { + pr_err("%pOFn: Too many regs: max %d got %d\n", np, + ARRAY_SIZE(econet_timer.membase), num_blocks); + return -EINVAL; + } =20 clk =3D of_clk_get(np, 0); if (IS_ERR(clk)) { @@ -160,7 +213,7 @@ static int __init timer_init(struct device_node *np) =20 econet_timer.freq_hz =3D clk_get_rate(clk); =20 - for (int i =3D 0; i < num_blocks; i++) { + for (i =3D 0; i < num_blocks; i++) { econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); @@ -169,22 +222,32 @@ static int __init timer_init(struct device_node *np) } } =20 - econet_timer.irq =3D irq_of_parse_and_map(np, 0); - if (econet_timer.irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed\n", np); - ret =3D -EINVAL; - goto out_membase; + for (i =3D 0; i < num_irqs; i++) { + econet_timer.irqs[i] =3D irq_of_parse_and_map(np, i); + if (econet_timer.irqs[i] <=3D 0) { + pr_err("%pOFn: failed mapping irq %d\n", np, i); + ret =3D -EINVAL; + goto out_irq_mapping; + } } =20 - irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); - - ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, - &econet_timer_pcpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, - econet_timer.irq, ret); - goto out_irq_mapping; + for (i =3D 0; i < num_irqs; i++) { + irq_set_status_flags(econet_timer.irqs[i], IRQ_NOAUTOEN); + + if (econet_timer.is_percpu) + ret =3D request_percpu_irq(econet_timer.irqs[i], + cevt_interrupt, np->name, + &econet_timer_pcpu); + else + ret =3D request_irq(econet_timer.irqs[i], cevt_interrupt, + IRQF_TIMER | IRQF_NOBALANCING, + np->name, NULL); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed: %pe\n", np, + i, ERR_PTR(ret)); + goto out_irq_free; + } } =20 cevt_init(np); @@ -216,11 +279,19 @@ static int __init timer_init(struct device_node *np) return 0; =20 out_irq_free: - free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); + while (--i >=3D 0) { + if (econet_timer.is_percpu) + free_percpu_irq(econet_timer.irqs[i], &econet_timer_pcpu); + else + free_irq(econet_timer.irqs[i], NULL); + } out_irq_mapping: - irq_dispose_mapping(econet_timer.irq); + for (i =3D 0; i < num_irqs; i++) { + if (econet_timer.irqs[i] > 0) + irq_dispose_mapping(econet_timer.irqs[i]); + } out_membase: - for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + for (i =3D 0; i < num_blocks; i++) { if (econet_timer.membase[i]) iounmap(econet_timer.membase[i]); } @@ -229,3 +300,4 @@ static int __init timer_init(struct device_node *np) } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); +TIMER_OF_DECLARE(econet_timer_en751627, "econet,en751627-timer", timer_ini= t); --=20 2.39.5