From nobody Mon May 25 08:12:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B61B72236F7; Sat, 16 May 2026 21:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968652; cv=none; b=V4qnyMH7IrBv677rTuFfiY+zolBXVygg8YMr3hZO3VjQM94gtgqfdDnu0si2ZKZllUVBMi8gAuWEvenHy2YoUC14vZ9NseMjQ0vXuOBaR99wCiy2WHQ4ttSvPo4BQhQacsPwTdZfFHWTTKSf+IHnfiICwhe9Yfh3dPoyPvHQ8EU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968652; c=relaxed/simple; bh=4AHVPOm7Ty5OQDgZI6VyLTMWXgglLaOgL2pOBQiHUM0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NU2JK04pnbGWF25BLC7Yf3W23H57QBfE8agko0pA+pPej7vv88TV7GKJw/GG8YDUoF7i4Teeie6RR/bkNnyJYQWyKZFa06VF2E0ScgWrDmNGwegg7lHahMz9NQKabati37FRXSs7Kk8W08GgMiFXRel311pFVLxb/Wg84TWYTSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Fjivqysl; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Fjivqysl" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2F7E13FA12B; Sat, 16 May 2026 23:57:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778968648; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=GHkeIisOHTKNaeFYyyTywb9lsuelDoJrv0RnP6LCepo=; b=Fjivqysltti9GfGzX6HINw04golNoBfoyr4xvWDWKTbe/7TA6pEl34it85XVpKWml4V42Y avYBntZfOBOZl9rXHL29M4EDLoXeQctJP9DEbpQDZA/DB/ZtS2PmUhKXZHGCdPmjUDf2Xe NA+mMBscYCqWs+NuxD1j0za61ITaqRqA8tam3aLH8d/zAANI4t8lA0OiY7tVzples/wKtK wH+U4lnfPsMDXTaoflofekk4HIabRmcnb0AOMEwYEJOAxpT+GJMDHI0TD4lZS5XXfYNUS2 xzca4p8ngG4vt10a025RG+3DFoNiVdcaMaFpbjMisYL78rTyu3J3YUyMrJc+LQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle , Conor Dooley Subject: [PATCH v4 1/4] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Date: Sat, 16 May 2026 21:57:17 +0000 Message-Id: <20260516215720.4160831-2-cjd@cjdns.fr> In-Reply-To: <20260516215720.4160831-1-cjd@cjdns.fr> References: <20260516215720.4160831-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This hardware is found in the EN751221 SoC family as well as the EN751627. The former uses a percpu IRQ for all timers while the latter uses an individual IRQ number per timer. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/timer/econet,en751221-timer.yaml | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.= yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml index c1e7c2b6afde..16f32741473f 100644 --- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -12,8 +12,9 @@ maintainers: description: The EcoNet High Precision Timer (HPT) is a timer peripheral found in var= ious EcoNet SoCs, including the EN751221 and EN751627 families. It provides p= er-VPE - count/compare registers and a per-CPU control register, with a single in= terrupt - line using a percpu-devid interrupt mechanism. + count/compare registers and a per-CPU control register. On EN751221 it u= ses a + single interrupt line using a percpu-devid interrupt mechanism, and on + EN751627 it uses an interrupt per VPE. =20 properties: compatible: @@ -28,8 +29,8 @@ properties: maxItems: 2 =20 interrupts: - maxItems: 1 - description: A percpu-devid timer interrupt shared across CPUs. + minItems: 1 + maxItems: 4 =20 clocks: maxItems: 1 @@ -52,21 +53,31 @@ allOf: items: - description: VPE timers 0 and 1 - description: VPE timers 2 and 3 + interrupts: + description: An interrupt for each timer (one per VPE) + minItems: 4 else: properties: reg: items: - description: VPE timers 0 and 1 + interrupts: + description: A percpu-devid timer interrupt shared across timers + maxItems: 1 =20 additionalProperties: false =20 examples: - | + #include timer@1fbf0400 { - compatible =3D "econet,en751627-timer", "econet,en751221-timer"; + compatible =3D "econet,en751627-timer"; reg =3D <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; interrupt-parent =3D <&intc>; - interrupts =3D <30>; + interrupts =3D , + , + , + ; clocks =3D <&hpt_clock>; }; - | --=20 2.39.5 From nobody Mon May 25 08:12:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 281DA38643B; Sat, 16 May 2026 21:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968653; cv=none; b=tQ2ze82jo6d2RyptaSh+yj5p0QqYgWNlPFUVUsIEds1ct4DdcQFToHlyqzTrC/5bc4veJ+etZNAjSUwQ3FTZTGGS5fyL9e0OCvRFqUCF7y/P1YQV8cx4MQxGdrBfwLXP2lODfuQzfy3UZUGzSsAn/KGxF/P7gONrDco95sYkyjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968653; c=relaxed/simple; bh=7wxpOJISV76f+OA+eUJDFOYKOmSTMyJ0sT0aUgy6Jx0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S/r24PFUo7bGrww/VpLuzwT5pbjf/SY4i3YQYxWynPaNToDRlExgcTqwya6pBgRprxZSYuNickagTWTadPddsqy9MSvetgtxJLn7tGqdN/i0YtzItL+yao6QZdSn5yN9Gls3QMvWe3BgdmsO0hKLeVt/eCCySqTIfkKNt0bbvtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=DUbRHobk; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="DUbRHobk" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 072CD3FA133; Sat, 16 May 2026 23:57:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778968650; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Q0h8RiPN75sqVf0my0iCAciaGj/g/mvtHx8ng9fbWfM=; b=DUbRHobkuF7yBfQa5mNCHXmv5Ux84Ai+pPKjohj2QEn7RIkFfiXPefsAGPXAXI4p4uonhX wqyQuEfKiHpyjIbu3ueCkrDCsw8PqdtrOPdiN7uhwhyj4nvZHFSEElAFVgWSpdWs43bjXz MEO0RgrKr8VjJbVfExEa5tHLjWRz4J+d0UgQb6Ypo1G0g4DoQb7jwf2KaDro/iROclmlTB ycloH846FKY5vQQIRiWpyp4aQ4rvyACBCywwQRq1sc8SdiSKH0VPIPrg5QGZvewfYYaMkA yCLXTZOPI1qL6PvyTwcQY8qicM0TrkxhM07fuZ3axioeBj+9Ma2KQq+3HcDJJg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v4 2/4] clocksource/timer-econet-en751221: Init teardown on error if possible Date: Sat, 16 May 2026 21:57:18 +0000 Message-Id: <20260516215720.4160831-3-cjd@cjdns.fr> In-Reply-To: <20260516215720.4160831-1-cjd@cjdns.fr> References: <20260516215720.4160831-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" As a clocksource, much of the initialization process is irreversible and the impact of a failure to initialize is a failure to boot. That said, good practice is to attempt a clean exit if probing fails, and supporting this pattern will reduce the likelihood that future contributions introduce a bug by trying to teardown after it is no longer possible to do so. Convert the init process into two clearly delineated phases, one which is reverted in case of error, and the other which can't be. Move all IRQ and address resource mapping before that point, and add teardown logic in case of error before the point of no return. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 82 ++++++++++++--------- 1 file changed, 48 insertions(+), 34 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 4008076b1a21..155471f68e6f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -24,6 +24,7 @@ =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; + int irq; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -126,22 +127,9 @@ static void __init cevt_dev_init(uint cpu) iowrite32(U32_MAX, reg_compare(cpu)); } =20 -static int __init cevt_init(struct device_node *np) +static void __init cevt_init(struct device_node *np) { - int i, irq, ret; - - irq =3D irq_of_parse_and_map(np, 0); - if (irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed", np); - return -EINVAL; - } - - ret =3D request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_p= cpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret); - goto err_unmap_irq; - } + int i; =20 for_each_possible_cpu(i) { struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, i); @@ -151,21 +139,12 @@ static int __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D irq; + cd->irq =3D econet_timer.irq; cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 cevt_dev_init(i); } - - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, - "clockevents/econet/timer:starting", - cevt_init_cpu, NULL); - return 0; - -err_unmap_irq: - irq_dispose_mapping(irq); - return ret; } =20 static int __init timer_init(struct device_node *np) @@ -186,22 +165,45 @@ static int __init timer_init(struct device_node *np) econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); - return -ENXIO; + ret =3D -ENXIO; + goto out_membase; } } =20 + econet_timer.irq =3D irq_of_parse_and_map(np, 0); + if (econet_timer.irq <=3D 0) { + pr_err("%pOFn: irq_of_parse_and_map failed\n", np); + ret =3D -EINVAL; + goto out_membase; + } + + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, + &econet_timer_pcpu); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, + econet_timer.irq, ret); + goto out_irq_mapping; + } + + cevt_init(np); + + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "clockevents/econet/timer:starting", + cevt_init_cpu, NULL); + if (ret < 0) { + pr_err("%pOFn: cpuhp setup failed (%d)\n", np, ret); + goto out_irq_free; + } + + /* Point of no return, do not attempt to tear down after this. */ + /* For clocksource purposes always read clock zero, whatever the CPU */ ret =3D clocksource_mmio_init(reg_count(0), np->name, econet_timer.freq_hz, 301, ECONET_BITS, clocksource_mmio_readl_up); - if (ret) { - pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret); - return ret; - } - - ret =3D cevt_init(np); - if (ret < 0) - return ret; + if (ret) + pr_err("%pOFn: clocksource_mmio_init failed: %d\n", np, ret); =20 sched_clock_register(sched_clock_read, ECONET_BITS, econet_timer.freq_hz); @@ -211,6 +213,18 @@ static int __init timer_init(struct device_node *np) (econet_timer.freq_hz / 1000) % 1000); =20 return 0; + +out_irq_free: + free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); +out_irq_mapping: + irq_dispose_mapping(econet_timer.irq); +out_membase: + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + if (econet_timer.membase[i]) + iounmap(econet_timer.membase[i]); + } + + return ret; } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); --=20 2.39.5 From nobody Mon May 25 08:12:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE4A5384250; Sat, 16 May 2026 21:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968655; cv=none; b=pgyN1einOKvLGB1NfsjnfUVuoe2zkqs3QIMvNq75LJWvRuBir0Q4WpL96LKJ4tugGRYh9Wf5uU1OxRGV3oP2TbNcA9taACDUBeKFjPHCREFCM1CPwVlw9dluRqeCiu523ZAbMZWDbGhqOhCxtHnVWJPiQtefPk8oPvl0jK3Y3DE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968655; c=relaxed/simple; bh=gBGMI6S3o4+n+8pLpjBQ+nXTfkXL9j4qXfNkTwzvv5Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sFzotNIIkjnbr+7hLhOr1X4hZ0uYGgHVm27MXk1wBavtsEsR1aqtgxnAyuRfmV5WLgxorfbxka5skE22j88KXR5UhtGAPFQddG1yrRxNXisTmx53sLS+zdPTIwYIC8Rlug1WjGUz69rHw9RtELw8wnphWJwKTKjAsUEF8QXfkQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=kvIOV0+Z; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="kvIOV0+Z" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6EAE23F9C13; Sat, 16 May 2026 23:57:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778968651; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=m+6v+hjQch8RJ+bE8KqFuX68S8nN6mY6vSXBtyBFUJQ=; b=kvIOV0+ZYsHZNjVB+jG6+n5X7x9owhx6JRCGPHpygCfYUPGhjv14v08Lga6SRt2uId12xB 2/z1EidcqOCgroyt+eA3OU+dccxH6xqScRbTXQslEFGvgImYz5ggKmHK8yEPRsZofX32k+ Bn0A1m5v1ta+GkmPnDntumn5F5Cnb7ZHpN6Vv8ffjc9JXRUaUkgT9TCO9r56/7ehMpEZxH IyNVVI0KO9JsAk5HWsfuIweRXRQGSSDc3AlwShhZ++AXDVVxmRsEsKIyxVIuR8qYAZFN5G VDW8IEQr7Ya7yHX3DsYgLDYIxRPbOjDqx0YKMmI7p6jivZqPqMGoGPskDzqQAA== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v4 3/4] clocksource/timer-econet-en751221: Disable IRQ until cevt registered Date: Sat, 16 May 2026 21:57:19 +0000 Message-Id: <20260516215720.4160831-4-cjd@cjdns.fr> In-Reply-To: <20260516215720.4160831-1-cjd@cjdns.fr> References: <20260516215720.4160831-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Eliminate a race condition where cevt_interrupt may trigger before clockevents_config_and_register has been called, and dev->event_handler is at that point NULL. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 155471f68e6f..ed750e39cc4f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -104,12 +104,11 @@ static int cevt_init_cpu(uint cpu) reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); iowrite32(reg, reg_ctl(cpu)); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); - - /* Do this last because it synchronously configures the timer */ clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + return 0; } =20 @@ -177,6 +176,8 @@ static int __init timer_init(struct device_node *np) goto out_membase; } =20 + irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, &econet_timer_pcpu); =20 --=20 2.39.5 From nobody Mon May 25 08:12:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCAA2236F7; Sat, 16 May 2026 21:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968663; cv=none; b=l0xHSAYYeIpb12pFD37bB99Zp/aqIst+T2cqfOk1LSI5OFunCR1B2t1cobxAKQhyWc80JWM9epZ17qMPvnusYA4Q14jXVLCDBBjR+Du7+5GwPQP+n2dScvY4TJVhYOxLjc9PR3tlSv1NoDdug0bo1tq6yLZHgo42S718sWQjyuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778968663; c=relaxed/simple; bh=fs101GKXojbBD0OSaUl1HJrb0AAsirp6lK1wI8Zk2So=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QDwOf3gudV270qZqL3toyOIxxx66EDaTSLUDgoSks88ISWvmojl0ZcMc6V8wra8fRiBvTWwX7IHKsw7J7nhz1SAhyJEQSPEkhCl74JEzbtF0q5c4ANawfjb763KK1JI387eofGO/H9Zjy6bWBlnRz5g7p85V++LxHb4FaBuHSk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=avzoVxrR; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="avzoVxrR" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2B9383F9C20; Sat, 16 May 2026 23:57:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778968653; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Vd8ofrTwwLFycghcQYAAn0t8YToXzlVuyDYfsfvMeX0=; b=avzoVxrRSeV1qjf0DAXrEOtIFfW5e56YxLP6vCvUFv45nnj9ijvdNGTasJQU5dvXJLEotO 1FcBvpFySVi0gIQIKpnFArOSpnKaXJO4Z5TJOFAajpQpe0xFytoP2UnMLrwSr2q1FOEFHW ItLpfwIimccqQSEwWVDwAIWNcuc4Kdx1OsT+eo+EbJU+iypEISC5Olhcs8XaxDFSzkkgmo 4A9c/pEsu/LmByJSERsvQDrJvQCCXNLN9+bxnkqVsEJO+HlejOntxCpjsF9tnm9CRmdcnY Vd7sSmieKvreGTMO9af5wmHMjMzxhd51VObcV7XP142OfwOB6EOkSR54Mst6/A== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v4 4/4] clocksource/timer-econet-en751221: Support EN751627 without percpu IRQ Date: Sat, 16 May 2026 21:57:20 +0000 Message-Id: <20260516215720.4160831-5-cjd@cjdns.fr> In-Reply-To: <20260516215720.4160831-1-cjd@cjdns.fr> References: <20260516215720.4160831-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751627 is based on the 1004Kc which uses a different interrupt number for each CPU timer. Support both this and the EN751221 which uses a single percpu interrupt. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 121 ++++++++++++++++---- 1 file changed, 97 insertions(+), 24 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index ed750e39cc4f..40f3b370485f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -21,10 +21,12 @@ #define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) /* 34Kc hardware has 1 block and 1004Kc has 2. */ #define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) +#define ECONET_NUM_IRQS NR_CPUS =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; - int irq; + int irqs[ECONET_NUM_IRQS]; + bool is_percpu; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -99,6 +101,25 @@ static int cevt_init_cpu(uint cpu) struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, cpu); u32 reg; =20 + if (!reg_ctl(cpu)) { + pr_err("%s: missing address resource for CPU %d\n", cd->name, + cpu); + return -EINVAL; + } + if (cd->irq <=3D 0) { + pr_err("%s: missing IRQ for CPU %d\n", cd->name, cpu); + return -EINVAL; + } + if (!econet_timer.is_percpu) { + int ret =3D irq_force_affinity(cd->irq, cpumask_of(cpu)); + + if (ret) { + pr_err("%s: failed to set IRQ affinity to CPU %d: %pe\n", + cd->name, cpu, ERR_PTR(ret)); + return ret; + } + } + pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu); =20 reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); @@ -107,7 +128,10 @@ static int cevt_init_cpu(uint cpu) clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + if (econet_timer.is_percpu) + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + else + enable_irq(cd->irq); =20 return 0; } @@ -138,19 +162,48 @@ static void __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D econet_timer.irq; + + if (econet_timer.is_percpu) + cd->irq =3D econet_timer.irqs[0]; + else + cd->irq =3D econet_timer.irqs[i]; + cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 - cevt_dev_init(i); + /* + * Tolerate CPUs that could exist but don't. + * Fail in cevt_init_cpu when they try to start. + */ + if (reg_ctl(i)) + cevt_dev_init(i); } } =20 static int __init timer_init(struct device_node *np) { - int num_blocks =3D DIV_ROUND_UP(num_possible_cpus(), 2); + int num_blocks =3D of_address_count(np); + int num_irqs =3D of_irq_count(np); struct clk *clk; - int ret; + int ret, i; + + econet_timer.is_percpu =3D of_device_is_compatible(np, "econet,en751221-t= imer"); + + if (econet_timer.is_percpu && num_irqs !=3D 1) { + pr_err("%pOFn: EN751221 clock must have 1 IRQ not %d\n", np, + num_irqs); + return -EINVAL; + } + if (num_irqs > ARRAY_SIZE(econet_timer.irqs)) { + pr_err("%pOFn: Too many IRQs max %d got %d\n", np, + ARRAY_SIZE(econet_timer.irqs), num_irqs); + return -EINVAL; + } + if (num_blocks > ARRAY_SIZE(econet_timer.membase)) { + pr_err("%pOFn: Too many regs: max %d got %d\n", np, + ARRAY_SIZE(econet_timer.membase), num_blocks); + return -EINVAL; + } =20 clk =3D of_clk_get(np, 0); if (IS_ERR(clk)) { @@ -160,7 +213,7 @@ static int __init timer_init(struct device_node *np) =20 econet_timer.freq_hz =3D clk_get_rate(clk); =20 - for (int i =3D 0; i < num_blocks; i++) { + for (i =3D 0; i < num_blocks; i++) { econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); @@ -169,22 +222,32 @@ static int __init timer_init(struct device_node *np) } } =20 - econet_timer.irq =3D irq_of_parse_and_map(np, 0); - if (econet_timer.irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed\n", np); - ret =3D -EINVAL; - goto out_membase; + for (i =3D 0; i < num_irqs; i++) { + econet_timer.irqs[i] =3D irq_of_parse_and_map(np, i); + if (econet_timer.irqs[i] <=3D 0) { + pr_err("%pOFn: failed mapping irq %d\n", np, i); + ret =3D -EINVAL; + goto out_irq_mapping; + } } =20 - irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); - - ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, - &econet_timer_pcpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, - econet_timer.irq, ret); - goto out_irq_mapping; + for (i =3D 0; i < num_irqs; i++) { + irq_set_status_flags(econet_timer.irqs[i], IRQ_NOAUTOEN); + + if (econet_timer.is_percpu) + ret =3D request_percpu_irq(econet_timer.irqs[i], + cevt_interrupt, np->name, + &econet_timer_pcpu); + else + ret =3D request_irq(econet_timer.irqs[i], cevt_interrupt, + IRQF_TIMER | IRQF_NOBALANCING, + np->name, NULL); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed: %pe\n", np, + i, ERR_PTR(ret)); + goto out_irq_free; + } } =20 cevt_init(np); @@ -216,11 +279,20 @@ static int __init timer_init(struct device_node *np) return 0; =20 out_irq_free: - free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); + while (--i >=3D 0) { + if (econet_timer.is_percpu) { + free_percpu_irq(econet_timer.irqs[i], &econet_timer_pcpu); + } else { + free_irq(econet_timer.irqs[i], NULL); + } + } out_irq_mapping: - irq_dispose_mapping(econet_timer.irq); + for (i =3D 0; i < num_irqs; i++) { + if (econet_timer.irqs[i] > 0) + irq_dispose_mapping(econet_timer.irqs[i]); + } out_membase: - for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + for (i =3D 0; i < num_blocks; i++) { if (econet_timer.membase[i]) iounmap(econet_timer.membase[i]); } @@ -229,3 +301,4 @@ static int __init timer_init(struct device_node *np) } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); +TIMER_OF_DECLARE(econet_timer_en751627, "econet,en751627-timer", timer_ini= t); --=20 2.39.5