From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5AFF333EB0E; Sat, 16 May 2026 18:30:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956260; cv=none; b=riSwy+WVS9KT1hiuMY7unHdSUfKHpKebYvjmdsg+02BmDnuxM5g7u178uuB3ICOiYNaVe0Z4Ebn4IUmfgc11rLiLaVBepwBl6ChdLC6fkw/ZK+07Xs0FxRVRXS0TgAG5nQS/CXxaQ1IqgdFtYNZ5qcBpE+x60c9ebLgs6mYceoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956260; c=relaxed/simple; bh=qd/xGyy1flBlfaXhDHK+Ds4y1aU389ligvtTqKbtVIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EwL/JEMfBLjK2Wxs+GOPiAXmQ+IfOt7u+E0LmHGfbnsDvRra3SuoL5B061WlNhuZdPJY7GKXMgiKRqWsYIhPfIeTOtuV35uvt12SkCVuI0v3fNaMmxc5AvGRzqrFiA76PEn2cORJEdvslYKRaK5V/r7sFdGd7VVov403iaYKwEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=qYLFM3NY; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="qYLFM3NY" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72B521CDD; Sat, 16 May 2026 11:30:46 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0575A3F85F; Sat, 16 May 2026 11:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956251; bh=qd/xGyy1flBlfaXhDHK+Ds4y1aU389ligvtTqKbtVIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qYLFM3NYxZOKEcRByQD888YKv9cDtPlQulAsDH4gYouxcbFBLRdhGGhXDB3q3Ks1G Mqy9/mVkoCVv4zHc5cnqAkD/b75zKUcg9YAUrrjuUWJW7zJRnghpbJ0gW9dAbK0wG+ DFc6cd0oPWpJ7kJX0BclGN5uH3urGPG+NkUDiThU= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 1/9] KVM: arm64: selftests: Add GPR save/restore functions for NV Date: Sat, 16 May 2026 19:29:55 +0100 Message-ID: <20260516183003.799058-2-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adapt entry.S and hyp-entry.S from arch/arm64/kvm/hyp so that guest hypervisors can save and restore GPRs, and provide exception handlers to regain control after the nested guest exits. Other system register save/restore will be added later on demand. Signed-off-by: Wei-Lin Chang --- tools/testing/selftests/kvm/Makefile.kvm | 3 + .../selftests/kvm/include/arm64/nested.h | 45 ++++++ tools/testing/selftests/kvm/lib/arm64/entry.S | 132 ++++++++++++++++++ .../selftests/kvm/lib/arm64/hyp-entry.S | 77 ++++++++++ .../testing/selftests/kvm/lib/arm64/nested.c | 12 ++ 5 files changed, 269 insertions(+) create mode 100644 tools/testing/selftests/kvm/include/arm64/nested.h create mode 100644 tools/testing/selftests/kvm/lib/arm64/entry.S create mode 100644 tools/testing/selftests/kvm/lib/arm64/hyp-entry.S create mode 100644 tools/testing/selftests/kvm/lib/arm64/nested.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 98da9fa4b8b7..3dc3e39f7025 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -30,10 +30,13 @@ LIBKVM_x86 +=3D lib/x86/svm.c LIBKVM_x86 +=3D lib/x86/ucall.c LIBKVM_x86 +=3D lib/x86/vmx.c =20 +LIBKVM_arm64 +=3D lib/arm64/entry.S LIBKVM_arm64 +=3D lib/arm64/gic.c LIBKVM_arm64 +=3D lib/arm64/gic_v3.c LIBKVM_arm64 +=3D lib/arm64/gic_v3_its.c LIBKVM_arm64 +=3D lib/arm64/handlers.S +LIBKVM_arm64 +=3D lib/arm64/hyp-entry.S +LIBKVM_arm64 +=3D lib/arm64/nested.c LIBKVM_arm64 +=3D lib/arm64/processor.c LIBKVM_arm64 +=3D lib/arm64/spinlock.c LIBKVM_arm64 +=3D lib/arm64/ucall.c diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h new file mode 100644 index 000000000000..86d931facacb --- /dev/null +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ARM64 Nested virtualization defines + */ + +#ifndef SELFTEST_KVM_NESTED_H +#define SELFTEST_KVM_NESTED_H + +#define ARM_EXCEPTION_IRQ 0 +#define ARM_EXCEPTION_EL1_SERROR 1 +#define ARM_EXCEPTION_TRAP 2 +#define ARM_EXCEPTION_IL 3 +#define ARM_EXCEPTION_EL2_IRQ 4 +#define ARM_EXCEPTION_EL2_SERROR 5 +#define ARM_EXCEPTION_EL2_TRAP 6 + +#ifndef __ASSEMBLER__ + +#include +#include "kvm_util.h" + +extern char hyp_vectors[]; + +struct cpu_context { + struct user_pt_regs regs; /* sp =3D sp_el0 */ +}; + +struct vcpu { + struct cpu_context context; +}; + +/* + * KVM has host_data and hyp_context, combine them because we're only doing + * hyp context. + */ +struct hyp_data { + struct cpu_context hyp_context; +}; + +u64 __guest_enter(struct vcpu *vcpu, struct cpu_context *hyp_context); +void __hyp_exception(u64 type); + +#endif /* !__ASSEMBLER__ */ + +#endif /* SELFTEST_KVM_NESTED_H */ diff --git a/tools/testing/selftests/kvm/lib/arm64/entry.S b/tools/testing/= selftests/kvm/lib/arm64/entry.S new file mode 100644 index 000000000000..33bedf5e7fb2 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/arm64/entry.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * adapted from arch/arm64/kvm/hyp/entry.S + */ + +/* + * Manually define these for now + */ +// offsetof(struct vcpu, context) +#define CPU_CONTEXT 0 +// offsetof(struct cpu_context, regs) +#define CPU_USER_PT_REGS 0 + +#define CPU_XREG_OFFSET(x) (CPU_USER_PT_REGS + 8*x) +#define CPU_LR_OFFSET CPU_XREG_OFFSET(30) +#define CPU_SP_EL0_OFFSET (CPU_LR_OFFSET + 8) + +.macro save_callee_saved_regs ctxt + str x18, [\ctxt, #CPU_XREG_OFFSET(18)] + stp x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)] + stp x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)] + stp x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)] + stp x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)] + stp x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)] + stp x29, lr, [\ctxt, #CPU_XREG_OFFSET(29)] +.endm + +.macro restore_callee_saved_regs ctxt + ldr x18, [\ctxt, #CPU_XREG_OFFSET(18)] + ldp x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)] + ldp x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)] + ldp x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)] + ldp x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)] + ldp x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)] + ldp x29, lr, [\ctxt, #CPU_XREG_OFFSET(29)] +.endm + +.macro save_sp_el0 ctxt, tmp + mrs \tmp, sp_el0 + str \tmp, [\ctxt, #CPU_SP_EL0_OFFSET] +.endm + +.macro restore_sp_el0 ctxt, tmp + ldr \tmp, [\ctxt, #CPU_SP_EL0_OFFSET] + msr sp_el0, \tmp +.endm + +/* + * u64 __guest_enter(struct vcpu *vcpu, struct cpu_context *hyp_context); + */ +.globl __guest_enter +__guest_enter: + // x0: vcpu + // x1: hyp context + + // Store vcpu and hyp context pointer on the stack + stp x0, x1, [sp, #-16]! + + // Store the hyp regs + save_callee_saved_regs x1 + + // Save hyp's sp_el0 + save_sp_el0 x1, x2 + + // x29 =3D vCPU user pt regs + add x29, x0, #CPU_CONTEXT + + // Restore the guest's sp_el0 + restore_sp_el0 x29, x0 + + // Restore guest regs x0-x17 + ldp x0, x1, [x29, #CPU_XREG_OFFSET(0)] + ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)] + ldp x4, x5, [x29, #CPU_XREG_OFFSET(4)] + ldp x6, x7, [x29, #CPU_XREG_OFFSET(6)] + ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)] + ldp x10, x11, [x29, #CPU_XREG_OFFSET(10)] + ldp x12, x13, [x29, #CPU_XREG_OFFSET(12)] + ldp x14, x15, [x29, #CPU_XREG_OFFSET(14)] + ldp x16, x17, [x29, #CPU_XREG_OFFSET(16)] + + // Restore guest regs x18-x29, lr + restore_callee_saved_regs x29 + + // Do not touch any register after this! + eret + +.globl __guest_exit +__guest_exit: + // x0: return code + // x1: vcpu + // x2-x29,lr: vcpu regs + // vcpu x0-x1 on the stack + + add x1, x1, #CPU_CONTEXT + + // Store the guest regs x2 and x3 + stp x2, x3, [x1, #CPU_XREG_OFFSET(2)] + + // Retrieve the guest regs x0-x1 from the stack + ldp x2, x3, [sp], #16 // x0, x1 + + // Store the guest regs x0-x1 and x4-x17 + stp x2, x3, [x1, #CPU_XREG_OFFSET(0)] + stp x4, x5, [x1, #CPU_XREG_OFFSET(4)] + stp x6, x7, [x1, #CPU_XREG_OFFSET(6)] + stp x8, x9, [x1, #CPU_XREG_OFFSET(8)] + stp x10, x11, [x1, #CPU_XREG_OFFSET(10)] + stp x12, x13, [x1, #CPU_XREG_OFFSET(12)] + stp x14, x15, [x1, #CPU_XREG_OFFSET(14)] + stp x16, x17, [x1, #CPU_XREG_OFFSET(16)] + + // Store the guest regs x18-x29, lr + save_callee_saved_regs x1 + + // Store the guest's sp_el0 + save_sp_el0 x1, x2 + + // At this point x0 and x1 on the stack is popped, so next is vCPU + // pointer, then hyp_context pointer + // *sp =3D=3D vCPU, *(sp + 8) =3D=3D hyp_context + // load x2 =3D hyp_context, x3 is just for ldp and popping sp + ldp x3, x2, [sp], #16 + + // Restore hyp's sp_el0 + restore_sp_el0 x2, x3 + + // Now restore the hyp regs + restore_callee_saved_regs x2 + + dsb sy // Synchronize against in-flight ld/st + ret diff --git a/tools/testing/selftests/kvm/lib/arm64/hyp-entry.S b/tools/test= ing/selftests/kvm/lib/arm64/hyp-entry.S new file mode 100644 index 000000000000..6341f6e05c90 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/arm64/hyp-entry.S @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * adapted from arch/arm64/kvm/hyp/hyp-entry.S + */ + +#include "nested.h" + +// skip over x0, x1 saved on entry, must be used only before the stack is = modified +.macro get_vcpu_ptr vcpu + ldr \vcpu, [sp, #16] +.endm + + .text + +el1_sync: // Guest trapped into EL2 + + get_vcpu_ptr x1 + mov x0, #ARM_EXCEPTION_TRAP + b __guest_exit + +el1_irq: +el1_fiq: + get_vcpu_ptr x1 + mov x0, #ARM_EXCEPTION_IRQ + b __guest_exit + +el1_error: + get_vcpu_ptr x1 + mov x0, #ARM_EXCEPTION_EL1_SERROR + b __guest_exit + +el2_sync: + mov x0, #ARM_EXCEPTION_EL2_TRAP + b __hyp_exception + +el2_irq: +el2_fiq: + mov x0, #ARM_EXCEPTION_EL2_IRQ + b __hyp_exception + +el2_error: + mov x0, #ARM_EXCEPTION_EL2_SERROR + b __hyp_exception + + + .ltorg + + .align 11 + +.globl hyp_vectors +hyp_vectors: + +.macro exception_vector target + .align 7 + stp x0, x1, [sp, #-16]! + b \target +.endm + + exception_vector el2_sync // Synchronous EL2t + exception_vector el2_irq // IRQ EL2t + exception_vector el2_fiq // FIQ EL2t + exception_vector el2_error // Error EL2t + + exception_vector el2_sync // Synchronous EL2h + exception_vector el2_irq // IRQ EL2h + exception_vector el2_fiq // FIQ EL2h + exception_vector el2_error // Error EL2h + + exception_vector el1_sync // Synchronous 64-bit EL1 + exception_vector el1_irq // IRQ 64-bit EL1 + exception_vector el1_fiq // FIQ 64-bit EL1 + exception_vector el1_error // Error 64-bit EL1 + + exception_vector el1_sync // Synchronous 32-bit EL1 + exception_vector el1_irq // IRQ 32-bit EL1 + exception_vector el1_fiq // FIQ 32-bit EL1 + exception_vector el1_error // Error 32-bit EL1 diff --git a/tools/testing/selftests/kvm/lib/arm64/nested.c b/tools/testing= /selftests/kvm/lib/arm64/nested.c new file mode 100644 index 000000000000..06ddaab2436f --- /dev/null +++ b/tools/testing/selftests/kvm/lib/arm64/nested.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM64 Nested virtualization helpers + */ + +#include "nested.h" +#include "test_util.h" + +void __hyp_exception(u64 type) +{ + GUEST_FAIL("Unexpected hyp exception! type: %lx\n", type); +} --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 364FE33D503; Sat, 16 May 2026 18:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956257; cv=none; b=CKhoeQ7Q8Fmc8/3sdPqobaH2hGPuySfB1GBv+dz5mGUiCydHoPECbsZfvgmsmOMZDRU76w4GV/e0kOPkd/Nl31FzBSBNnWej4D25vdnfMzzJMxGwf9ONK0Zuw6ucWhYnGiIajXoYM2lcf0+4fTZwaMggrWhwMDfVJQYudF96uMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956257; c=relaxed/simple; bh=oes1Zq1kjZJVeEfVMd7tTaCf/godZJPRNpOF8x60M7Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y2x79sTENu55FACEcu4jOGeOn9KXeZqZ52Yt+8mTuQu9v8284oAX7nHVqsq+mLiA9lsfZHJg88JgYCTCnACMOK9LrbXHoS8FkncRtFjVNnz66iYaIRmfsaR1lL6gYiJ0RhEM4mdZ6ycI04EQMPApysXHu/UxNkqi+uFDGF0FKyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZzMsjZUe; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZzMsjZUe" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 76D272D91; Sat, 16 May 2026 11:30:49 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09DDD3F85F; Sat, 16 May 2026 11:30:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956254; bh=oes1Zq1kjZJVeEfVMd7tTaCf/godZJPRNpOF8x60M7Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZzMsjZUeF9Y1iEIsRLrVrIagU7XwyK43VIstkh2KG+3ABw923pUruQwifyGeFF/t6 TPz2TgwwMQhlZarcQX1ZPQKx06U0z2DfxbsU3zRlN0JuKCgLv3puU0HV5t/SrG3N1S B7xc0tXkNsiRhhppG7HQHZMxVCOEByclbF2+kUZc= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 2/9] KVM: arm64: selftests: Add helpers for guest hypervisors Date: Sat, 16 May 2026 19:29:56 +0100 Message-ID: <20260516183003.799058-3-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helpers so that guest hypervisors can run nested guests. SP_EL1 save/restore is added to allow nested guests to use a stack. Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/include/arm64/nested.h | 17 +++++++ tools/testing/selftests/kvm/lib/arm64/entry.S | 5 ++ .../testing/selftests/kvm/lib/arm64/nested.c | 46 +++++++++++++++++++ 3 files changed, 68 insertions(+) diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h index 86d931facacb..30e626e427da 100644 --- a/tools/testing/selftests/kvm/include/arm64/nested.h +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -21,8 +21,17 @@ =20 extern char hyp_vectors[]; =20 +enum vcpu_sysreg { + __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ + + SP_EL1, + + NR_SYS_REGS +}; + struct cpu_context { struct user_pt_regs regs; /* sp =3D sp_el0 */ + u64 sys_regs[NR_SYS_REGS]; }; =20 struct vcpu { @@ -37,9 +46,17 @@ struct hyp_data { struct cpu_context hyp_context; }; =20 +void prepare_hyp(void); +void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top); +int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data); + +void do_hvc(void); u64 __guest_enter(struct vcpu *vcpu, struct cpu_context *hyp_context); void __hyp_exception(u64 type); =20 +void __sysreg_save_el1_state(struct cpu_context *ctxt); +void __sysreg_restore_el1_state(struct cpu_context *ctxt); + #endif /* !__ASSEMBLER__ */ =20 #endif /* SELFTEST_KVM_NESTED_H */ diff --git a/tools/testing/selftests/kvm/lib/arm64/entry.S b/tools/testing/= selftests/kvm/lib/arm64/entry.S index 33bedf5e7fb2..df3af3463c6c 100644 --- a/tools/testing/selftests/kvm/lib/arm64/entry.S +++ b/tools/testing/selftests/kvm/lib/arm64/entry.S @@ -3,6 +3,11 @@ * adapted from arch/arm64/kvm/hyp/entry.S */ =20 + .globl do_hvc + do_hvc: + hvc #0 + ret + /* * Manually define these for now */ diff --git a/tools/testing/selftests/kvm/lib/arm64/nested.c b/tools/testing= /selftests/kvm/lib/arm64/nested.c index 06ddaab2436f..f6c24beb01d0 100644 --- a/tools/testing/selftests/kvm/lib/arm64/nested.c +++ b/tools/testing/selftests/kvm/lib/arm64/nested.c @@ -4,7 +4,53 @@ */ =20 #include "nested.h" +#include "processor.h" #include "test_util.h" +#include + +void prepare_hyp(void) +{ + write_sysreg(HCR_EL2_E2H | HCR_EL2_RW, hcr_el2); + write_sysreg(hyp_vectors, vbar_el2); + isb(); +} + +void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top) +{ + memset(vcpu, 0, sizeof(*vcpu)); + vcpu->context.regs.pc =3D l2_pc; + vcpu->context.regs.pstate =3D PSR_MODE_EL1h | PSR_D_BIT | PSR_A_BIT | PSR= _I_BIT | PSR_F_BIT; + vcpu->context.sys_regs[SP_EL1] =3D l2_stack_top; +} + +void __sysreg_save_el1_state(struct cpu_context *ctxt) +{ + ctxt->sys_regs[SP_EL1] =3D read_sysreg(sp_el1); +} + +void __sysreg_restore_el1_state(struct cpu_context *ctxt) +{ + write_sysreg(ctxt->sys_regs[SP_EL1], sp_el1); +} + +int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data) +{ + u64 ret; + + __sysreg_restore_el1_state(&vcpu->context); + + write_sysreg(vcpu->context.regs.pstate, spsr_el2); + write_sysreg(vcpu->context.regs.pc, elr_el2); + + ret =3D __guest_enter(vcpu, &hyp_data->hyp_context); + + vcpu->context.regs.pc =3D read_sysreg(elr_el2); + vcpu->context.regs.pstate =3D read_sysreg(spsr_el2); + + __sysreg_save_el1_state(&vcpu->context); + + return ret; +} =20 void __hyp_exception(u64 type) { --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36F6B33FE2F; Sat, 16 May 2026 18:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956260; cv=none; b=eIQ92j+jfG+7EzhJE8VS927fhriKYan03XHskm7IWYG4CFsuxOcuO09pgr3iZrfxk1jTs9vVWMNeUp2U0loogMIK36+jjyyLOc5y35gQse7ZPi88oc0gnLLmKZ6Id6aNaHhcAIJdHuAzDkDr/QWOo5qKZNE94XPN+1byAFJs50o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956260; c=relaxed/simple; bh=5dITwd1Xwtsf0FSmhxiGWNKsuOsFRRNYwaEcdnmG+YA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LMgK+5+hXszoOo5/5jSpHMKMSj5kXC1++y6ErDcHYyA7VHGXjJ+9wrIdcQ8KOTm5LQ9RCRLz0n5YqxDgBr7F3loTI6eNB4U/FwVnAb5wnmz9fF4lUrNM4qTMr39pow3wu5nsEOMklMLE0QmpfmJ9CT3N5gr5OMM/EOawKCmN9RQ= ARC-Authentication-Results: i=1; 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t=1778956257; bh=5dITwd1Xwtsf0FSmhxiGWNKsuOsFRRNYwaEcdnmG+YA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FOwnjdBjlESEb170DESQ3X5e+PRe5gxDF0rQ8ZGbNG3VlEnEQV7v8SaQ01z9chRVZ ZmtIiYTmO2di+dG8IwawubT6mzxEY4TnHTS3QygNZ5nPcZmVy4P8b3pcrUiEqHuvpa 0VtpkA7y3SZE/j9Ddv9qDdEeclKdJ5Z55LFh8G1Q= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 3/9] KVM: arm64: selftests: Add hello_nested basic NV selftest Date: Sat, 16 May 2026 19:29:57 +0100 Message-ID: <20260516183003.799058-4-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This selftest simply starts an L1, which starts its own guest (L2). L2 runs without stage-1 and 2 translations, it calls an HVC to jump back to L1. Signed-off-by: Wei-Lin Chang --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/arm64/hello_nested.c | 104 ++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 tools/testing/selftests/kvm/arm64/hello_nested.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 3dc3e39f7025..e8c108e0c487 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -168,6 +168,7 @@ TEST_GEN_PROGS_arm64 +=3D arm64/arch_timer_edge_cases TEST_GEN_PROGS_arm64 +=3D arm64/at TEST_GEN_PROGS_arm64 +=3D arm64/debug-exceptions TEST_GEN_PROGS_arm64 +=3D arm64/hello_el2 +TEST_GEN_PROGS_arm64 +=3D arm64/hello_nested TEST_GEN_PROGS_arm64 +=3D arm64/host_sve TEST_GEN_PROGS_arm64 +=3D arm64/hypercalls TEST_GEN_PROGS_arm64 +=3D arm64/external_aborts diff --git a/tools/testing/selftests/kvm/arm64/hello_nested.c b/tools/testi= ng/selftests/kvm/arm64/hello_nested.c new file mode 100644 index 000000000000..1cab56e4597b --- /dev/null +++ b/tools/testing/selftests/kvm/arm64/hello_nested.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * hello_nested - Go from vEL2 to EL1 then back + */ + +#include "nested.h" +#include "processor.h" +#include "test_util.h" +#include "ucall.h" + +#define XLATE2GPA (0xABCD) +#define L2STACKSZ (0x100) + +/* + * TPIDR_EL2 is used to store vcpu id, so save and restore it. + */ +static gpa_t ucall_translate_to_gpa(void *gva) +{ + gpa_t gpa; + u64 vcpu_id =3D read_sysreg(tpidr_el2); + + GUEST_SYNC2(XLATE2GPA, gva); + + /* get the result from userspace */ + gpa =3D read_sysreg(tpidr_el2); + + write_sysreg(vcpu_id, tpidr_el2); + + return gpa; +} + +static void l2_guest_code(void) +{ + do_hvc(); +} + +static void guest_code(void) +{ + struct vcpu vcpu; + struct hyp_data hyp_data; + int ret; + gpa_t l2_pc, l2_stack_top; + /* force 16-byte alignment for the stack pointer */ + u8 l2_stack[L2STACKSZ] __attribute__((aligned(16))); + + GUEST_ASSERT_EQ(get_current_el(), 2); + GUEST_PRINTF("vEL2 entry\n"); + + l2_pc =3D ucall_translate_to_gpa(l2_guest_code); + l2_stack_top =3D ucall_translate_to_gpa(&l2_stack[L2STACKSZ]); + + init_vcpu(&vcpu, l2_pc, l2_stack_top); + prepare_hyp(); + + ret =3D run_l2(&vcpu, &hyp_data); + GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP); + GUEST_ASSERT_EQ(ESR_ELx_EC(read_sysreg(esr_el2)), ESR_ELx_EC_HVC64); + GUEST_DONE(); +} + +int main(void) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + struct ucall uc; + gpa_t gpa; + + TEST_REQUIRE(kvm_check_cap(KVM_CAP_ARM_EL2)); + vm =3D vm_create(1); + + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); + kvm_arch_vm_finalize_vcpus(vm); + + while (true) { + vcpu_run(vcpu); + + switch (get_ucall(vcpu, &uc)) { + case UCALL_SYNC: + if (uc.args[0] =3D=3D XLATE2GPA) { + gpa =3D addr_gva2gpa(vm, (gva_t)uc.args[1]); + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL2), gpa); + } + break; + case UCALL_PRINTF: + pr_info("%s", uc.buffer); + break; + case UCALL_DONE: + pr_info("DONE!\n"); + goto end; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + fallthrough; + default: + TEST_FAIL("Unhandled ucall: %ld\n", uc.cmd); + } + } + +end: + kvm_vm_free(vm); + return 0; +} --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4A2333446CB; Sat, 16 May 2026 18:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Handle an "add" hypercall in L1 to add 2 numbers passed by L2, and return the result. This better tests our save/restore functionality. Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/arm64/hello_nested.c | 32 ++++++++++++++++++- .../selftests/kvm/include/arm64/nested.h | 2 +- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/hello_nested.c b/tools/testi= ng/selftests/kvm/arm64/hello_nested.c index 1cab56e4597b..9ed5285f5f2d 100644 --- a/tools/testing/selftests/kvm/arm64/hello_nested.c +++ b/tools/testing/selftests/kvm/arm64/hello_nested.c @@ -11,6 +11,10 @@ #define XLATE2GPA (0xABCD) #define L2STACKSZ (0x100) =20 +#define L2SUCCESS (0x0) +#define L2FAILED (0x1) +#define L2ADD (0x2) + /* * TPIDR_EL2 is used to store vcpu id, so save and restore it. */ @@ -31,7 +35,14 @@ static gpa_t ucall_translate_to_gpa(void *gva) =20 static void l2_guest_code(void) { - do_hvc(); + int ans =3D 0; + + ans =3D do_hvc(L2ADD, 2, 3); + + if (ans =3D=3D 5) + do_hvc(L2SUCCESS, 0, 0); + else + do_hvc(L2FAILED, 0, 0); } =20 static void guest_code(void) @@ -42,6 +53,7 @@ static void guest_code(void) gpa_t l2_pc, l2_stack_top; /* force 16-byte alignment for the stack pointer */ u8 l2_stack[L2STACKSZ] __attribute__((aligned(16))); + u64 arg1, arg2; =20 GUEST_ASSERT_EQ(get_current_el(), 2); GUEST_PRINTF("vEL2 entry\n"); @@ -55,6 +67,24 @@ static void guest_code(void) ret =3D run_l2(&vcpu, &hyp_data); GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP); GUEST_ASSERT_EQ(ESR_ELx_EC(read_sysreg(esr_el2)), ESR_ELx_EC_HVC64); + + if (vcpu.context.regs.regs[0] =3D=3D L2ADD) { + arg1 =3D vcpu.context.regs.regs[1]; + arg2 =3D vcpu.context.regs.regs[2]; + GUEST_PRINTF("L2 add request, arg1: %lx, arg2: %lx\n", arg1, arg2); + vcpu.context.regs.regs[0] =3D arg1 + arg2; + } else { + GUEST_FAIL("Unexpected hvc action\n"); + } + + ret =3D run_l2(&vcpu, &hyp_data); + GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP); + GUEST_ASSERT_EQ(ESR_ELx_EC(read_sysreg(esr_el2)), ESR_ELx_EC_HVC64); + + if (vcpu.context.regs.regs[0] !=3D L2SUCCESS) + GUEST_FAIL("L2 failed\n"); + + GUEST_PRINTF("L2 success!\n"); GUEST_DONE(); } =20 diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h index 30e626e427da..c10ef4a85be7 100644 --- a/tools/testing/selftests/kvm/include/arm64/nested.h +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -50,7 +50,7 @@ void prepare_hyp(void); void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top); int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data); =20 -void do_hvc(void); +u64 do_hvc(u64 action, u64 arg1, u64 arg2); u64 __guest_enter(struct vcpu *vcpu, struct cpu_context *hyp_context); void __hyp_exception(u64 type); =20 --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 60E3B405C40; Sat, 16 May 2026 18:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956267; cv=none; b=TTz9vWa7st5Ln+M/3A4cqgITgWr2qbLUAzBKM9TLQ/2KpLDpez7TlhpMLZB9f5qCRLC5LRiFd5EOSF71sC3Lexkl5MF3cdPOq/7849t25wwIYyHR/hzBK7hY9C4ZoNPRYXKQrrtsXd3FFp95UDKCKXMQ/FIc79nqciNbTH4c5hg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956267; c=relaxed/simple; bh=NjiLBvJulETNmJY6cc2tolrFjLCUJdQFnQKrPk5Q/hg=; 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Sat, 16 May 2026 11:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956263; bh=NjiLBvJulETNmJY6cc2tolrFjLCUJdQFnQKrPk5Q/hg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V5hbW2sNxeF4TdF7LOWlkkUOkMt8HpTKd4Fbof8XRzQYpGa+0RqLIAdVpmxwGVc60 ApBJjEWmke0KyERqvE6DzRYOE7seT53kLquSC2SKl17otKShgVwD55+IbwH3rwfWVE hikNAFNwJRAXrp/c1pwEnkGLt/ehLgWvst4Qyeb4= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 5/9] KVM: arm64: selftests: Add shadow_stage2 test Date: Sat, 16 May 2026 19:29:59 +0100 Message-ID: <20260516183003.799058-6-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The shadow_stage2 test is aimed to exercise the shadow page table management code in KVM. In this first patch a basic test similar to hello_nested is created. Right now it doesn't turn on stage-2 for the nested guest (L2) yet, therefore the shadow page table code in KVM will only be triggered minimally now. Signed-off-by: Wei-Lin Chang --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/arm64/shadow_stage2.c | 128 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 tools/testing/selftests/kvm/arm64/shadow_stage2.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index e8c108e0c487..c0fac2ba1339 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -176,6 +176,7 @@ TEST_GEN_PROGS_arm64 +=3D arm64/page_fault_test TEST_GEN_PROGS_arm64 +=3D arm64/psci_test TEST_GEN_PROGS_arm64 +=3D arm64/sea_to_user TEST_GEN_PROGS_arm64 +=3D arm64/set_id_regs +TEST_GEN_PROGS_arm64 +=3D arm64/shadow_stage2 TEST_GEN_PROGS_arm64 +=3D arm64/smccc_filter TEST_GEN_PROGS_arm64 +=3D arm64/vcpu_width_config TEST_GEN_PROGS_arm64 +=3D arm64/vgic_init diff --git a/tools/testing/selftests/kvm/arm64/shadow_stage2.c b/tools/test= ing/selftests/kvm/arm64/shadow_stage2.c new file mode 100644 index 000000000000..cf76a2b0582d --- /dev/null +++ b/tools/testing/selftests/kvm/arm64/shadow_stage2.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * shadow_stage2 - Test correctness of shadow stage 2 + */ + +#include "nested.h" +#include "processor.h" +#include "test_util.h" +#include "ucall.h" + +#define XLATE2GPA (0xABCD) +#define L2STACKSZ (0x100) + +#define L2SUCCESS (0x0) +#define L2FAILED (0x1) +#define L2SYNC (0x2) + +/* + * TPIDR_EL2 is used to store vcpu id, so save and restore it. + */ +static gpa_t ucall_translate_to_gpa(void *gva) +{ + gpa_t gpa; + u64 vcpu_id =3D read_sysreg(tpidr_el2); + + GUEST_SYNC2(XLATE2GPA, gva); + + /* get the result from userspace */ + gpa =3D read_sysreg(tpidr_el2); + + write_sysreg(vcpu_id, tpidr_el2); + + return gpa; +} + +static void l2_guest_code(void) +{ + do_hvc(L2SYNC, 10, 0); + do_hvc(L2SYNC, 20, 0); + do_hvc(L2SYNC, 30, 0); + + do_hvc(L2SUCCESS, 0, 0); +} + +static void guest_code(void) +{ + struct vcpu vcpu; + struct hyp_data hyp_data; + int ret, i =3D 0; + gpa_t l2_pc, l2_stack_top; + /* force 16-byte alignment for the stack pointer */ + u8 l2_stack[L2STACKSZ] __attribute__((aligned(16))); + + GUEST_ASSERT_EQ(get_current_el(), 2); + GUEST_PRINTF("vEL2 entry\n"); + + l2_pc =3D ucall_translate_to_gpa(l2_guest_code); + l2_stack_top =3D ucall_translate_to_gpa(&l2_stack[L2STACKSZ]); + + init_vcpu(&vcpu, l2_pc, l2_stack_top); + prepare_hyp(); + + while (true) { + GUEST_PRINTF("L2 enter\n"); + ret =3D run_l2(&vcpu, &hyp_data); + GUEST_PRINTF("L2 exit\n"); + GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP); + GUEST_ASSERT_EQ(ESR_ELx_EC(read_sysreg(esr_el2)), ESR_ELx_EC_HVC64); + + if (vcpu.context.regs.regs[0] =3D=3D L2SYNC) + GUEST_SYNC3(L2SYNC, i++, vcpu.context.regs.regs[1]); + else + break; + } + + if (vcpu.context.regs.regs[0] !=3D L2SUCCESS) + GUEST_FAIL("L2 failed\n"); + + GUEST_PRINTF("L2 success!\n"); + GUEST_DONE(); +} + +int main(void) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + struct ucall uc; + gpa_t gpa; + + TEST_REQUIRE(kvm_check_cap(KVM_CAP_ARM_EL2)); + vm =3D vm_create(1); + + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); + kvm_arch_vm_finalize_vcpus(vm); + + while (true) { + vcpu_run(vcpu); + + switch (get_ucall(vcpu, &uc)) { + case UCALL_SYNC: + if (uc.args[0] =3D=3D XLATE2GPA) { + gpa =3D addr_gva2gpa(vm, (gva_t)uc.args[1]); + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL2), gpa); + } + if (uc.args[0] =3D=3D L2SYNC) + pr_info("L2SYNC, L1 info: %ld, L2 info: %ld\n", uc.args[1], uc.args[2]= ); + break; + case UCALL_PRINTF: + pr_info("[L1] %s", uc.buffer); + break; + case UCALL_DONE: + pr_info("DONE!\n"); + goto end; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + fallthrough; + default: + TEST_FAIL("Unhandled ucall: %ld\n", uc.cmd); + } + } + +end: + kvm_vm_free(vm); + return 0; +} --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AD344346784; Sat, 16 May 2026 18:31:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956270; cv=none; b=c4Otk7HiMEiA+OheYbrxlyVdyaMRMRM/cpeJEy2mp9EusU/IEpc/6oFB3tTpRjbV2CtIGAmGQHkCIJGboO8rR5Ig8tvkrQ0jE3z+uXBUZOQMS/pVPmQBwOyIrJd+GbR3qKizPxni0/UKlhDHJ1978x4M5tvP+Rqm0Bh0IaG6aYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956270; c=relaxed/simple; bh=jADMEVZuXP3pAMbKzFIdmO4l26Z49yvuX6i+PGRaGSI=; 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Sat, 16 May 2026 11:31:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956266; bh=jADMEVZuXP3pAMbKzFIdmO4l26Z49yvuX6i+PGRaGSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EMtBQNSdsfY93wcLqMuI5+b453PA5kzcOT/rTsqInDh8uabl8rFIATtsowQL62NI9 Wtvcip2D30av12+kf64gPKTyQj/414nurusUCSeb+f0FncU8zzZlwxuyvULAkci6wm C73C1WaSK7A+4LiJnP58PJMMZS9Usa098a5pEUX4= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 6/9] KVM: arm64: selftests: shadow_stage2: Allocate L2 stack from dedicated pool Date: Sat, 16 May 2026 19:30:00 +0100 Message-ID: <20260516183003.799058-7-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of using L1's stack, create a simple page allocator and use that to allocate L2 stack. The allocator will also be used later on when the stage-2 page table generator builds stage-2 mappings for the nested guest (L2). Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/arm64/shadow_stage2.c | 20 ++++++++--- .../selftests/kvm/include/arm64/nested.h | 9 +++++ .../testing/selftests/kvm/lib/arm64/nested.c | 33 +++++++++++++++++++ 3 files changed, 58 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/shadow_stage2.c b/tools/test= ing/selftests/kvm/arm64/shadow_stage2.c index cf76a2b0582d..1ad510a38654 100644 --- a/tools/testing/selftests/kvm/arm64/shadow_stage2.c +++ b/tools/testing/selftests/kvm/arm64/shadow_stage2.c @@ -9,12 +9,16 @@ #include "ucall.h" =20 #define XLATE2GPA (0xABCD) -#define L2STACKSZ (0x100) =20 #define L2SUCCESS (0x0) #define L2FAILED (0x1) #define L2SYNC (0x2) =20 +/* Used for L2 stack and guest S2 page tables. */ +#define L2_PAGE_POOL_ADDR (0x80000000) +#define L2_PAGE_POOL_NPAGES (512) +#define L2_PAGE_POOL_MEMSLOT (0x2) + /* * TPIDR_EL2 is used to store vcpu id, so save and restore it. */ @@ -48,14 +52,18 @@ static void guest_code(void) struct hyp_data hyp_data; int ret, i =3D 0; gpa_t l2_pc, l2_stack_top; - /* force 16-byte alignment for the stack pointer */ - u8 l2_stack[L2STACKSZ] __attribute__((aligned(16))); + struct page_pool pp; =20 GUEST_ASSERT_EQ(get_current_el(), 2); GUEST_PRINTF("vEL2 entry\n"); =20 + pp.start =3D L2_PAGE_POOL_ADDR; + pp.npages =3D L2_PAGE_POOL_NPAGES; + pp.current =3D L2_PAGE_POOL_ADDR; + pp.page_size =3D get_page_size(); + + l2_stack_top =3D alloc_page(&pp) + pp.page_size; l2_pc =3D ucall_translate_to_gpa(l2_guest_code); - l2_stack_top =3D ucall_translate_to_gpa(&l2_stack[L2STACKSZ]); =20 init_vcpu(&vcpu, l2_pc, l2_stack_top); prepare_hyp(); @@ -96,6 +104,10 @@ int main(void) vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); kvm_arch_vm_finalize_vcpus(vm); =20 + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, + L2_PAGE_POOL_ADDR, L2_PAGE_POOL_MEMSLOT, + L2_PAGE_POOL_NPAGES, 0); + while (true) { vcpu_run(vcpu); =20 diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h index c10ef4a85be7..8e7d7738b381 100644 --- a/tools/testing/selftests/kvm/include/arm64/nested.h +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -46,6 +46,15 @@ struct hyp_data { struct cpu_context hyp_context; }; =20 +struct page_pool { + gpa_t start; + gpa_t current; + size_t npages; + size_t page_size; +}; + +size_t get_page_size(void); +gpa_t alloc_page(struct page_pool *pp); void prepare_hyp(void); void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top); int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data); diff --git a/tools/testing/selftests/kvm/lib/arm64/nested.c b/tools/testing= /selftests/kvm/lib/arm64/nested.c index f6c24beb01d0..7f47e340f00d 100644 --- a/tools/testing/selftests/kvm/lib/arm64/nested.c +++ b/tools/testing/selftests/kvm/lib/arm64/nested.c @@ -7,6 +7,39 @@ #include "processor.h" #include "test_util.h" #include +#include + +size_t get_page_size(void) +{ + u64 tcr_el1 =3D read_sysreg(tcr_el1); + u64 tg0 =3D SYS_FIELD_GET(TCR_EL1, TG0, tcr_el1); + + switch (tg0) { + case TCR_EL1_TG0_4K: + return SZ_4K; + case TCR_EL1_TG0_16K: + return SZ_16K; + case TCR_EL1_TG0_64K: + return SZ_64K; + default: + GUEST_FAIL("Unexpected tg0 value!\n"); + return 0; + } +} + +gpa_t alloc_page(struct page_pool *pp) +{ + gpa_t page =3D pp->current; + + pp->current +=3D pp->page_size; + + if ((pp->current - pp->start) / pp->page_size <=3D pp->npages) { + return page; + } else { + GUEST_FAIL("%s failed!\n", __func__); + return 0; + } +} =20 void prepare_hyp(void) { --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 83D0F3451D6; Sat, 16 May 2026 18:31:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956272; cv=none; b=RB4SAeb3Q9NYhl770e06VXoviM0QX8MMOfkF8DkFMqwzVWZ8QQSQVEI1NJTpCNnxYwROErC+GszvJoGdySd9wteIYfBzlNNnEwOfPkjrKzaERq6JC8rDy1/NERppf4d7CfRO19BkO6HV0ZAeqfgaasnnU/7jmGOLB/eobFMh0F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956272; c=relaxed/simple; bh=waACEwaOCU9Q56/CgdQoWvYngZ8Q6B/c8GIndLVbAcQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Sat, 16 May 2026 11:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956269; bh=waACEwaOCU9Q56/CgdQoWvYngZ8Q6B/c8GIndLVbAcQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sKa08AsosCe81z3+QYLy0GKotDrI/oTc9yFQYA2Qcwvib+5EX/jkNhQoyOe+D0VM7 9X6BjsHACpnmO+kQL9qjViOAQZLBVxNVL011lFr/tNqddm77JgVUNmiKvAmpZMVR0p yFoVIuP4YtbbcCTjUa0QMp3Skyq/pxxJI+y68qfY= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 7/9] KVM: arm64: selftests: shadow_stage2: Check supported stage-2 granule size Date: Sat, 16 May 2026 19:30:01 +0100 Message-ID: <20260516183003.799058-8-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When selecting a granule size for stage-2, the supported stage-2 granule size must be checked. Add the check. For simplicity, we check whether the guest stage-1 granule size is supported for stage-2, and skip the test otherwise. Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/arm64/shadow_stage2.c | 8 +++++ .../selftests/kvm/include/arm64/nested.h | 1 + .../testing/selftests/kvm/lib/arm64/nested.c | 30 +++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/shadow_stage2.c b/tools/test= ing/selftests/kvm/arm64/shadow_stage2.c index 1ad510a38654..c5332b8b5683 100644 --- a/tools/testing/selftests/kvm/arm64/shadow_stage2.c +++ b/tools/testing/selftests/kvm/arm64/shadow_stage2.c @@ -14,6 +14,8 @@ #define L2FAILED (0x1) #define L2SYNC (0x2) =20 +#define TGRAN2NOSUP (0x3) + /* Used for L2 stack and guest S2 page tables. */ #define L2_PAGE_POOL_ADDR (0x80000000) #define L2_PAGE_POOL_NPAGES (512) @@ -53,6 +55,7 @@ static void guest_code(void) int ret, i =3D 0; gpa_t l2_pc, l2_stack_top; struct page_pool pp; + u64 mmfr0 =3D read_sysreg(id_aa64mmfr0_el1); =20 GUEST_ASSERT_EQ(get_current_el(), 2); GUEST_PRINTF("vEL2 entry\n"); @@ -62,6 +65,9 @@ static void guest_code(void) pp.current =3D L2_PAGE_POOL_ADDR; pp.page_size =3D get_page_size(); =20 + if (!has_tgran_2(mmfr0, pp.page_size)) + GUEST_SYNC1(TGRAN2NOSUP); + l2_stack_top =3D alloc_page(&pp) + pp.page_size; l2_pc =3D ucall_translate_to_gpa(l2_guest_code); =20 @@ -119,6 +125,8 @@ int main(void) } if (uc.args[0] =3D=3D L2SYNC) pr_info("L2SYNC, L1 info: %ld, L2 info: %ld\n", uc.args[1], uc.args[2]= ); + if (uc.args[0] =3D=3D TGRAN2NOSUP) + ksft_exit_skip("Guest page size not supported as guest stage-2 page si= ze!\n"); break; case UCALL_PRINTF: pr_info("[L1] %s", uc.buffer); diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h index 8e7d7738b381..fc59fabff12d 100644 --- a/tools/testing/selftests/kvm/include/arm64/nested.h +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -55,6 +55,7 @@ struct page_pool { =20 size_t get_page_size(void); gpa_t alloc_page(struct page_pool *pp); +bool has_tgran_2(u64 mmfr0, size_t size); void prepare_hyp(void); void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top); int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data); diff --git a/tools/testing/selftests/kvm/lib/arm64/nested.c b/tools/testing= /selftests/kvm/lib/arm64/nested.c index 7f47e340f00d..cda41f355263 100644 --- a/tools/testing/selftests/kvm/lib/arm64/nested.c +++ b/tools/testing/selftests/kvm/lib/arm64/nested.c @@ -9,6 +9,36 @@ #include #include =20 +#define _has_tgran_2(__r, __sz) \ + ({ \ + u64 _s1, _s2, _mmfr0 =3D __r; \ + \ + _s2 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ + TGRAN##__sz##_2, _mmfr0); \ + \ + _s1 =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, \ + TGRAN##__sz, _mmfr0); \ + \ + ((_s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_NI && \ + _s2 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz) || \ + (_s2 =3D=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz && \ + _s1 !=3D ID_AA64MMFR0_EL1_TGRAN##__sz##_NI)); \ + }) + +bool has_tgran_2(u64 mmfr0, size_t size) +{ + switch (size) { + case SZ_4K: + return _has_tgran_2(mmfr0, 4); + case SZ_16K: + return _has_tgran_2(mmfr0, 16); + case SZ_64K: + return _has_tgran_2(mmfr0, 64); + default: + return false; + } +} + size_t get_page_size(void) { u64 tcr_el1 =3D read_sysreg(tcr_el1); --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5FC01344031; Sat, 16 May 2026 18:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956283; cv=none; b=L86WEX+UjijV3qtyEVBqTm+kND96ciN/5lGMIU737TPSrRI/x1xgOih/SCna5vsyHuh4549+jONfx9ytrz0YCfKoMgVsD0UEzldQMnPLPATzR7VL7eT904S4jXqgWq++OILuS1bIS1L95juuOZ6A7+CHXZe+tftJIn9f0hUA/Es= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956283; c=relaxed/simple; bh=fwVDg016m7eeWy4bYy16DTCCBEBDMvvZImnp5Carqqo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CCk9RRgaYm1SUOYQuA7Sa+bMalU6ZX5anbovslYvB5DO9aH3XMJ1RNz+AQx2qVTYEglCMSzCr74/lLv859LuJ8zlbxssP3Uv1fo34vMNpK2qAst0OWs9vTqNkN6v8D/sRo70GUJ/4urbw9KqnIXqWTMc6fOZB09xIcbo1iCIWyM= ARC-Authentication-Results: i=1; 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t=1778956272; bh=fwVDg016m7eeWy4bYy16DTCCBEBDMvvZImnp5Carqqo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LN2kdcYCpJYQSQAIS40HNiC08siLiOrQMYbk5r3oYmosomJZmIEPjxJgCzmKmE4pg +ljrjPYwPbeXyZCI9SOjfEfg45magdrdOyI6LQwM6o0Z/JmHC6CEcGWUfXiyZgCC5f aGetGu8f9AwluRkR//12eMufmZeaKGfSNGazQHHE= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 8/9] KVM: arm64: selftests: Add infrastructure for using stage-2 in guest Date: Sat, 16 May 2026 19:30:02 +0100 Message-ID: <20260516183003.799058-9-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a stage-2 page table generator, the s2_mmu structure, and vEL2 stage-2 preparation code for a guest hypervisor to turn on stage-2 translation for its nested guest. Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/arm64/hello_nested.c | 2 +- .../selftests/kvm/arm64/shadow_stage2.c | 2 +- .../selftests/kvm/include/arm64/nested.h | 15 +- .../testing/selftests/kvm/lib/arm64/nested.c | 145 +++++++++++++++++- 4 files changed, 160 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/hello_nested.c b/tools/testi= ng/selftests/kvm/arm64/hello_nested.c index 9ed5285f5f2d..b57e41c73214 100644 --- a/tools/testing/selftests/kvm/arm64/hello_nested.c +++ b/tools/testing/selftests/kvm/arm64/hello_nested.c @@ -62,7 +62,7 @@ static void guest_code(void) l2_stack_top =3D ucall_translate_to_gpa(&l2_stack[L2STACKSZ]); =20 init_vcpu(&vcpu, l2_pc, l2_stack_top); - prepare_hyp(); + prepare_hyp_no_s2(); =20 ret =3D run_l2(&vcpu, &hyp_data); GUEST_ASSERT_EQ(ret, ARM_EXCEPTION_TRAP); diff --git a/tools/testing/selftests/kvm/arm64/shadow_stage2.c b/tools/test= ing/selftests/kvm/arm64/shadow_stage2.c index c5332b8b5683..2b274b810dcf 100644 --- a/tools/testing/selftests/kvm/arm64/shadow_stage2.c +++ b/tools/testing/selftests/kvm/arm64/shadow_stage2.c @@ -72,7 +72,7 @@ static void guest_code(void) l2_pc =3D ucall_translate_to_gpa(l2_guest_code); =20 init_vcpu(&vcpu, l2_pc, l2_stack_top); - prepare_hyp(); + prepare_hyp_no_s2(); =20 while (true) { GUEST_PRINTF("L2 enter\n"); diff --git a/tools/testing/selftests/kvm/include/arm64/nested.h b/tools/tes= ting/selftests/kvm/include/arm64/nested.h index fc59fabff12d..1bcbb31b8d67 100644 --- a/tools/testing/selftests/kvm/include/arm64/nested.h +++ b/tools/testing/selftests/kvm/include/arm64/nested.h @@ -38,6 +38,14 @@ struct vcpu { struct cpu_context context; }; =20 +struct s2_mmu { + gpa_t pgd; + unsigned int vmid; + unsigned int page_size_shift; + u64 vtcr; + u64 ipa_bits; +}; + /* * KVM has host_data and hyp_context, combine them because we're only doing * hyp context. @@ -56,8 +64,13 @@ struct page_pool { size_t get_page_size(void); gpa_t alloc_page(struct page_pool *pp); bool has_tgran_2(u64 mmfr0, size_t size); -void prepare_hyp(void); +void prepare_hyp_no_s2(void); +void prepare_hyp(struct s2_mmu *mmu); void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top); +void create_s2_mapping(struct s2_mmu *mmu, u64 ipa, u64 pa, size_t size, + struct page_pool *pp); +void init_s2_mmu(struct s2_mmu *mmu, unsigned int vmid, gpa_t pgd, + size_t page_size, u64 ipa_bits); int run_l2(struct vcpu *vcpu, struct hyp_data *hyp_data); =20 u64 do_hvc(u64 action, u64 arg1, u64 arg2); diff --git a/tools/testing/selftests/kvm/lib/arm64/nested.c b/tools/testing= /selftests/kvm/lib/arm64/nested.c index cda41f355263..9848d607ef64 100644 --- a/tools/testing/selftests/kvm/lib/arm64/nested.c +++ b/tools/testing/selftests/kvm/lib/arm64/nested.c @@ -71,13 +71,22 @@ gpa_t alloc_page(struct page_pool *pp) } } =20 -void prepare_hyp(void) +void prepare_hyp_no_s2(void) { write_sysreg(HCR_EL2_E2H | HCR_EL2_RW, hcr_el2); write_sysreg(hyp_vectors, vbar_el2); isb(); } =20 +void prepare_hyp(struct s2_mmu *mmu) +{ + write_sysreg(mmu->vtcr, vtcr_el2); + write_sysreg(mmu->pgd | ((u64)mmu->vmid << 48), vttbr_el2); + write_sysreg(HCR_EL2_E2H | HCR_EL2_RW | HCR_EL2_VM, hcr_el2); + write_sysreg(hyp_vectors, vbar_el2); + isb(); +} + void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2_stack_top) { memset(vcpu, 0, sizeof(*vcpu)); @@ -86,6 +95,140 @@ void init_vcpu(struct vcpu *vcpu, gpa_t l2_pc, gpa_t l2= _stack_top) vcpu->context.sys_regs[SP_EL1] =3D l2_stack_top; } =20 +static int stage2_levels(unsigned int page_size_shift, u64 ipa_bits) +{ + /* taken from ARM64_HW_PGTABLE_LEVELS(ipa) in KVM */ + return (ipa_bits - 4) / (page_size_shift - 3); +} + +static u64 get_index(struct s2_mmu *mmu, u64 ipa, int level) +{ + int width =3D mmu->page_size_shift - 3; + int shift_amount =3D mmu->page_size_shift + (3 - level) * width; + + return (ipa >> shift_amount) & GENMASK_ULL(width - 1, 0); +} + +static u64 pte_gpa_to_gva(u64 gpa) +{ + /* + * This depends on how the memory used for s2pt is mapped in GVA, + * currently it is assumed they are idmapped. + */ + return gpa; +} + +static u64 pte_to_pt_base(u64 pte) +{ + return pte & GENMASK_ULL(47, 12); +} + +#define S2_PTE_AF (1ULL << 10) +#define S2_PTE_SH_INNER (3ULL << 8) +#define S2_PTE_S2AP_RW (3ULL << 6) +#define S2_PTE_ATTR_NORMAL_WB (0xfULL << 2) +#define S2_PTE_TYPE_TABLE (1ULL << 1) +#define S2_PTE_TYPE_PAGE (1ULL << 1) +#define S2_PTE_VALID 1ULL + +/* No block mappings for now. */ +static void create_one_s2_mapping(struct s2_mmu *mmu, u64 ipa, u64 pa, + struct page_pool *pp) +{ + int levels =3D stage2_levels(mmu->page_size_shift, mmu->ipa_bits); + u64 index, pte, pte_new, table_attr, page_attr; + gpa_t pte_addr, pt_base =3D mmu->pgd; + + table_attr =3D S2_PTE_TYPE_TABLE | S2_PTE_VALID; + page_attr =3D S2_PTE_AF | S2_PTE_SH_INNER | S2_PTE_S2AP_RW | + S2_PTE_ATTR_NORMAL_WB | S2_PTE_TYPE_PAGE | S2_PTE_VALID; + + for (int level =3D 4 - levels; level <=3D 3; level++) { + index =3D get_index(mmu, ipa, level); + pte_addr =3D pt_base + index * 8; + pte =3D *((u64 *)pte_gpa_to_gva(pte_addr)); + + if (level =3D=3D 3) { + /* Last level, install leaf entry. */ + pte_new =3D pa & ~GENMASK_ULL(mmu->page_size_shift - 1, 0); + pte_new |=3D page_attr; + *((u64 *)pte_gpa_to_gva(pte_addr)) =3D pte_new; + } else if (!(pte & S2_PTE_VALID)) { + /* Empty next level table, allocate and install. */ + pte_new =3D alloc_page(pp); + pte_new |=3D table_attr; + *((u64 *)pte_gpa_to_gva(pte_addr)) =3D pte_new; + pt_base =3D pte_to_pt_base(pte_new); + } else { + /* Next level table found, descend into it. */ + pt_base =3D pte_to_pt_base(pte); + } + } +} + +void create_s2_mapping(struct s2_mmu *mmu, u64 ipa, u64 pa, size_t size, + struct page_pool *pp) +{ + u64 ipa_end; + u64 mask =3D pp->page_size - 1; + + ipa_end =3D (ipa + size + mask) & ~mask; + ipa &=3D ~mask; + pa &=3D ~mask; + + while (ipa < ipa_end) { + create_one_s2_mapping(mmu, ipa, pa, pp); + pa +=3D pp->page_size; + ipa +=3D pp->page_size; + } + dsb(ishst); +} + +void init_s2_mmu(struct s2_mmu *mmu, unsigned int vmid, gpa_t pgd, + size_t page_size, u64 ipa_bits) +{ + u64 ps, tg0, sl0_base, mmfr0 =3D read_sysreg(id_aa64mmfr0_el1); + int levels; + + mmu->vmid =3D vmid; + mmu->pgd =3D pgd; + mmu->ipa_bits =3D ipa_bits; + mmu->vtcr =3D 0; + + switch (page_size) { + case SZ_4K: + tg0 =3D VTCR_EL2_TG0_4K; + mmu->page_size_shift =3D 12; + sl0_base =3D 2; + break; + case SZ_16K: + tg0 =3D VTCR_EL2_TG0_16K; + mmu->page_size_shift =3D 14; + sl0_base =3D 3; + break; + case SZ_64K: + default: + tg0 =3D VTCR_EL2_TG0_64K; + mmu->page_size_shift =3D 16; + sl0_base =3D 3; + break; + } + + levels =3D stage2_levels(mmu->page_size_shift, mmu->ipa_bits); + mmu->vtcr |=3D FIELD_PREP(VTCR_EL2_SL0, (sl0_base - (4 - levels))); + + ps =3D SYS_FIELD_GET(ID_AA64MMFR0_EL1, PARANGE, mmfr0); + /* cap ps to 48-bit */ + ps =3D ps > 0b0101 ? 0b0101 : ps; + mmu->vtcr |=3D VTCR_EL2_RES1 | SYS_FIELD_PREP(VTCR_EL2, PS, ps) = | + SYS_FIELD_PREP(VTCR_EL2, TG0, tg0) | + SYS_FIELD_PREP_ENUM(VTCR_EL2, SH0, INNER) | + SYS_FIELD_PREP_ENUM(VTCR_EL2, ORGN0, WBWA) | + SYS_FIELD_PREP_ENUM(VTCR_EL2, IRGN0, WBWA); + + mmu->vtcr |=3D FIELD_PREP(VTCR_EL2_T0SZ, 64 - ipa_bits); +} + void __sysreg_save_el1_state(struct cpu_context *ctxt) { ctxt->sys_regs[SP_EL1] =3D read_sysreg(sp_el1); --=20 2.43.0 From nobody Mon May 25 08:11:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 489CE33CEA9; Sat, 16 May 2026 18:31:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778956283; cv=none; b=gaU0vVbDBaQt4Spr3E1uQIOLwd8WbBVRj50C6mRWVQ61JwJUntX8VKEsKhmypWIhocZJ6EJKtI+h6Pc2n1zlBBsl2R+BU/j1krDZsd0E9wZNrEQdKkkL+KeT3MNa9qQvf17SuYfcMdOrc/VgfkDv+lnDumEy9TPcbxWAUQcTSZ8= ARC-Message-Signature: i=1; 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Sat, 16 May 2026 11:31:10 -0700 (PDT) Received: from workstation-e142269.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 24C233F85F; Sat, 16 May 2026 11:31:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778956275; bh=/1t/CERV4WJKmLTkfx/AdC8xUY2k0LviAytjvvkIoEI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qpRjr816bPDh6feC6wJMq4ZIT5RzIoLJmWRlzCn5rCnXmoTiF3bHGGE1C5XSnJc7Q VjYxy9b7Uts/utZxVgpD6SKJNwAU6vibvirdlm9ieO0R71PaivSFzOxTjBQeAyOv0i RLlH90CDHQA/7p5jNQ6H7s9GkpJ+9Z12pLK0DLbo= From: Wei-Lin Chang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Cc: Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Itaru Kitayama , Wei-Lin Chang Subject: [PATCH v3 9/9] KVM: arm64: selftests: shadow_stage2: Turn on stage-2 translation for the nested guest Date: Sat, 16 May 2026 19:30:03 +0100 Message-ID: <20260516183003.799058-10-weilin.chang@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260516183003.799058-1-weilin.chang@arm.com> References: <20260516183003.799058-1-weilin.chang@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Utilize the stage-2 library functions to initialize a s2_mmu, build a stage-2 page table, and turn on stage-2 translation for the nested guest. This better tests out the shadow page table code in KVM. Signed-off-by: Wei-Lin Chang --- .../selftests/kvm/arm64/shadow_stage2.c | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/shadow_stage2.c b/tools/test= ing/selftests/kvm/arm64/shadow_stage2.c index 2b274b810dcf..5bce55abdea7 100644 --- a/tools/testing/selftests/kvm/arm64/shadow_stage2.c +++ b/tools/testing/selftests/kvm/arm64/shadow_stage2.c @@ -51,9 +51,11 @@ static void l2_guest_code(void) static void guest_code(void) { struct vcpu vcpu; + struct s2_mmu mmu; struct hyp_data hyp_data; int ret, i =3D 0; - gpa_t l2_pc, l2_stack_top; + gpa_t l2_pc, l2_stack_start, l2_stack_top, s2_pgd; + gpa_t do_hvc_gpa; struct page_pool pp; u64 mmfr0 =3D read_sysreg(id_aa64mmfr0_el1); =20 @@ -68,11 +70,20 @@ static void guest_code(void) if (!has_tgran_2(mmfr0, pp.page_size)) GUEST_SYNC1(TGRAN2NOSUP); =20 - l2_stack_top =3D alloc_page(&pp) + pp.page_size; + l2_stack_start =3D alloc_page(&pp); + l2_stack_top =3D l2_stack_start + pp.page_size; l2_pc =3D ucall_translate_to_gpa(l2_guest_code); + do_hvc_gpa =3D ucall_translate_to_gpa(do_hvc); + + s2_pgd =3D alloc_page(&pp); =20 init_vcpu(&vcpu, l2_pc, l2_stack_top); - prepare_hyp_no_s2(); + init_s2_mmu(&mmu, 0, s2_pgd, pp.page_size, 40); + create_s2_mapping(&mmu, l2_pc, l2_pc, pp.page_size * 2, &pp); + create_s2_mapping(&mmu, do_hvc_gpa, do_hvc_gpa, pp.page_size, &pp); + create_s2_mapping(&mmu, l2_stack_start, l2_stack_start, pp.page_size, &pp= ); + + prepare_hyp(&mmu); =20 while (true) { GUEST_PRINTF("L2 enter\n"); @@ -113,6 +124,12 @@ int main(void) vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, L2_PAGE_POOL_ADDR, L2_PAGE_POOL_MEMSLOT, L2_PAGE_POOL_NPAGES, 0); + /* + * This idmap allows L1 to traverse and build its guest stage-2, where + * it must do a PA to VA conversion in order to descend to the next + * level. + */ + virt_map(vm, L2_PAGE_POOL_ADDR, L2_PAGE_POOL_ADDR, L2_PAGE_POOL_NPAGES); =20 while (true) { vcpu_run(vcpu); --=20 2.43.0