From nobody Fri Jun 12 11:37:53 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2B50E423A89 for ; Fri, 15 May 2026 08:58:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778835521; cv=none; b=sdjMkLS0ov2FbgGee4zWn0ITzFY0NR0NJCh+mgQitQqXZD0jtTrNdKUzg8BJPo8XGjf/IlSU/17jRK+Jh4/1mewWDL0rRKkpWOGmvHBo7JC+o+T4RLLgLvd20yJ96ctf3QoeORSbzTbcffDd1VQZDsu7wmBzMJkExYniIM0UDWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778835521; c=relaxed/simple; bh=Xf1MKewX1qHIoEYl7yF7sCbi2Zzhjv/ESbywRaQiUYw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=GJcT+Tef+j/FF6WfMHz/N8hrb21HdAPOBqew3xIzqUG1oE5AKHzTH7aajzDIsR7L7W4KVs7D6AgUAmP8aEh9VGPqVDXpSYSxbowXztkSraBQCTnokie64oUhCOuWEPa4DDhbOmCdmxO4LA7ClDVwI86TSpJU1JmZFiNtJEZPbQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=PicMm3+e; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="PicMm3+e" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 91E1D26A4; Fri, 15 May 2026 01:58:31 -0700 (PDT) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5C16B3FAF5; Fri, 15 May 2026 01:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778835516; bh=Xf1MKewX1qHIoEYl7yF7sCbi2Zzhjv/ESbywRaQiUYw=; h=From:To:Cc:Subject:Date:From; b=PicMm3+eRwPFO1YojcuvsED2Q2H66VvtbZEw0e4P8BxfibmSmAXfMRYdmPuFiDHET dz107WYMOKzfN+x554qVUwCMR3UEonMX0gWc58O8a4WGoZLMNJyL87+kRA6TvoUjx4 BfRG1sEGGJnKkYri08g6HHPtYrvSacLDe3bf3fZw= From: Ben Horgan To: ben.horgan@arm.com Cc: james.morse@arm.com, reinette.chatre@intel.com, fenghuay@nvidia.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm_mpam: Fix software reset values of MPAMCFG_PRI Date: Fri, 15 May 2026 09:58:25 +0100 Message-ID: <20260515085825.1157812-1-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Priority partitioning is not supported other than to set the per-PARTID defaults in MPAMCFG_PRI, INTPRI and DSPRI, to the highest priority. When 0 is the lowest priority, all ones is the highest priority. However, these values are calculated with an extra higher bit set. Luckily, there is still no chance of setting functional bits incorrectly. When the priority widths are maximal, this is ensured as the fields have width 16 and a u16 holds the value for each field. When the widths are smaller, the higher order bits beyond the advertised widths, MPAMF_PRI_IDR.DSPRI_WD and MPAMF_PRI_IDR.INTPRI_WD, in the priority fields INTPRI and DSPRI are not used to calculate the priority. It is not specified whether these higher order bits are RAZ/WI or Res0 and so it is desirable not to set them to avoid the chance of misleading reads. Correct the priority reset values. Fixes: 880df85d8673 ("arm_mpam: Probe and reset the rest of the features") Signed-off-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 41b14344b16f..a627dc2c53de 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1539,12 +1539,9 @@ static u16 mpam_wa_t241_calc_min_from_max(struct mpa= m_props *props, static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid, struct mpam_config *cfg) { - u32 pri_val =3D 0; u16 cmax =3D MPAMCFG_CMAX_CMAX; struct mpam_msc *msc =3D ris->vmsc->msc; struct mpam_props *rprops =3D &ris->props; - u16 dspri =3D GENMASK(rprops->dspri_wd, 0); - u16 intpri =3D GENMASK(rprops->intpri_wd, 0); =20 mutex_lock(&msc->part_sel_lock); __mpam_part_sel(ris->ris_idx, partid, msc); @@ -1609,16 +1606,25 @@ static void mpam_reprogram_ris_partid(struct mpam_m= sc_ris *ris, u16 partid, =20 if (mpam_has_feature(mpam_feat_intpri_part, rprops) || mpam_has_feature(mpam_feat_dspri_part, rprops)) { - /* aces high? */ - if (!mpam_has_feature(mpam_feat_intpri_part_0_low, rprops)) - intpri =3D 0; - if (!mpam_has_feature(mpam_feat_dspri_part_0_low, rprops)) - dspri =3D 0; + u32 pri_val =3D 0; + + if (mpam_has_feature(mpam_feat_intpri_part, rprops)) { + u16 intpri =3D GENMASK(rprops->intpri_wd - 1, 0); + + /* aces high? */ + if (!mpam_has_feature(mpam_feat_intpri_part_0_low, rprops)) + intpri =3D 0; =20 - if (mpam_has_feature(mpam_feat_intpri_part, rprops)) pri_val |=3D FIELD_PREP(MPAMCFG_PRI_INTPRI, intpri); - if (mpam_has_feature(mpam_feat_dspri_part, rprops)) + } + if (mpam_has_feature(mpam_feat_dspri_part, rprops)) { + u16 dspri =3D GENMASK(rprops->dspri_wd - 1, 0); + + if (!mpam_has_feature(mpam_feat_dspri_part_0_low, rprops)) + dspri =3D 0; + pri_val |=3D FIELD_PREP(MPAMCFG_PRI_DSPRI, dspri); + } =20 mpam_write_partsel_reg(msc, PRI, pri_val); } --=20 2.43.0