From nobody Fri Jun 12 12:44:29 2026 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E6663F7AA5 for ; Fri, 15 May 2026 07:58:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831920; cv=none; b=akgAG91oI2qi301ac7YpYLTporw/sB89rN5gDKtD1K4lkqdk+W08ybhayf9iPifmarYBInjVykS81lURxrug9j2q2DLA2R2rzmHtkLyKpL0F1GYBAYIim/khX/b3RBZVRKL1+HlLxNRZdFDiR9xkaI13+bVWFF+lCEh1X6t+GVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831920; c=relaxed/simple; bh=b66pnBT8a97F3xfRqp9174x/oLh8WkkmAfQefImwv9s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PXTOWfKvNPpn8ORaWbGdZDX7HABEHMo71aNoGviYeiBjJaeu2fobEjhmkV/Y6Y0/y99Sz/1THxDOHOlgxVzqpYp75qJySD3lKVc274Lct5ra75dzNuLX76k8DF05WCphm2ifHGUchyXmWL93kfP6tCj/lmTnT5TSY1qhhw3ajm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iHxDHimO; arc=none smtp.client-ip=209.85.216.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iHxDHimO" Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-366070f71adso8169409a91.2 for ; Fri, 15 May 2026 00:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778831916; x=1779436716; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cl4rPiyhUQMqgrmFZmcx0RjrEneUBteFh/YjQtcvgsc=; b=iHxDHimO4F/jZsyQ0fCITL1FsMwozJ/HmEYV2Fhcd/k42IJJTTpv9XAzMpJFSX9k+6 WmUrEwiDZt5i2tyMDPLa7xIIwAOzDqLTZKWJ9gq5CB6AVJHLZoN9L4DDD2GYy99ixtDL TBcqe3ujy4i+F4fAG+gzbTNJ25otwD2YzD85SDCCmTLgmW8Oky7jCsXO1wFV9rxTlkfn IChFzzrGzv963+BkaxWRxgl9wgRAfVqMwDfFB/J4zgUSQ0N+2CNqXOSlH6hFxEMca69V xxLYNM+6sdXEQQL2ce+xU2NKBJ7mc7eUD8E7IC2vBMl8WUCbibc28uiRRwuzP21k+gw6 QaWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778831916; x=1779436716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=cl4rPiyhUQMqgrmFZmcx0RjrEneUBteFh/YjQtcvgsc=; b=UywiPiIjfQEoAVEllTiPkJ9YM/DwCLcn+LIZ2ytYjhUuaYbna55V9BhJBj7K6u0OyN 1aT9NpOcvblc14XUkfxw9uvl5yTm0bwEx2lsSkHu7t6/wtyCRtT9NjpK8zHsBI9xvZac 0UKrmLbrPEOLtBh1O+e7pUMWBVyABk4bl30h/37K7rxjlzYGIxxX6ITiUyqVwfWsiDmF NK/Ei0cXspdPu9Blys9Vd4U4GCHe5uA3zkCnKHmlQDby/eWBqAONco9ED2bn3tGsSNY2 1552pqfLYvvS5DvGu0fVZUQgoMvqgJsFpkRfdQnzFWBcNRgWHz4ookemhoP49RNeJhPB IINQ== X-Forwarded-Encrypted: i=1; AFNElJ/WXFnfxtj3KMAx/0QzI5ENyF7kwruCSN5eW9TxsRNMdukYVC7jNn7dkR3xsF9zno2Hyoj1MM1856qo8hQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yzazx3G0uTE2iiygINAwyazeInKcU2PMCPkNVLxfAHzyJ9X0cod WcYRO8lnRTN5GHKI7VcJjmatyBdafoE4ogRcyF8NL92CHt1uHF1zpzC6qmkRWD6y8XM= X-Gm-Gg: Acq92OHBNyUpdiGB6Sewcqm+dyELZwAQZBKcekGgsc9rYtonUlghWZluotsdO5M7sPg e+/EAcgyHs0YXapCfnK+0BsQmlAmsirWSu5SnZ05JIKubBNRFS9dV1aZSE1PyfhxSsEukxYp3uZ m8rX+bMVXwzAr0V7Z1LEe/o3g4gy/ojSc8IOwH/ls6XaxwrH93SEUPct9zYb+iu2jgfloG4ulsk yOD0bdu4RmgmAtDw6SIh0F9oewI8Vo1asCeBjprjnd8FqfnzHRlQhHeGPVZijeoigV60blQ0H4p pASGdWzaFlB1Q+i2h+b8gmbsNRffRNqotOZ5A55jSC2ba2s3uWSj2Qu0cT8job2SCJWcSJNALk7 lM+shTxdxvso8DdPBbiUihUmdyk+ccCes7OPLYwCHIh/7mMRAj/gk52dOfZHOY14/NAhEuElirl N7rgZlM6nL0/ePnVs4JSSdEkNtFD4+8VFDy9zZmvYFUHrCDYy9ojQ= X-Received: by 2002:a17:90b:57c7:b0:365:7e4d:bcb8 with SMTP id 98e67ed59e1d1-369519cdb59mr2843557a91.1.1778831916312; Fri, 15 May 2026 00:58:36 -0700 (PDT) Received: from localhost.localdomain ([2405:201:d008:80b:a00:27ff:feb6:42dd]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36959c7eacesm542040a91.2.2026.05.15.00.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2026 00:58:35 -0700 (PDT) From: Pramod Maurya To: jic23@kernel.org Cc: lars@metafoo.de, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pramod.nexgen@gmail.com Subject: [PATCH v4 1/3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema Date: Fri, 15 May 2026 03:57:34 -0400 Message-ID: <20260515075736.172172-2-pramod.nexgen@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260515075736.172172-1-pramod.nexgen@gmail.com> References: <20260510083219.70224-1-pramod.nexgen@gmail.com> <20260515075736.172172-1-pramod.nexgen@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Xilinx XADC and UltraScale System Monitor device tree binding from the legacy plain-text format to a YAML schema, enabling automated validation with dt-schema. The new binding covers the same hardware and compatible strings: - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro) - xlnx,axi-xadc-1.00.a (AXI softmacro) - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard) The xlnx,channels subnode retains its legacy name (including the comma) for backwards compatibility with existing device trees. Place xlnx,channels under properties: now that dt-schema PR#195 allows comma-containing nodenames for long-established bindings. Fix reg constraints inside channel subnodes to use maxItems and an items block rather than bare minimum/maximum keywords which are silently ignored on array types. Remove the redundant type: boolean from xlnx,bipolar since the $ref to /schemas/types.yaml#/definitions/flag already implies it. Signed-off-by: Pramod Maurya --- Changes in v4: - Move xlnx,channels from patternProperties: to properties: per Rob Herring's guidance (keywords.yaml: "Fixed strings belong in properties") This requires a companion dt-schema update to add xlnx,channels as an object-type exception in vendor-props.yaml (like adi,channels). - Fix reg constraints inside channel subnodes: remove items block with minimum/maximum which is invalid for cell arrays per cell.yaml; the valid channel range (0-16) is documented in the description instead. - Remove redundant type: boolean from xlnx,bipolar; the $ref to /schemas/types.yaml#/definitions/flag already implies boolean type. - Fix patternProperties regex for channel subnodes to "^channel@([0-9a-f]|1= 0)$" covering all valid hex unit addresses for channels 0-16. Changes in v3: - Move xlnx,channels from properties: to patternProperties: to satisfy vendor-props.yaml meta-schema (reversed in v4, see above) Changes in v2: - Fix patternProperties regex to use lowercase hex unit addresses - Add allOf/if/then conditional requiring xlnx,external-mux-channel when xlnx,external-mux is "single" or "dual" .../bindings/iio/adc/xilinx-xadc.txt | 141 ------------ .../bindings/iio/adc/xlnx,xadc.yaml | 210 ++++++++++++++++++ MAINTAINERS | 7 + 3 files changed, 217 insertions(+), 141 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.t= xt create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Do= cumentation/devicetree/bindings/iio/adc/xilinx-xadc.txt deleted file mode 100644 index f42e18078376..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt +++ /dev/null @@ -1,141 +0,0 @@ -Xilinx XADC device driver - -This binding document describes the bindings for the Xilinx 7 Series XADC = as well -as the UltraScale/UltraScale+ System Monitor. - -The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xil= inx. -The XADC has a DRP interface for communication. Currently two different -frontends for the DRP interface exist. One that is only available on the Z= YNQ -family as a hardmacro in the SoC portion of the ZYNQ. The other one is ava= ilable -on all series 7 platforms and is a softmacro with a AXI interface. This bi= nding -document describes the bindings for both of them since the bindings are ve= ry -similar. - -The Xilinx System Monitor is an ADC that is found in the UltraScale and -UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface= for -communication. Xilinx provides a standard IP core that can be used to acce= ss the -System Monitor through an AXI interface in the FPGA fabric. This IP core is -called the Xilinx System Management Wizard. This document describes the bi= ndings -for this IP. - -Required properties: - - compatible: Should be one of - * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device - configuration interface to interface to the XADC hardmacro. - * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to - interface to the XADC hardmacro. - * "xlnx,system-management-wiz-1.3": When using the - Xilinx System Management Wizard fabric IP core to access the - UltraScale and UltraScale+ System Monitor. - - reg: Address and length of the register set for the device - - interrupts: Interrupt for the XADC control interface. - - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, - when using the axi-xadc or the axi-system-management-wizard this must be - the clock that provides the clock to the AXI bus interface of the core. - -Optional properties: - - xlnx,external-mux: - * "none": No external multiplexer is used, this is the default - if the property is omitted. - * "single": External multiplexer mode is used with one - multiplexer. - * "dual": External multiplexer mode is used with two - multiplexers for simultaneous sampling. - - xlnx,external-mux-channel: Configures which pair of pins is used to - sample data in external mux mode. - Valid values for single external multiplexer mode are: - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Valid values for dual external multiplexer mode are: - 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] - 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] - ... - 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] - - This property needs to be present if the device is configured for - external multiplexer mode (either single or dual). If the device is - not using external multiplexer mode the property is ignored. - - xnlx,channels: List of external channels that are connected to the ADC - Required properties: - * #address-cells: Should be 1. - * #size-cells: Should be 0. - - The child nodes of this node represent the external channels which are - connected to the ADC. If the property is no present no external - channels will be assumed to be connected. - - Each child node represents one channel and has the following - properties: - Required properties: - * reg: Pair of pins the channel is connected to. - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Note each channel number should only be used at most - once. - Optional properties: - * xlnx,bipolar: If set the channel is used in bipolar - mode. - - -Examples: - xadc@f8007100 { - compatible =3D "xlnx,zynq-xadc-1.00.a"; - reg =3D <0xf8007100 0x20>; - interrupts =3D <0 7 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&pcap_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - }; - channel@1 { - reg =3D <1>; - }; - channel@8 { - reg =3D <8>; - }; - }; - }; - - xadc@43200000 { - compatible =3D "xlnx,axi-xadc-1.00.a"; - reg =3D <0x43200000 0x1000>; - interrupts =3D <0 53 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&fpga1_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - xlnx,bipolar; - }; - }; - }; - - adc@80000000 { - compatible =3D "xlnx,system-management-wiz-1.3"; - reg =3D <0x80000000 0x1000>; - interrupts =3D <0 81 4>; - interrupt-parent =3D <&gic>; - clocks =3D <&fpga1_clk>; - - xlnx,channels { - #address-cells =3D <1>; - #size-cells =3D <0>; - channel@0 { - reg =3D <0>; - xlnx,bipolar; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Doc= umentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml new file mode 100644 index 000000000000..06a0ce498352 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XADC and UltraScale System Monitor + +maintainers: + - Lars-Peter Clausen + +description: | + The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP + (Dynamic Reconfiguration Port) interface for communication. Two different + frontends for the DRP interface are supported: + + - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in + the SoC portion of the ZYNQ device. + - AXI softmacro: available on all Series 7 platforms as a softmacro + with an AXI interface (PG019). + + The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+ + FPGAs. It is accessed through the Xilinx System Management Wizard IP core + via an AXI interface in the FPGA fabric. + + The xlnx,channels subnode name contains a comma as part of the legacy + device tree binding that has been in use for over a decade. This name is + retained for backwards compatibility with existing device trees. + +properties: + compatible: + enum: + - xlnx,zynq-xadc-1.00.a + - xlnx,axi-xadc-1.00.a + - xlnx,system-management-wiz-1.3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: | + When using the ZYNQ this must be the ZYNQ PCAP clock. + When using the axi-xadc or system-management-wiz this must be + the clock that provides the clock to the AXI bus interface. + maxItems: 1 + + xlnx,external-mux: + $ref: /schemas/types.yaml#/definitions/string + description: | + Selects the external multiplexer mode. If omitted, no external + multiplexer is used. + enum: + - none + - single + - dual + + xlnx,external-mux-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configures which pair of pins is used to sample data in external + multiplexer mode. Required when xlnx,external-mux is "single" or + "dual". + + Valid values for single external multiplexer mode: + 0: VP/VN + 1: VAUXP[0]/VAUXN[0] + 2: VAUXP[1]/VAUXN[1] + ... + 16: VAUXP[15]/VAUXN[15] + + Valid values for dual external multiplexer mode: + 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] + 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] + ... + 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] + minimum: 0 + maximum: 16 + + xlnx,channels: + type: object + description: + List of external channels connected to the ADC. If this node is + absent, no external channels are assumed to be connected. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^channel@([0-9a-f]|10)$": + type: object + description: + Represents an external channel connected to the ADC. + + properties: + reg: + description: | + Pair of pins the channel is connected to. + 0: VP/VN + 1: VAUXP[0]/VAUXN[0] + 2: VAUXP[1]/VAUXN[1] + ... + 16: VAUXP[15]/VAUXN[15] + maxItems: 1 + + xlnx,bipolar: + $ref: /schemas/types.yaml#/definitions/flag + description: + If set, the channel is used in bipolar mode. + + required: + - reg + + additionalProperties: false + + required: + - '#address-cells' + - '#size-cells' + + additionalProperties: false + +allOf: + - if: + properties: + xlnx,external-mux: + enum: + - single + - dual + required: + - xlnx,external-mux + then: + required: + - xlnx,external-mux-channel + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + /* ZYNQ hardmacro example */ + adc@f8007100 { + compatible =3D "xlnx,zynq-xadc-1.00.a"; + reg =3D <0xf8007100 0x20>; + interrupts =3D <0 7 4>; + interrupt-parent =3D <&gic>; + clocks =3D <&pcap_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + }; + channel@1 { + reg =3D <1>; + }; + channel@8 { + reg =3D <8>; + }; + }; + }; + + - | + /* AXI softmacro example */ + adc@43200000 { + compatible =3D "xlnx,axi-xadc-1.00.a"; + reg =3D <0x43200000 0x1000>; + interrupts =3D <0 53 4>; + interrupt-parent =3D <&gic>; + clocks =3D <&fpga1_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + xlnx,bipolar; + }; + }; + }; + + - | + /* UltraScale System Management Wizard example */ + adc@80000000 { + compatible =3D "xlnx,system-management-wiz-1.3"; + reg =3D <0x80000000 0x1000>; + interrupts =3D <0 81 4>; + interrupt-parent =3D <&gic>; + clocks =3D <&fpga1_clk>; + + xlnx,channels { + #address-cells =3D <1>; + #size-cells =3D <0>; + channel@0 { + reg =3D <0>; + xlnx,bipolar; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index b2040011a386..58d35c17704d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29266,6 +29266,13 @@ F: Documentation/devicetree/bindings/watchdog/xlnx= ,xps-timebase-wdt.yaml F: drivers/watchdog/of_xilinx_wdt.c F: drivers/watchdog/xilinx_wwdt.c =20 +XILINX XADC DRIVER +M: Lars-Peter Clausen +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml +F: drivers/iio/adc/xilinx-xadc* + XILINX XDMA DRIVER M: Lizhi Hou M: Brian Xu --=20 2.52.0 From nobody Fri Jun 12 12:44:29 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6AD23F7A9E for ; Fri, 15 May 2026 07:58:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831921; cv=none; b=qzXAxcKW1MDEgN31GR1wgYpM30Irs23XSywAEbdqwwPy6cJhYMfl6MqpPduPu2MXs201kzSCwU1pxApa3SKum1WkvK/upZih/AYuiOi/gY/oVXMNmjrJN2YFkC0TeLHPGbbetn1kSvU9fOmZhHte+oRvAUQvHvs94EGH+0dswUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831921; c=relaxed/simple; bh=0BPD+9vjFSgd3h65DskY/GMiR76jSb75S9E/lfiLFRU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qm1nP3RYxEhZCIWrvLwY9fAM7ZZc6cRosJxqOIO05JGcPRkWNwMzUquxZkWDLorvDGRHXtLkIsmXf0xKeTKjnmZer4kGVQzGGPCIn1rNBw2o0PrcCRqP5sXocc79uimfx11cQ6vtS1TJqIX/9HES/G2Eax56EPJUDuwfR7xK8Oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=sqiQOqUZ; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sqiQOqUZ" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-3660daea6a5so4905171a91.1 for ; Fri, 15 May 2026 00:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778831920; x=1779436720; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D2RAe37c0Y+mS2qQ9ryuy+Bjx4murGSjLzlq4yUfzjU=; b=sqiQOqUZt4W/w8b38r+A8VFw+bAeidEnSjTS99O9bJ83X//CaF7tb5p0GWDdV8NS8l OPMXaCkvBocRe/cpvgiiYs160Jxr+z6Pr/GJ8LZkcPEFF167XCsAQSBVe5K0vv7YtatN 4KNuY7Bp4iCD4aEwjKkjyX7Lkzf6nfauMiDcCFOcu1qYyOnOWlg2U73uij+zpkqsQJly 9sNtjhUdrZ+yV64tYEUU8/V4KHainugmzRBEzUB6/puyQ0f4Uf94pcyfxMFKCXsVPbII 7AAjgEPehz1MvFoHOYPhACMyvPHlluJsimj84ewIphwxtRn0rV+YreskTbDHhwBQ2i7y mqdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778831920; x=1779436720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=D2RAe37c0Y+mS2qQ9ryuy+Bjx4murGSjLzlq4yUfzjU=; b=EBx0RB0FXgX1ldEb0mns7aEnVaaQWdfHXggQKJb9qsCTZwq14wvqWsY8DNKYs5Mukg kkNwjEMFSv6APd/sk2ZFrrNv+ZO9kyX0LjB2ALRvkKoZpbpX14kXve6+zgsMNgwSOGCF H+BW1Mon9+gGRMhfp5YjdExQUI5u+d4ZvUAkorbcWqnXu3foYcAyUkulObbL0Vzd0ck/ +QDRGF7To/E+RtgB/O8WGkEXcilcyb2YAedmbUzxne9kHyiG2V4YO1jWR8uMw68FtyUB 63IvGfqSjRNCZIL+jERB/okj//0DPokn/YVpu28yVN8H8gbZlWreomQ/Edght5MJcuvs TK/g== X-Forwarded-Encrypted: i=1; AFNElJ/DhjV1uX7RyCrR3GsiLPYdWQjPJyyL/336JU2BiSHBMFFzrYLcIja6t2iZzYzR0Gf4hW1X/K2jIPGP2nQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0EdudqTyA+usteABpq2x5FYVfxgAbA+Zs1rJKg10jM4W+t4Bd CGgvvOPNM881vs28ukp/jY4d4iQF3E8j17pyOhHI/Mg6f0ROY/6pOd6w X-Gm-Gg: Acq92OFefoCTq0kVkb177Pjq1Jr/T2znrmNWQIdX/gQ55olmZU8zV1vlo4opp6UJq2Q 9ypuICPYhCuRQ3uvzeOLpUbVeYgRDJPUtdmxrtn1ZKXS3fhYDozJM+/F1/jFBHiDe1MLq1Vo5qF H7B3mGvfe0TM8D6H2G5/Q8vWcrxZWlvj9WpHGf72hCmIo/vekjrUa8UxU/56C9Eb88NUB+1BQ2s bXiyv0j2XKiv3E7ypkiUlFb1ywL1sNNvPUD7XL1llZNUohq3UZQqxNYQOO8/e+IyiF294mbCwGl Lwj8tSYTuBQ1TPjyiKbwNOAWJDNx2uCjIdpP9rj5vZCbS7HT7bXo+wU77sIZwSSw1QCP+IWzBkU qj17WjeeTRi+FwZKzfmHwCaTbu73miRN7kPzbQl5afSYYrcFEk4CgfZeb4K2xBHV0a5fFBOWP1M dH9w+ktsgTkO59unMLb5bv1L6yvHQ80mxuDjG2t7dG X-Received: by 2002:a17:90b:3845:b0:368:763a:17b8 with SMTP id 98e67ed59e1d1-36951889325mr3054654a91.2.1778831920063; Fri, 15 May 2026 00:58:40 -0700 (PDT) Received: from localhost.localdomain ([2405:201:d008:80b:a00:27ff:feb6:42dd]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36959c7eacesm542040a91.2.2026.05.15.00.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2026 00:58:39 -0700 (PDT) From: Pramod Maurya To: jic23@kernel.org Cc: lars@metafoo.de, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pramod.nexgen@gmail.com Subject: [PATCH v4 2/3] staging: axis-fifo: Fix alignment of wait_event_interruptible arguments Date: Fri, 15 May 2026 03:57:35 -0400 Message-ID: <20260515075736.172172-3-pramod.nexgen@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260515075736.172172-1-pramod.nexgen@gmail.com> References: <20260510083219.70224-1-pramod.nexgen@gmail.com> <20260515075736.172172-1-pramod.nexgen@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The second argument to wait_event_interruptible() was indented with a single tab instead of being aligned to the opening parenthesis. Since the fully-aligned form exceeds 80 columns, break the condition at the comparison operator and align the continuation line to the opening parenthesis. Fixes the following checkpatch.pl warning: CHECK: Alignment should match open parenthesis Signed-off-by: Pramod Maurya --- drivers/staging/axis-fifo/axis-fifo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-f= ifo/axis-fifo.c index 3aa2aa870ea9..1c34de020cf8 100644 --- a/drivers/staging/axis-fifo/axis-fifo.c +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -246,7 +246,8 @@ static ssize_t axis_fifo_write(struct file *f, const ch= ar __user *buf, mutex_lock(&fifo->write_lock); =20 ret =3D wait_event_interruptible(fifo->write_queue, - ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >=3D words_to_write); + ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >=3D + words_to_write); if (ret) goto end_unlock; } --=20 2.52.0 From nobody Fri Jun 12 12:44:29 2026 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99BDE3F7A8B for ; Fri, 15 May 2026 07:58:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831927; cv=none; b=cxuuxagC5GgmG5OvY9jfKF8YeChjsZ63/NK9j0aI/Dyl7YEKcPHTxSEOoowZdQnpECdq0Xuc3+4lXzklODZtc0lpz+qi2FqP92zLj7mCy9h+LeuicCtMlna7RgMtt99s+JUWyEuDVQuXqSA9QqbrPsp4UvHBx+SsSPMZBgzzk1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778831927; c=relaxed/simple; bh=wyYa8gIFgLjBYlLhyXw9vzSHb5OxneEJ6CcsElborA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fBue3hA8KfjRCz+WE1hYivtihI0ZTngxjmK3uV+NnkV3hv3z4EithlmmAIucphGevcw1XUyNe3sDwIIiorbJZN2W6JoUIkNzR4UyaSROimGYL02jQ6jhZuhx/CzBrrbGm6iJBLFyNw3AMdRTSe2wHbgqoF+igDQPhZF9qA8vPu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GOyUGC8z; arc=none smtp.client-ip=209.85.216.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GOyUGC8z" Received: by mail-pj1-f49.google.com with SMTP id 98e67ed59e1d1-3664df32e91so7751905a91.3 for ; Fri, 15 May 2026 00:58:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778831924; x=1779436724; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5MiS+JhxTiWTYXV5rcm6uEgwCs/g+gk9Na8Cem5QvF0=; b=GOyUGC8zk2B7f1atKHeOFC8hTNzjFpG8l0wfhMd6NehmJYo0p6jPcvKvZCAYAzF7Bs 91X/PJJ+3425G8d+eFddfzeZNiCqoYudAR5iWKwJfUbOAP9Da25AAPsZHK/3Db2cELIL dXoJqaNBAQOwMqfUxoTNnQWewjyFDhvMLH7qVf7GfocPdXY3GApQCDFTFGepQobbAkuI sXfouRycjEbD5AHxKLUzcsfpl5YFON/SI77PqWuTPGDeb/ZXUXkoipj6TsWenWitIEIa fNO0xeDgDfT/MPY2kTZq5RLZ1SgviWMYmGpqUVSxf+Sh6V8Z8DFnGJ5rFFnvItAinvtB 4tqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778831924; x=1779436724; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5MiS+JhxTiWTYXV5rcm6uEgwCs/g+gk9Na8Cem5QvF0=; b=jFiMuwz06ANmNwVmdzD9pcsbRGeU5tcQDfyNO01d7l8DpzpZG2UgIfDLHC2i55NxJo R1qlES4TfeZKgu9IWldAeuTsfKLMSwmZgNyL5sw2ysaTFvLsIi6X1XTNofUMVDdE2w3z ChNJk5A80+93DWjGV9Jxd14S1a1VWSzbGXXEnKjZmtSvC8wSSZDxbJx6bzh2jIN5kHqz 710fbbKxPQz4y1rAGuoS5EkQjM9ybUSGmpKrzH4Gsvf4af42Qfiw0gyA2cl5rbEPxQJt U4EbmWgdc90kDKTFld8ZRc8/7spiVCg5VW+m1s1GGRr2P+FiejqCHHlTRxqmkMopgLx7 KIDg== X-Forwarded-Encrypted: i=1; AFNElJ+KfvBOo8CRDlPPS8cyPxMdU5r6OcsWeWy0XuTNqkMC83HXnURARbhQ9SmebUjXALYxjz3lfey/X3Chflo=@vger.kernel.org X-Gm-Message-State: AOJu0YzhwiYHCpzFVJM1tVlBdYys4l4FpbUGOWwBIjrkVispbyFItnMU MHLc/vX5X1mvlV7ORL0z7L01FADhcQZIEYtUrg05hXxAQFgBmub2mIJy X-Gm-Gg: Acq92OFLuRtGg21v6qEBSXCi6Zd+eU/6/KX2RMkMgTvm083LchZ86CwuLg61H7OobAG g6+SDrMGSqVyrqy1KvqcJjdnm9sZO2AvtVVeMJNk31SKcJc7GveIHWcSFi3VusJ3Oc2LZriEOaP AHJt9DokBBYbtXumrY5JuS3UJwA5EyzrhDK3is0uQ/7cWW1WxzXWB/Yv5USEmzr9/QEPmSbIkzu gxHTs5Cvp37/tx02kIPEhv7oX6p66Vl7bm8KFmx25LkF42kXcv9Ctb9SDTUsfwGZgJiIlJ/ia8d eWsjItbPhWstnfHrrsNYTUM7N9kbS21rD2kHLBBE42kAsyunSfzwyJYnT+Zycyp2R6AnjGYQm1R IKPNDVzDd+eqZ5zVA+PZEE/vrpKl0i7qmXNWOGpF+9ODVAm1CUYoz73ILs52rrXOwlSJirf0jvR 2AFDWCnEFPUotLA1u7jdfplY7CcnQEh+Pkt9wONJqh X-Received: by 2002:a17:90b:38d2:b0:366:33a6:9921 with SMTP id 98e67ed59e1d1-369519af699mr2924409a91.4.1778831923836; Fri, 15 May 2026 00:58:43 -0700 (PDT) Received: from localhost.localdomain ([2405:201:d008:80b:a00:27ff:feb6:42dd]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36959c7eacesm542040a91.2.2026.05.15.00.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2026 00:58:43 -0700 (PDT) From: Pramod Maurya To: jic23@kernel.org Cc: lars@metafoo.de, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pramod.nexgen@gmail.com Subject: [PATCH v4 3/3] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO Date: Fri, 15 May 2026 03:57:36 -0400 Message-ID: <20260515075736.172172-4-pramod.nexgen@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260515075736.172172-1-pramod.nexgen@gmail.com> References: <20260510083219.70224-1-pramod.nexgen@gmail.com> <20260515075736.172172-1-pramod.nexgen@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080). The binding documents the three supported compatible strings and the vendor-specific properties that the axis-fifo staging driver reads from the device tree. This resolves the following checkpatch.pl warnings in drivers/staging/axis-fifo/axis-fifo.c: WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documen= ted WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documen= ted WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documen= ted Signed-off-by: Pramod Maurya --- .../bindings/misc/xlnx,axi-fifo-mm-s.yaml | 93 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm= -s.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml= b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml new file mode 100644 index 000000000000..f4ef7c277cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI-Stream FIFO + +maintainers: + - Jacob Feder + +description: + The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to + an AXI-Stream FIFO IP core. It allows a processor to transmit and receive + AXI-Stream packets via simple MMIO register reads and writes. Currently + only store-forward mode with a 32-bit AXI4-Lite interface is supported. + +properties: + compatible: + enum: + - xlnx,axi-fifo-mm-s-4.1 + - xlnx,axi-fifo-mm-s-4.2 + - xlnx,axi-fifo-mm-s-4.3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + xlnx,axi-str-rxd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width of the receive AXI-Stream data bus in bits. Currently only 32 + is supported. + const: 32 + + xlnx,axi-str-txd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width of the transmit AXI-Stream data bus in bits. Currently only 32 + is supported. + const: 32 + + xlnx,rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of the receive FIFO in words. + + xlnx,tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of the transmit FIFO in words. + + xlnx,use-rx-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Set to 1 if the receive data FIFO is enabled, 0 otherwise. + enum: [0, 1] + + xlnx,use-tx-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Set to 1 if the transmit data FIFO is enabled, 0 otherwise. + enum: [0, 1] + +required: + - compatible + - reg + - interrupts + - xlnx,axi-str-rxd-tdata-width + - xlnx,axi-str-txd-tdata-width + - xlnx,rx-fifo-depth + - xlnx,tx-fifo-depth + - xlnx,use-rx-data + - xlnx,use-tx-data + +additionalProperties: false + +examples: + - | + axi_fifo: fifo@43c00000 { + compatible =3D "xlnx,axi-fifo-mm-s-4.3"; + reg =3D <0x43c00000 0x10000>; + interrupts =3D <0 30 4>; + interrupt-parent =3D <&intc>; + xlnx,axi-str-rxd-tdata-width =3D <32>; + xlnx,axi-str-txd-tdata-width =3D <32>; + xlnx,rx-fifo-depth =3D <0x1000>; + xlnx,tx-fifo-depth =3D <0x1000>; + xlnx,use-rx-data =3D <1>; + xlnx,use-tx-data =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 58d35c17704d..bbb6b8c20ed6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29164,6 +29164,12 @@ S: Maintained F: Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml F: drivers/iio/adc/xilinx-ams.c =20 +XILINX AXI-STREAM FIFO DRIVER +M: Jacob Feder +S: Maintained +F: Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml +F: drivers/staging/axis-fifo/ + XILINX AXI ETHERNET DRIVER M: Radhey Shyam Pandey S: Maintained --=20 2.52.0