From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 074741DE8BE; Fri, 15 May 2026 01:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; cv=none; b=ehVlM1HwxIIbogtgvMlsklMU2Oa8IEKcsD2v1cbh8uzOWgu+3CBntIYpOV8VpTMYMQJB10473iwWC0XmaPNva40jEUAur3RfM6dL2CDTxO52nC+meh+E5mYJt/ujJQQk32/5DlCWM+zBKBUFIkMZN03PNLiisLFlPKXv1B4J1yU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; c=relaxed/simple; bh=jjQnxfRGET2wkjQ49uKQqq5EzfIY6g35fjsnjyMVD4U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mvX1PspUH+5mj2eXCx0O8Q3NaohYC89xW2peb3CXnIffTpEYKtGwE5TKfo0+DxwJkuZjHZld/08ujJBT5pUJHIeHPYxcoAWuWr5/kfkHICGdk7Hu4lL0HbNQPeHN1OpmWh/UeDTbbwIhFDH3FbVz+MuhNe5piHk8accJztjPZEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OY+pFhx5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OY+pFhx5" Received: by smtp.kernel.org (Postfix) with ESMTPS id B441FC2BCC6; Fri, 15 May 2026 01:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778807892; bh=jjQnxfRGET2wkjQ49uKQqq5EzfIY6g35fjsnjyMVD4U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OY+pFhx5lOG86Ao5tfC2wtNj6CF2cBACUAsOrpG69Pz+aYYebjMhdfmIlOa8IbvOJ umTOSEzROcreQEP8fktrctT7MnEKs5b9gr7aI8ZJJ3R3Ks7BLHANOEfRSTL+xN0vJC LXnvNK4khINUkoNB0wFOenvDQVarwWlGNzOHCLiq6KK1fE9Lt4N3LU1qquD2cKjfSn 26R3K4reFS/Uarx/tsxXV+yLk0wBDSFt3VKczWxgtdg8+zIYFDyfxwmBv40FRcVvSf QwbFl4Rw5OSEYwEUwI4YPMRmru4yVO3V6SqeQ0xHj+jDSO3/FyKjr+g9F8o/9sx3uu Qmke8Hd6XKj7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A164ACD4F39; Fri, 15 May 2026 01:18:12 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:17:57 +0800 Subject: [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-1-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=871; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=9QG7ZiRK3RyROMWf2rb572b5ZDl0GYAcQWD6s3msFM8=; b=BmYVDPTGabV641x/qomuXrXxvhNW6sr86M4t/0nTP8YFuQsD95smGsJaFll9aSWKoJtQnh7cU 5tJXdszmLHLBQn3ku83uxnGymFuIGnfBD/Gu4ylCzy79lP6l68xIEup X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..04e593c66c7c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1407,6 +1407,8 @@ patternProperties: description: Rockchip Electronics Co., Ltd. "^rocktech,.*": description: ROCKTECH DISPLAYS LIMITED + "^rongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^rohm,.*": description: ROHM Semiconductor Co., Ltd "^ronbo,.*": --=20 2.34.1 From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0F23385BE; Fri, 15 May 2026 01:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; cv=none; b=bvyM8Q/6W1JnpJ3KrdMFUN5/72r+RGVga7tJVlkmr0MjSRweNvPucg5rtmjr0buuzMuXhdk6Of6quFwsrL6qSbY92CF3dkciVGclWi31iFsNNyi+sIeiKUCGOUnUZJmMEgP9GI2GUIstshkg+i1tlmO+6qfyUewbArbpxYka5mY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; c=relaxed/simple; bh=wWzUQXRnbB0RB/9TAJFVHDrh9+wM/VoEhvOqImuQdSU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RbnFCy2qmRuhCb3wIwEbS3IlGKyL3DQy/R8za7PauutZpWnNgoiSUC9CTwx+tGuqtZu0e6WLmk1ebFcf2B9HHNHVmauNDLCmAf+/ir1lYaFRQb8gy/d/768G3ax/VmDQxHWQgZwalgv7CtnuicsXZyCKCRWcNfXT6jN4slG4jrc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Uvz6LxSB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Uvz6LxSB" Received: by smtp.kernel.org (Postfix) with ESMTPS id BFD4FC2BCC9; Fri, 15 May 2026 01:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778807892; bh=wWzUQXRnbB0RB/9TAJFVHDrh9+wM/VoEhvOqImuQdSU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Uvz6LxSBRs0Xft2rXVCD6uVrvfCNLCzx5vIeGQuNrciFk0Ge87j/7ZpjBSFA71Ux8 4nF/VQMkD/nGrYNRm/WwoziPMN1eHQsSe1wZDiVeFopY42FssdPZfZIhD1wf+ohpXZ UPYiTZbUeIUS11wI6qbnKD3wOgdjL8J7GABEDU8eLYVdyizCi42CWBTfw7aq53c1Zc cgf3p/6CCnJyVZ+r/LC4Ewwo2tQ5TfJmCXGkL3Zbog2ewuFp9hJ9W9LvsM5+IKB/Lf lsLt1fK/i0nEAJBdVAgRu3hYcHUyxe59KF9E0cbLtJc/qGQTjv/J2TCZdEnol/X1lM hOrjWx4rsxQxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3811CD4F25; Fri, 15 May 2026 01:18:12 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:17:58 +0800 Subject: [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-2-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=757; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=XZFNeOKWu/CkLjPDC+5weDpv+XeEMBj7yaDkjZ2TskU=; b=f4NijLLDER036QaslKhiTpq3CTiQi8EvmPdcda9IBEWa7XodQ/34i0jF6cN01hhGnaYRoq914 jbulhmTlriFA0pZS9SDJ/22YUVe9cGvjG5hLQ97ZKrIjM98NQ/Nyhdf X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Update Documentation for supporting UltraRISC CP100 based CPU. CP100 is used in UltraRISC DP1000 SoC. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..9f5226717701 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: --=20 2.34.1 From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F0722F7478; Fri, 15 May 2026 01:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; cv=none; b=LLUTdhz2e6Y2dYjeQyVoHCNL+t6Pdq2V7L5hxipkIcSSYBqOpwz4mSDfq2Y1H8vam55/HWfFZWLpwUx4GWO3tZuLgC8/8nvQLsip2QeLXoBKAvh1fU8JZe3FF5OJCySXe3V2LEZSwSO6/YZI22goTVAc/9mxcBBtVDvGWFU5XII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; c=relaxed/simple; bh=fldrCiL0VTRIPUbDx8lKsvu2ghQXL+gjW6ClP1G/zJ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bWCZJTU80MAyXNM7+ZC/eCVxZTF8z4ebE6XQyKEpBzEhgTAOPGqA9y/yAXSPxfnNwOZw0u1GSpnO8sTdY5wk/RNKqUuuE/Wd9tQQ7u1k9oVd9i8QOmrTU7i7AiSxuvHdRqQMeYwGe0bX2RMjr53bT9x4kG+V44hwUUDETizJ8d4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CMe2IjR5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CMe2IjR5" Received: by smtp.kernel.org (Postfix) with ESMTPS id CF969C2BCC7; Fri, 15 May 2026 01:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778807892; bh=fldrCiL0VTRIPUbDx8lKsvu2ghQXL+gjW6ClP1G/zJ4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CMe2IjR5SW+Nb8znQxvKBwUFj0RV3/YiOSjGvEmhkqDqKef8cevOfwaX19znyNTOX Iobn6EuSEebocm5wK4TxfEExU3yWi1hH/mfPYOflO9MtWZZzOR53Xqv/O/N/rWqYWj KbTBIbihGe/3IGkwQDbTvOWAYNJOvZWaCirrNMJ4hSsTCeq6JmMmfXWnVvT7WHdGi+ MhSGbGCZvsi1ICwlcQsiwcLonjclsGPGVsYYV3YCv8A6a+vTXC02FfrL72rgZnK+vm Lxd3GeRMkeQ+IMDUgSf3ygkZbV+VKLtEMdZfUlqDdyNi9WAm/HMBipYRrfn7bTLIAl MjbuqKdKHG/Ww== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C36BBCD37AC; Fri, 15 May 2026 01:18:12 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:17:59 +0800 Subject: [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-3-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=1778; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=qaBC2cTXnLnD+JIt0DLP1KqvWkTUCFHsUaQu5JTU/dA=; b=WjaarwqtmIiEMHOknJXQgaDxZpuJJfoLCE7K7+8MSl1guMQezkfhgQUtrbv5/DmQj7A6v8tJ9 d+WC3TY9ctLAq4A0b3FJ1jfR0C4XK/KzKYSFEKNzqBXQW77JE2Nf+UF X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add DT binding documentation for the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++= ++++ MAINTAINERS | 6 +++++ 2 files changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Docum= entation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..d4421c2ef945 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - rongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index b2040011a386..5bf971ff48b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23082,6 +23082,12 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h =20 +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.34.1 From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4060A368964; Fri, 15 May 2026 01:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; cv=none; b=gXImaFGqkL5TcBW7WRr5agUy5JkWhpep+PTFqDVm96bgDrbwWYweI/iRYrI+ROu7EzoS/DIts8QLXfYOC6Zvm3QyAWc7KDoOB6gLALw2L9xv59E7qofr3JQBh5VbNwlE+P8VV6OTmkEpvBAXRo5dV2pi2FWo6b+6zeIsD0UjOcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778807893; c=relaxed/simple; bh=JRT4MxexkJ8P9HZKdmQPtFUfwGYiqT4wP9WIUsn4168=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lLcIwN773zpTByPQmjv3VJuFhxAzrk4m5YdG2/BZONHFB3eQkA3XTbm4azqOS0quACgh8WthOPtQoPOuFXJb1EI041HcldKBQ4a0NEWDH+c01VpKW1BR/+qxnioALaq1paxRZHSu15xOAMXsDzI4GYMCO4mwRiXHokeyH/YyA7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gR0k//j7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gR0k//j7" Received: by smtp.kernel.org (Postfix) with ESMTPS id E6646C2BD04; Fri, 15 May 2026 01:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778807893; bh=JRT4MxexkJ8P9HZKdmQPtFUfwGYiqT4wP9WIUsn4168=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gR0k//j7qkAzUXnvIqUEuVeowhfkes0+7ugmE/gHhf4nSij8jWF44kbBvFQhm+2V1 GjNFApvNQqxsSLtwoI13GPUmQqNAYoRTXWsl9SpiXJ/Q7KtSd4FBaSKfbzjaqwsc1w YEgvM8KKrNzYlwRWuhxPYvced3CuGs2mUQReCk1rC185cTt2HriFsMb68ApFcPSfXh cqUHFFrfyGRs/38zXk7ycPdsdf7Q+7xtcuDKMOoa/wJfYBvVBFlmRSRObNcAZFBS2l KoNYh3mCTCEFQEObIrg5GUtOHh6M64E48Z+WEBM/KWp2ngk+9JSsAX3U/7a0W/VyeZ ok4rwIxEDCW4g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4645CD4F3C; Fri, 15 May 2026 01:18:12 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:18:00 +0800 Subject: [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-4-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=8595; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=Ryby9hZuN7SHyXVlBdmHsw3fGds+h05WBF/9u3gnjj8=; b=1ms6oJVaXPuFMoEnClPMUvo6AV+r6jTiIXQ9zEWR4VHGoOAViGCJib+EFlvbUc0a5qin/9UDG rWr1XkxHvIgB4wag7aLpzeY/ac3tDhqhHQfvxVByu2v+/YuefwPrFcp X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add bindings for the pin controllers on the UltraRISC DP1000 RISC-V SoC. Signed-off-by: Jia Wang --- .../bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml | 168 +++++++++++++++++= ++++ MAINTAINERS | 7 + .../dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h | 65 ++++++++ 3 files changed, 240 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pin= ctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinc= trl.yaml new file mode 100644 index 000000000000..c7ed1f96382a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.ya= ml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 Pin Controller +maintainers: + - Jia Wang + +description: | + UltraRISC RISC-V SoC DP1000 pin controller. + + The binding supports two child node styles under the same controller + compatible: + + - legacy DP1000-specific nodes using phandle-array properties + `pinctrl-pins` and `pinconf-pins` + - generic pinctrl nodes using `pins`, `function` and generic pin + configuration properties + +properties: + compatible: + const: ultrarisc,dp1000-pinctrl + + reg: + maxItems: 1 + + "#pinctrl-cells": + $ref: /schemas/types.yaml#/definitions/uint32 + +patternProperties: + '.*-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + properties: + pinctrl-pins: + description: | + The list of pins and their mux settings that properties in the n= ode + apply to. The format: `PORT PIN FUNCTION`. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + pinconf-pins: + description: | + The list of pins and their pad configuration that properties in = the + node apply to. The format: `PORT PIN CONF`. + CONF is a DP1000-specific encoding of pull and drive strength as + defined in dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + pins: + description: List of pins affected by this state node. + minItems: 1 + uniqueItems: true + items: + type: string + pattern: '^(PA([0-9]|1[0-5])|P[BCD][0-7]|LPC([0-9]|1[0-2]))$' + + function: + description: | + Mux function to select for the listed pins. + gpio maps to the hardware default mode. The default mode is + GPIO for PA/PB/PC/PD pins and LPC for LPC pins. + func1 is not supported on LPC pins. + enum: + - gpio + - func0 + - func1 + + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: Output drive strength in mA. + enum: [20, 27, 33, 40] + + oneOf: + - allOf: + - anyOf: + - required: [pinctrl-pins] + - required: [pinconf-pins] + - not: + required: [pins] + - allOf: + - required: [pins] + - not: + anyOf: + - required: [pinctrl-pins] + - required: [pinconf-pins] + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pinmux@11081000 { + compatible =3D "ultrarisc,dp1000-pinctrl"; + reg =3D <0x0 0x11081000 0x0 0x1000>; + #pinctrl-cells =3D <2>; + + i2c0-pins { + pins =3D "PA12", "PA13"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0-pins { + pins =3D "PA8", "PA9"; + function =3D "func1"; + bias-pull-up; + drive-strength =3D <33>; + }; + }; + }; + + - | + /* Legacy example */ + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pinmux@11081000 { + compatible =3D "ultrarisc,dp1000-pinctrl"; + reg =3D <0x0 0x11081000 0x0 0x1000>; + #pinctrl-cells =3D <2>; + + i2c0-pins { + pinctrl-pins =3D < + UR_DP1000_IOMUX_A 12 UR_DP1000_FUNC0 + UR_DP1000_IOMUX_A 13 UR_DP1000_FUNC0 + >; + + pinconf-pins =3D < + UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_DP1000_PULL_UP, + UR_DP1000_DRIVE_DEF) + UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_DP1000_PULL_UP, + UR_DP1000_DRIVE_DEF) + >; + }; + + uart0-pins { + pinctrl-pins =3D < + UR_DP1000_IOMUX_A 8 UR_DP1000_FUNC1 + UR_DP1000_IOMUX_A 9 UR_DP1000_FUNC1 + >; + + pinconf-pins =3D < + UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_DP1000_PULL_UP, + UR_DP1000_DRIVE_DEF) + UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_DP1000_PULL_UP, + UR_DP1000_DRIVE_DEF) + >; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5bf971ff48b2..baaaa46b1a56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27358,6 +27358,13 @@ S: Maintained F: drivers/usb/common/ulpi.c F: include/linux/ulpi/ =20 +ULTRARISC DP1000 PINCTRL DRIVER +M: Jia Wang +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml +F: include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h + ULTRATRONIK BOARD SUPPORT M: Goran Ra=C4=91enovi=C4=87 M: B=C3=B6rge Str=C3=BCmpfel diff --git a/include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h b/inclu= de/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h new file mode 100644 index 000000000000..bef28115898d --- /dev/null +++ b/include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * UltraRISC DP1000 pinctrl header. + * + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H +#define _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H + +/** + * UltraRISC DP1000 IO pad configuration + * port: A, B, C, D, LPC + * Pin in the port + * pin: + * PA: 0 - 15 + * PB-PD: 0 - 7 + * LPC: 0 - 12 + * func: + * UR_DP1000_FUNC_DEF: default + * UR_DP1000_FUNC0: func0 + * UR_DP1000_FUNC1: func1 + */ +#define UR_DP1000_IOMUX_A 0x0 +#define UR_DP1000_IOMUX_B 0x1 +#define UR_DP1000_IOMUX_C 0x2 +#define UR_DP1000_IOMUX_D 0x3 +#define UR_DP1000_IOMUX_LPC 0x4 + +#define UR_DP1000_FUNC_DEF 0 +#define UR_DP1000_FUNC0 1 +#define UR_DP1000_FUNC1 0x10000 + +/** + * Configure pull up/down resistor of the IO pin + * UR_DP1000_PULL_DIS: disable pull-up and pull-down + * UR_DP1000_PULL_UP: enable pull-up + * UR_DP1000_PULL_DOWN: enable pull-down + */ +#define UR_DP1000_PULL_DIS 0 +#define UR_DP1000_PULL_UP 1 +#define UR_DP1000_PULL_DOWN 2 +/** + * Configure drive strength of the IO pin + * UR_DP1000_DRIVE_DEF: default value, reset value is 2 + * UR_DP1000_DRIVE_0: 20mA + * UR_DP1000_DRIVE_1: 27mA + * UR_DP1000_DRIVE_2: 33mA + * UR_DP1000_DRIVE_3: 40mA + */ +#define UR_DP1000_DRIVE_DEF 2 +#define UR_DP1000_DRIVE_0 0 +#define UR_DP1000_DRIVE_1 1 +#define UR_DP1000_DRIVE_2 2 +#define UR_DP1000_DRIVE_3 3 + +/** + * Combine the pull-up/down resistor and drive strength + * pull: UR_DP1000_PULL_DIS, UR_DP1000_PULL_UP, UR_DP1000_PULL_DOWN + * drive: UR_DP1000_DRIVE_DEF, UR_DP1000_DRIVE_0, UR_DP1000_DRIVE_1, + * UR_DP1000_DRIVE_2, UR_DP1000_DRIVE_3 + */ +#define UR_DP1000_BIAS(pull, drive) (((pull) << 2) | (drive)) + +#endif /* _DT_BINDINGS_PINCTRL_ULTRARISC_DP1000_PINCTRL_H */ --=20 2.34.1 From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EC3D367F44; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-5-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=25874; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=TnWbocLflgDfzfKXlLjVQf0dGw+ONyA7AHpdfXbMXbA=; b=BV+r5LeBu3elFFVgigOhuIzUH6Z0zDigCfx9AqrWW3iCmwwEIqesxh1XadqxgaAT3HT2m74A2 CqyXC9RA20dCHxhYtt8Lde7u+sGEqKdOxOTcArGUbJ/EsD4vQtJMROK X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the base device tree for the UltraRISC DP1000 SoC. It describes the 8=C3=97CP100 CPU cores and essential SoC peripherals including the interrupt controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC and the DMA controller. Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb= 5@ultrarisc.com/ Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e= 274@ultrarisc.com/ Signed-off-by: Jia Wang --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 851 ++++++++++++++++++++++++++= ++++ 2 files changed, 852 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index baaaa46b1a56..832e01898ae5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23087,6 +23087,7 @@ M: Jia Wang L: linux-riscv@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dt= s/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..1aae53fc1a2b --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,851 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible =3D "ultrarisc,dp1000"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <10000000>; + + cpu0: cpu@0 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x0>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache0>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache0: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x1>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache1>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache1: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x2>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache2>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache2: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x3>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache3>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache3: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x10>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache4>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache4: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu5: cpu@5 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x11>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache5>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache5: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu6: cpu@6 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x12>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache6>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache6: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu7: cpu@7 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x13>; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdcbh"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache7>; + riscv,cbom-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <0x01>; + }; + + l2_cache7: l2-cache { + /* L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + }; + + clocks { + device_clk: device_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <62500000>; + #clock-cells =3D <0>; + }; + + timer_clk: timer_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <50000000>; + #clock-cells =3D <0>; + }; + + csr_clk: csr_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <250000000>; + #clock-cells =3D <0>; + }; + }; + + l4_cache: l4-cache { + /* L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <4>; + cache-size =3D <0x1000000>; + cache-sets =3D <0x4000>; + cache-unified; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00 0x80000000 0x4 0x00000000>; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + + clint: clint@8000000 { + compatible =3D "sifive,clint0", "riscv,clint0"; + reg =3D <0x00 0x8000000 0x00 0x100000>; + interrupts-extended =3D <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, + <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, + <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, + <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, + <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, + <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, + <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, + <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; + }; + + plic: plic@9000000 { + compatible =3D "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg =3D <0x00 0x9000000 0x00 0x4000000>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc= 0xa>, + <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, + <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, + <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, + <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, + <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, + <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, + <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; + riscv,ndev =3D <160>; + }; + + pmx0: pinmux@11081000 { + compatible =3D "ultrarisc,dp1000-pinctrl"; + reg =3D <0x0 0x11081000 0x0 0x1000>; + #pinctrl-cells =3D <2>; + }; + + gpio: gpio@20200000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x20200000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "bus", "db"; + clocks =3D <&csr_clk>, <&device_clk>; + + gpio_a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <16>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <34>; + gpio-ranges =3D <&pmx0 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pmx0 16 0 8>; + }; + + gpio_c: gpio-port@2 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pmx0 24 0 8>; + }; + + gpio_d: gpio-port@3 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <3>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pmx0 32 0 8>; + }; + }; + + uart0: serial@20300000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x00 0x20300000 0x00 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <17>; + clock-frequency =3D <62500000>; + reg-io-width =3D <0x04>; + reg-shift =3D <0x02>; + }; + + uart1: serial@20310000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x00 0x20310000 0x00 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <18>; + clock-frequency =3D <62500000>; + reg-io-width =3D <0x04>; + reg-shift =3D <0x02>; + }; + + uart2: serial@20400000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x00 0x20400000 0x00 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <25>; + clock-frequency =3D <62500000>; + reg-io-width =3D <0x04>; + reg-shift =3D <0x02>; + }; + + uart3: serial@20410000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x00 0x20410000 0x00 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <26>; + clock-frequency =3D <62500000>; + reg-io-width =3D <0x04>; + reg-shift =3D <0x02>; + }; + + spi0: spi@20320000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0x0 0x20320000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <19>; + num-cs =3D <3>; + }; + + spi1: spi@20420000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0x0 0x20420000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <27>; + num-cs =3D <3>; + }; + + i2c0: i2c@20330000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x20330000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <20>; + }; + + i2c1: i2c@20340000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x20340000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <21>; + }; + + i2c2: i2c@20430000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x20430000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <28>; + }; + + i2c3: i2c@20440000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x20440000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&device_clk>; + interrupt-parent =3D <&plic>; + interrupts =3D <29>; + }; + + pcie_x16: pcie@21000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x21000000 0x0 0x01000000>, + <0x0 0x4fff0000 0x0 0x00010000>; + reg-names =3D "dbi", "config"; + ranges =3D <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <16>; + interrupt-parent =3D <&plic>; + interrupts =3D <43>, <44>, <45>, <46>, <47>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + }; + + pcie_x4a: pcie@23000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x23000000 0x0 0x01000000>, + <0x0 0x6fff0000 0x0 0x00010000>; + reg-names =3D "dbi", "config"; + ranges =3D <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <63>, <64>, <65>, <66>, <67>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + }; + + pcie_x4b: pcie@24000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x24000000 0x0 0x01000000>, + <0x0 0x7fff0000 0x0 0x00010000>; + reg-names =3D "dbi", "config"; + ranges =3D <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <73>, <74>, <75>, <76>, <77>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + }; + + ethernet: ethernet@38000000 { + compatible =3D "snps,dwmac", "snps,dwmac-5.10a"; + reg =3D <0x00 0x38000000 0x00 0x1000000>; + clocks =3D <&csr_clk>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&plic>; + interrupts =3D <84>; + interrupt-names =3D "macirq"; + local-mac-address =3D [ff ff ff ff ff ff]; + max-speed =3D <1000>; + phy-mode =3D "rgmii-id"; + snps,txpbl =3D <8>; + snps,rxpbl =3D <8>; + }; + + dmac: dma-controller@39000000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0x0 0x39000000 0x0 0x400>; + clocks =3D <&device_clk>, <&device_clk>; + clock-names =3D "core-clk", "cfgr-clk"; + #dma-cells =3D <1>; + dma-channels =3D <8>; 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b=kdhWWJJbkN7l8bVUxBtesHmIxahTPemosAtwTXXaDmhE7Xj0bXdaTPTBvjeUQhlTS r2oRT7HT44NyMtbTbIldOBXmNvhjBTUI2FcznLKTYl/9WO90EQ213BuXv6Xq2T8v0c 1cmfjAolRmL10jMiU9N2JL2BREo36TH6WtkYw/wl9RilBITnMIm6nES+YRoCVsp1m0 RQJDpKOPgAONVt/Lz9B6JhodkaK0LYWcDoxZu92tKlaRTZoxEQWFMLRIkJDhAQyXyq WV4GYBwMwlzixHe3TtwnJJ7a2jYf/Iaw7htJnocvd/MEP2V9QgkH2azdD8GO1ngotB wf6r65mglzvHA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04F09CD4F25; Fri, 15 May 2026 01:18:13 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:18:02 +0800 Subject: [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-6-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=29980; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=8drpWySj4LGM4a6wP0yAw40A5piAI3o4i67FqENQcw0=; b=iULDG55BK0A/HETCfUkm4hsy7BYFADem6KTGqb0FNUuOfba63JYTU4LkiUhtAOLYmCPfrX4jW fYZreQ2DlPEDDJh3Zm2F69EfD1SPGpEcxsf1NkbyGvHO4SyIlaEGn5L X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add pinctrl driver for UltraRISC DP1000 pinctrl controller. Signed-off-by: Jia Wang --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/ultrarisc/Kconfig | 23 + drivers/pinctrl/ultrarisc/Makefile | 4 + drivers/pinctrl/ultrarisc/pinctrl-dp1000.c | 112 ++++ drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 746 ++++++++++++++++++++++= ++++ drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 71 +++ 8 files changed, 959 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 832e01898ae5..ecd87d58f28c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27364,6 +27364,7 @@ M: Jia Wang L: linux-gpio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml +F: drivers/pinctrl/ultrarisc/* F: include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h =20 ULTRATRONIK BOARD SUPPORT diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 03f2e3ee065f..76105be8b395 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -711,5 +711,6 @@ source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/visconti/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" +source "drivers/pinctrl/ultrarisc/Kconfig" =20 endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f7d5d5f76d0c..4df3e52518ea 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -98,3 +98,4 @@ obj-y +=3D ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) +=3D uniphier/ obj-$(CONFIG_PINCTRL_VISCONTI) +=3D visconti/ obj-$(CONFIG_ARCH_VT8500) +=3D vt8500/ +obj-$(CONFIG_ARCH_ULTRARISC) +=3D ultrarisc/ diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/= Kconfig new file mode 100644 index 000000000000..ba8747b90127 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_ULTRARISC + tristate + depends on OF + select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINCONF + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select IRQ_DOMAIN_HIERARCHY + select MFD_SYSCON + +config PINCTRL_ULTRARISC_DP1000 + tristate "UltraRISC DP1000 SoC Pinctrl driver" + select PINCTRL_ULTRARISC + depends on OF && HAS_IOMEM + default ARCH_ULTRARISC + help + Say Y to select the pinctrl driver for UltraRISC DP1000 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-dp1000. diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc= /Makefile new file mode 100644 index 000000000000..5d49ce1c0af9 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_PINCTRL_ULTRARISC) +=3D pinctrl-ultrarisc.o +obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) +=3D pinctrl-dp1000.o diff --git a/drivers/pinctrl/ultrarisc/pinctrl-dp1000.c b/drivers/pinctrl/u= ltrarisc/pinctrl-dp1000.c new file mode 100644 index 000000000000..23b6cc512031 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-dp1000.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang + */ + +#include +#include +#include + +#include "pinctrl-ultrarisc.h" + +static const struct pinctrl_pin_desc ur_dp1000_pins[] =3D { + PINCTRL_PIN(0, "PA0"), + PINCTRL_PIN(1, "PA1"), + PINCTRL_PIN(2, "PA2"), + PINCTRL_PIN(3, "PA3"), + PINCTRL_PIN(4, "PA4"), + PINCTRL_PIN(5, "PA5"), + PINCTRL_PIN(6, "PA6"), + PINCTRL_PIN(7, "PA7"), + PINCTRL_PIN(8, "PA8"), + PINCTRL_PIN(9, "PA9"), + PINCTRL_PIN(10, "PA10"), + PINCTRL_PIN(11, "PA11"), + PINCTRL_PIN(12, "PA12"), + PINCTRL_PIN(13, "PA13"), + PINCTRL_PIN(14, "PA14"), + PINCTRL_PIN(15, "PA15"), + PINCTRL_PIN(16, "PB0"), + PINCTRL_PIN(17, "PB1"), + PINCTRL_PIN(18, "PB2"), + PINCTRL_PIN(19, "PB3"), + PINCTRL_PIN(20, "PB4"), + PINCTRL_PIN(21, "PB5"), + PINCTRL_PIN(22, "PB6"), + PINCTRL_PIN(23, "PB7"), + PINCTRL_PIN(24, "PC0"), + PINCTRL_PIN(25, "PC1"), + PINCTRL_PIN(26, "PC2"), + PINCTRL_PIN(27, "PC3"), + PINCTRL_PIN(28, "PC4"), + PINCTRL_PIN(29, "PC5"), + PINCTRL_PIN(30, "PC6"), + PINCTRL_PIN(31, "PC7"), + PINCTRL_PIN(32, "PD0"), + PINCTRL_PIN(33, "PD1"), + PINCTRL_PIN(34, "PD2"), + PINCTRL_PIN(35, "PD3"), + PINCTRL_PIN(36, "PD4"), + PINCTRL_PIN(37, "PD5"), + PINCTRL_PIN(38, "PD6"), + PINCTRL_PIN(39, "PD7"), + PINCTRL_PIN(40, "LPC0"), + PINCTRL_PIN(41, "LPC1"), + PINCTRL_PIN(42, "LPC2"), + PINCTRL_PIN(43, "LPC3"), + PINCTRL_PIN(44, "LPC4"), + PINCTRL_PIN(45, "LPC5"), + PINCTRL_PIN(46, "LPC6"), + PINCTRL_PIN(47, "LPC7"), + PINCTRL_PIN(48, "LPC8"), + PINCTRL_PIN(49, "LPC9"), + PINCTRL_PIN(50, "LPC10"), + PINCTRL_PIN(51, "LPC11"), + PINCTRL_PIN(52, "LPC12"), +}; + +static const struct ur_function_desc ur_dp1000_functions[] =3D { + { "gpio", UR_FUNC_DEF, true }, + { "func0", UR_FUNC0, false }, + { "func1", UR_FUNC1, false }, +}; + +#define UR_DP1000_PORT(_name, _npins, _func, _conf, _modes) \ + { .name =3D (_name), .npins =3D (_npins), .func_offset =3D (_func), \ + .conf_offset =3D (_conf), .supported_modes =3D (_modes) } + +static const struct ur_pinctrl_match_data ur_dp1000_match_data =3D { + .pins =3D ur_dp1000_pins, + .npins =3D ARRAY_SIZE(ur_dp1000_pins), + .functions =3D ur_dp1000_functions, + .num_functions =3D ARRAY_SIZE(ur_dp1000_functions), + .num_ports =3D 5, + .ports =3D { + UR_DP1000_PORT("A", 16, 0x2c0, 0x310, UR_FUNC0 | UR_FUNC1), + UR_DP1000_PORT("B", 8, 0x2c4, 0x318, UR_FUNC0 | UR_FUNC1), + UR_DP1000_PORT("C", 8, 0x2c8, 0x31c, UR_FUNC0 | UR_FUNC1), + UR_DP1000_PORT("D", 8, 0x2cc, 0x320, UR_FUNC0 | UR_FUNC1), + UR_DP1000_PORT("LPC", 13, 0x2d0, 0x324, UR_FUNC0), + }, +}; + +static const struct of_device_id ur_pinctrl_of_match[] =3D { + { .compatible =3D "ultrarisc,dp1000-pinctrl", .data =3D &ur_dp1000_match_= data, }, + { } +}; +MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); + +static struct platform_driver ur_pinctrl_driver =3D { + .driver =3D { + .name =3D "ultrarisc-pinctrl-dp1000", + .of_match_table =3D ur_pinctrl_of_match, + }, + .probe =3D ur_pinctrl_probe, +}; + +module_platform_driver(ur_pinctrl_driver); + +MODULE_DESCRIPTION("UltraRISC DP1000 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctr= l/ultrarisc/pinctrl-ultrarisc.c new file mode 100644 index 000000000000..774746943e28 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c @@ -0,0 +1,746 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../devicetree.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" + +#include "pinctrl-ultrarisc.h" + +#define UR_CONF_BIT_PER_PIN 4 +#define UR_CONF_PIN_PER_REG (32 / UR_CONF_BIT_PER_PIN) +static const int ur_drive_strengths[] =3D { 20, 27, 33, 40 }; + +static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *matc= h_data, + struct ur_pin_val *pin_val, u32 pin_num) +{ + for (u32 i =3D 0; i < match_data->num_ports; i++) { + if (pin_num < match_data->ports[i].npins) { + pin_val->port =3D i; + pin_val->pin =3D pin_num; + return 0; + } + pin_num -=3D match_data->ports[i].npins; + } + + return -EINVAL; +} + +static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *= pin_val) +{ + struct ur_pinctrl *ur_pinctrl =3D pinctrl_dev_get_drvdata(pctldev); + int index =3D 0; + + for (u32 i =3D 0; i < pin_val->port; i++) + index +=3D ur_pinctrl->match_data->ports[i].npins; + + return index + pin_val->pin; +} + +static u32 ur_get_pin_conf_offset(const struct ur_port_desc *port_desc, u3= 2 pin) +{ + return port_desc->conf_offset + + (pin / UR_CONF_PIN_PER_REG) * sizeof(u32); +} + +static u32 ur_read_pin_conf(struct ur_pinctrl *pctldata, unsigned int pin) +{ + const struct ur_port_desc *port_desc; + struct ur_pin_val pin_val; + u32 reg_offset; + u32 shift; + u32 conf; + u32 mask; + + if (ur_pin_num_to_port_pin(pctldata->match_data, &pin_val, pin)) + return 0; + + port_desc =3D &pctldata->match_data->ports[pin_val.port]; + reg_offset =3D ur_get_pin_conf_offset(port_desc, pin_val.pin); + shift =3D (pin_val.pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + mask =3D GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; + conf =3D field_get(mask, readl_relaxed(pctldata->base + reg_offset)); + + return conf; +} + +static int ur_write_pin_conf(struct ur_pinctrl *pctldata, unsigned int pin= , u32 conf) +{ + const struct ur_port_desc *port_desc; + struct ur_pin_val pin_val; + unsigned long flags; + void __iomem *reg; + u32 reg_offset; + u32 val; + u32 shift; + u32 mask; + + if (ur_pin_num_to_port_pin(pctldata->match_data, &pin_val, pin)) + return -EINVAL; + + port_desc =3D &pctldata->match_data->ports[pin_val.port]; + reg_offset =3D ur_get_pin_conf_offset(port_desc, pin_val.pin); + reg =3D pctldata->base + reg_offset; + shift =3D (pin_val.pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + mask =3D GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; + + raw_spin_lock_irqsave(&pctldata->lock, flags); + val =3D readl_relaxed(reg); + val =3D (val & ~mask) | field_prep(mask, conf); + writel_relaxed(val, reg); + raw_spin_unlock_irqrestore(&pctldata->lock, flags); + + return 0; +} + +static int ur_set_pin_mux(struct ur_pinctrl *pctldata, struct ur_pin_val *= pin_val) +{ + const struct ur_port_desc *port_desc =3D &pctldata->match_data->ports[pin= _val->port]; + void __iomem *reg =3D pctldata->base + port_desc->func_offset; + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&pctldata->lock, flags); + val =3D readl_relaxed(reg); + val &=3D ~((UR_FUNC0 | UR_FUNC1) << pin_val->pin); + val |=3D pin_val->mode << pin_val->pin; + writel_relaxed(val, reg); + raw_spin_unlock_irqrestore(&pctldata->lock, flags); + + return 0; +} + +static int ur_set_pin_mux_by_num(struct ur_pinctrl *pctldata, unsigned int= pin, u32 mode) +{ + struct ur_pin_val pin_val =3D { .mode =3D mode }; + const struct ur_port_desc *port_desc; + int ret; + + ret =3D ur_pin_num_to_port_pin(pctldata->match_data, &pin_val, pin); + if (ret) + return ret; + + port_desc =3D &pctldata->match_data->ports[pin_val.port]; + if (mode !=3D UR_FUNC_DEF && !(port_desc->supported_modes & mode)) + return -EINVAL; + + return ur_set_pin_mux(pctldata, &pin_val); +} + +static int ur_hw_to_config(unsigned long *config, u32 conf) +{ + enum pin_config_param param =3D pinconf_to_config_param(*config); + u32 drive =3D FIELD_GET(UR_DRIVE_MASK, conf); + u32 pull =3D FIELD_GET(UR_PULL_MASK, conf); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (pull !=3D UR_PULL_DIS) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull !=3D UR_PULL_UP) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (pull !=3D UR_PULL_DOWN) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_DRIVE_STRENGTH: + if (drive >=3D ARRAY_SIZE(ur_drive_strengths)) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, ur_drive_strengths[drive]); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int ur_config_to_hw(unsigned long config, u32 *conf) +{ + enum pin_config_param param =3D pinconf_to_config_param(config); + u32 arg =3D pinconf_to_config_argument(config); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DIS); + return 0; + case PIN_CONFIG_BIAS_PULL_UP: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_UP); + return 0; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DOWN); + return 0; + case PIN_CONFIG_DRIVE_STRENGTH: + for (u32 i =3D 0; i < ARRAY_SIZE(ur_drive_strengths); i++) { + if (ur_drive_strengths[i] !=3D arg) + continue; + FIELD_MODIFY(UR_DRIVE_MASK, conf, i); + return 0; + } + return -EINVAL; + case PIN_CONFIG_DRIVE_PUSH_PULL: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_PERSIST_STATE: + return 0; + default: + return -EOPNOTSUPP; + } +} + +struct ur_legacy_prop_data { + struct ur_pin_val *pin_vals; + unsigned int *group_pins; + unsigned int num_pins; +}; + +static int ur_legacy_parse_prop(struct pinctrl_dev *pctldev, + struct device_node *np, + const char *propname, + struct ur_legacy_prop_data *prop) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + int rows; + + rows =3D pinctrl_count_index_with_args(np, propname); + if (rows < 0) + return dev_err_probe(pctldev->dev, rows, "%pOF: invalid %s count\n", + np, propname); + + prop->pin_vals =3D devm_kcalloc(pctldev->dev, rows, sizeof(*prop->pin_val= s), + GFP_KERNEL); + if (!prop->pin_vals) + return -ENOMEM; + + prop->group_pins =3D devm_kcalloc(pctldev->dev, rows, sizeof(*prop->group= _pins), + GFP_KERNEL); + if (!prop->group_pins) + return -ENOMEM; + + prop->num_pins =3D rows; + + for (int i =3D 0; i < rows; i++) { + struct of_phandle_args pin_args; + int ret; + + ret =3D pinctrl_parse_index_with_args(np, propname, i, &pin_args); + if (ret) + return dev_err_probe(pctldev->dev, ret, + "%pOF: failed to parse %s[%d]\n", + np, propname, i); + + if (pin_args.args_count !=3D 3) + return dev_err_probe(pctldev->dev, -EINVAL, + "%pOF: invalid %s[%d] args_count=3D%d\n", + np, propname, i, pin_args.args_count); + + prop->pin_vals[i].port =3D pin_args.args[0]; + prop->pin_vals[i].pin =3D pin_args.args[1]; + prop->pin_vals[i].mode =3D pin_args.args[2]; + + if (prop->pin_vals[i].port >=3D pctldata->match_data->num_ports) + return dev_err_probe(pctldev->dev, -EINVAL, + "%pOF: invalid %s[%d] port=3D%u\n", + np, propname, i, prop->pin_vals[i].port); + + if (prop->pin_vals[i].pin >=3D + pctldata->match_data->ports[prop->pin_vals[i].port].npins) + return dev_err_probe(pctldev->dev, -EINVAL, + "%pOF: invalid %s[%d] pin=3D%u\n", + np, propname, i, prop->pin_vals[i].pin); + + prop->group_pins[i] =3D ur_pin_to_desc(pctldev, &prop->pin_vals[i]); + } + + return 0; +} + +static const char *ur_legacy_get_function_name(const struct ur_pinctrl_mat= ch_data *match_data, + u32 mode) +{ + for (u32 i =3D 0; i < match_data->num_functions; i++) { + if (match_data->functions[i].mode =3D=3D mode) + return match_data->functions[i].name; + } + + return NULL; +} + +static int ur_legacy_conf_to_configs(struct pinctrl_dev *pctldev, u32 conf, + unsigned long **configs, + unsigned int *num_configs) +{ + u32 drive =3D FIELD_GET(UR_DRIVE_MASK, conf); + u32 pull =3D FIELD_GET(UR_PULL_MASK, conf); + unsigned long config; + int ret; + + switch (pull) { + case UR_PULL_DIS: + config =3D pinconf_to_config_packed(PIN_CONFIG_BIAS_DISABLE, 1); + break; + case UR_PULL_UP: + config =3D pinconf_to_config_packed(PIN_CONFIG_BIAS_PULL_UP, 1); + break; + case UR_PULL_DOWN: + config =3D pinconf_to_config_packed(PIN_CONFIG_BIAS_PULL_DOWN, 1); + break; + default: + return -EINVAL; + } + + ret =3D pinctrl_utils_add_config(pctldev, configs, num_configs, config); + if (ret) + return ret; + + if (drive >=3D ARRAY_SIZE(ur_drive_strengths)) + return -EINVAL; + + config =3D pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, + ur_drive_strengths[drive]); + + return pinctrl_utils_add_config(pctldev, configs, num_configs, config); +} + +static int ur_legacy_add_mux_maps(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps, + const struct ur_legacy_prop_data *prop) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + + for (u32 i =3D 0; i < prop->num_pins; i++) { + const char *function; + const char *group; + int ret; + + function =3D ur_legacy_get_function_name(pctldata->match_data, + prop->pin_vals[i].mode); + if (!function) + return -EINVAL; + + group =3D pctldata->match_data->pins[prop->group_pins[i]].name; + if (!group) + return -EINVAL; + + ret =3D pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, + num_maps, group, function); + if (ret) + return ret; + } + + return 0; +} + +static int ur_legacy_add_pinconf_maps(struct pinctrl_dev *pctldev, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps, + const struct ur_legacy_prop_data *prop) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + + for (u32 i =3D 0; i < prop->num_pins; i++) { + unsigned long *configs =3D NULL; + unsigned int num_configs =3D 0; + const char *group; + int ret; + + ret =3D ur_legacy_conf_to_configs(pctldev, prop->pin_vals[i].conf, + &configs, &num_configs); + if (ret) + goto err; + + group =3D pctldata->match_data->pins[prop->group_pins[i]].name; + if (!group) { + ret =3D -EINVAL; + goto err; + } + + ret =3D pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, + num_maps, group, configs, + num_configs, + PIN_MAP_TYPE_CONFIGS_PIN); +err: + kfree(configs); + if (ret) + return ret; + } + + return 0; +} + +static int ur_legacy_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct ur_legacy_prop_data conf_prop =3D {}; + struct ur_legacy_prop_data mux_prop =3D {}; + struct pinctrl_map *new_map =3D NULL; + unsigned int reserved_maps =3D 0; + unsigned int total_maps =3D 0; + bool conf_present =3D false; + bool mux_present =3D false; + unsigned int map_num =3D 0; + int ret; + + if (of_property_present(np, "pinctrl-pins")) + mux_present =3D true; + if (of_property_present(np, "pinconf-pins")) + conf_present =3D true; + if (!mux_present && !conf_present) + return -EINVAL; + + if (mux_present) { + ret =3D ur_legacy_parse_prop(pctldev, np, "pinctrl-pins", &mux_prop); + if (ret) + goto err; + total_maps +=3D mux_prop.num_pins; + } + + if (conf_present) { + ret =3D ur_legacy_parse_prop(pctldev, np, "pinconf-pins", &conf_prop); + if (ret) + goto err; + total_maps +=3D conf_prop.num_pins; + } + + ret =3D pinctrl_utils_reserve_map(pctldev, &new_map, &reserved_maps, + &map_num, total_maps); + if (ret) + goto err; + + if (mux_present) { + ret =3D ur_legacy_add_mux_maps(pctldev, &new_map, &reserved_maps, + &map_num, &mux_prop); + if (ret) + goto err; + } + + if (conf_present) { + ret =3D ur_legacy_add_pinconf_maps(pctldev, &new_map, &reserved_maps, + &map_num, &conf_prop); + if (ret) + goto err; + } + + *map =3D new_map; + *num_maps =3D map_num; + + return 0; + +err: + pinctrl_utils_free_map(pctldev, new_map, map_num); + return ret; +} + +static int ur_generic_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + bool legacy =3D of_property_present(np, "pinctrl-pins") || + of_property_present(np, "pinconf-pins"); + bool generic =3D of_property_present(np, "pins"); + + if (legacy && generic) { + dev_err(pctldev->dev, + "%pOF: mixed legacy and generic pinctrl properties are not supported\n", + np); + return -EINVAL; + } + + if (generic) + return ur_generic_dt_node_to_map(pctldev, np, map, num_maps); + + if (legacy) + return ur_legacy_dt_node_to_map(pctldev, np, map, num_maps); + + return -EINVAL; +} + +static void ur_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + pinctrl_utils_free_map(pctldev, map, num_maps); +} + +static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static const struct pinctrl_ops ur_pinctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .dt_node_to_map =3D ur_dt_node_to_map, + .dt_free_map =3D ur_dt_free_map, + .pin_dbg_show =3D ur_pin_dbg_show, +}; + +static int ur_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + + (void)range; + + return ur_set_pin_mux_by_num(pctldata, offset, UR_FUNC_DEF); +} + +static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selec= tor, + unsigned int group_selector) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + const struct ur_function_desc *desc; + const struct function_desc *func; + const unsigned int *pins; + unsigned int npins; + int ret; + + func =3D pinmux_generic_get_function(pctldev, func_selector); + if (!func || !func->data) + return -EINVAL; + + desc =3D func->data; + ret =3D pinctrl_generic_get_group_pins(pctldev, group_selector, &pins, &n= pins); + if (ret) + return ret; + + for (u32 i =3D 0; i < npins; i++) { + ret =3D ur_set_pin_mux_by_num(pctldata, pins[i], desc->mode); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinmux_ops ur_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .function_is_gpio =3D pinmux_generic_function_is_gpio, + .set_mux =3D ur_set_mux, + .gpio_request_enable =3D ur_gpio_request_enable, + .strict =3D true, +}; + +static int ur_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + + return ur_hw_to_config(config, ur_read_pin_conf(pctldata, pin)); +} + +static int ur_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct ur_pinctrl *pctldata =3D pinctrl_dev_get_drvdata(pctldev); + u32 conf =3D ur_read_pin_conf(pctldata, pin); + int ret; + + for (u32 i =3D 0; i < num_configs; i++) { + ret =3D ur_config_to_hw(configs[i], &conf); + if (ret) + return ret; + } + + return ur_write_pin_conf(pctldata, pin, conf); +} + +static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret || !npins) + return ret ?: -EINVAL; + + return ur_pin_config_get(pctldev, pins[0], config); +} + +static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (u32 i =3D 0; i < npins; i++) { + ret =3D ur_pin_config_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops ur_pinconf_ops =3D { + .pin_config_get =3D ur_pin_config_get, + .pin_config_set =3D ur_pin_config_set, + .pin_config_group_get =3D ur_pin_config_group_get, + .pin_config_group_set =3D ur_pin_config_group_set, +#ifdef CONFIG_GENERIC_PINCONF + .is_generic =3D true, +#endif +}; + +static int ur_add_pin_groups(struct ur_pinctrl *pctldata) +{ + for (u32 i =3D 0; i < pctldata->match_data->npins; i++) { + int ret; + + pctldata->group_names[i] =3D pctldata->match_data->pins[i].name; + pctldata->group_pins[i] =3D pctldata->match_data->pins[i].number; + + ret =3D pinctrl_generic_add_group(pctldata->pctl_dev, pctldata->group_na= mes[i], + &pctldata->group_pins[i], 1, NULL); + if (ret < 0) + return dev_err_probe(pctldata->dev, ret, + "failed to add pin group %s\n", + pctldata->group_names[i]); + } + + return 0; +} + +static int ur_add_functions(struct ur_pinctrl *pctldata) +{ + for (u32 i =3D 0; i < pctldata->match_data->num_functions; i++) { + const struct ur_function_desc *desc =3D &pctldata->match_data->functions= [i]; + struct pinfunction func =3D desc->gpio ? + PINCTRL_GPIO_PINFUNCTION(desc->name, pctldata->group_names, + pctldata->match_data->npins) : + PINCTRL_PINFUNCTION(desc->name, pctldata->group_names, + pctldata->match_data->npins); + int ret; + + ret =3D pinmux_generic_add_pinfunction(pctldata->pctl_dev, &func, (void = *)desc); + if (ret < 0) + return dev_err_probe(pctldata->dev, ret, + "failed to add function %s\n", + desc->name); + } + + return 0; +} + +int ur_pinctrl_probe(struct platform_device *pdev) +{ + const struct ur_pinctrl_match_data *match_data; + struct ur_pinctrl *pctldata; + struct pinctrl_desc *desc; + int ret; + + match_data =3D of_device_get_match_data(&pdev->dev); + if (!match_data) + return -ENODEV; + + desc =3D devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + pctldata =3D devm_kzalloc(&pdev->dev, sizeof(*pctldata), GFP_KERNEL); + if (!pctldata) + return -ENOMEM; + + pctldata->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctldata->base)) + return PTR_ERR(pctldata->base); + pctldata->dev =3D &pdev->dev; + pctldata->match_data =3D match_data; + pctldata->group_names =3D devm_kcalloc(&pdev->dev, match_data->npins, + sizeof(*pctldata->group_names), GFP_KERNEL); + if (!pctldata->group_names) + return -ENOMEM; + + pctldata->group_pins =3D devm_kcalloc(&pdev->dev, match_data->npins, + sizeof(*pctldata->group_pins), GFP_KERNEL); + if (!pctldata->group_pins) + return -ENOMEM; + + raw_spin_lock_init(&pctldata->lock); + + desc->name =3D dev_name(&pdev->dev); + desc->owner =3D THIS_MODULE; + desc->pins =3D match_data->pins; + desc->npins =3D match_data->npins; + desc->pctlops =3D &ur_pinctrl_ops; + desc->pmxops =3D &ur_pinmux_ops; + desc->confops =3D &ur_pinconf_ops; + + ret =3D devm_pinctrl_register_and_init(&pdev->dev, desc, pctldata, &pctld= ata->pctl_dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register pinctrl\n"); + + ret =3D ur_add_pin_groups(pctldata); + if (ret) + return ret; + + ret =3D ur_add_functions(pctldata); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctldata); + + return pinctrl_enable(pctldata->pctl_dev); +} +EXPORT_SYMBOL_GPL(ur_pinctrl_probe); + +MODULE_DESCRIPTION("UltraRISC pinctrl core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctr= l/ultrarisc/pinctrl-ultrarisc.h new file mode 100644 index 000000000000..25291f18c950 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang + */ + +#ifndef __PINCTRL_ULTRARISC_H__ +#define __PINCTRL_ULTRARISC_H__ + +#include +#include +#include + +struct platform_device; + +struct ur_pin_val { + u32 port; + u32 pin; + union { + u32 mode; + u32 conf; + }; +#define UR_FUNC_DEF 0 +#define UR_FUNC0 1 +#define UR_FUNC1 0x10000 + +#define UR_BIAS_MASK 0x0000000F +#define UR_PULL_MASK 0x0C +#define UR_PULL_DIS 0 +#define UR_PULL_UP 1 +#define UR_PULL_DOWN 2 +#define UR_DRIVE_MASK 0x03 +}; + +struct ur_port_desc { + const char *name; + u32 npins; + u32 func_offset; + u32 conf_offset; + u32 supported_modes; +}; + +struct ur_function_desc { + const char *name; + u32 mode; + bool gpio; +}; + +struct ur_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + u32 npins; + const struct ur_function_desc *functions; + u32 num_functions; + u32 num_ports; + struct ur_port_desc ports[]; +}; + +struct ur_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + void __iomem *base; + const struct ur_pinctrl_match_data *match_data; + raw_spinlock_t lock; + const char **group_names; + unsigned int *group_pins; +}; + +int ur_pinctrl_probe(struct platform_device *pdev); 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Fri, 15 May 2026 01:18:13 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:18:03 +0800 Subject: [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-7-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=5336; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=t/R0mLPTbNUZPAL58YRehEFOhBPdOUX92xeh2IinM2w=; b=bT1IuSu9q223icKQubL2BmVf3Yu/tWmMhB7XitawJ8tOZWGSfNzx/DGXFJHZ2lPy6MR+hq3Jp qnAT0mbxXslCKi23braHdfI83aXi4xEm+qG0hOSJAx3yGKwNTUuhFyb X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + .../dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi | 85 ++++++++++++++++ arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 +++++++++++++++++= ++++ 4 files changed, 199 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y +=3D spacemit subdir-y +=3D starfive subdir-y +=3D tenstorrent subdir-y +=3D thead +subdir-y +=3D ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile new file mode 100644 index 000000000000..d01a770d3cba --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-rongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi b/= arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..101b416b1079 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" + +&pmx0 { + i2c0_pins: i2c0-pins { + pins =3D "PA12", "PA13"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D "PB6", "PB7"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D "PC0", "PC1"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D "PC2", "PC3"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + pciex4a_link_pins: pciex4a-link-pins { + pins =3D "PC0"; + function =3D "func1"; + bias-pull-down; + drive-strength =3D <33>; + }; + + pciex4b_link_pins: pciex4b-link-pins { + pins =3D "PC1"; + function =3D "func1"; + bias-pull-down; + drive-strength =3D <33>; + }; + + spi0_pins: spi0-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7"; + function =3D "func1"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D "PA0", "PA1", "PA2", "PA3"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D "PA8", "PA9"; + function =3D "func1"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D "PB4", "PB5"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D "PC4", "PC5"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts b/arch/risc= v/boot/dts/ultrarisc/dp1000-rongda-m0.dts new file mode 100644 index 000000000000..6f72d60ad55e --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-rongda-m0-pinctrl.dtsi" +#include + +/ { + model =3D "Rongda M0 Board"; + compatible =3D "rongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-poweroff { + compatible =3D "gpio-poweroff"; + gpios =3D <&gpio_b 0 GPIO_ACTIVE_HIGH>; + active-delay-ms =3D <100>; + + status =3D "disabled"; + }; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio_b 1 GPIO_ACTIVE_HIGH>; + active-delay =3D <100>; + + status =3D "disabled"; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@32 { + compatible =3D "whwave,sd3078"; + reg =3D <0x32>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-8-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=7121; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=xX1Mb67eueb8njtg09s4f3y/jZXeNZx3JHf6ugsERgg=; b=hO9vbV/B71IzWvgeBG1C/Y3C9z9QXaKWDM4yTnc6xy/nC8RaxNRqRQQhO6Qf+AEN+QbbdWczR oBI7NBSDAL+AfHRZBimTcRSzhzmIknJrYko1v+ZssmHXmlxdUDdDzv7 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 107 ++++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 182 +++++++++++++++++= ++++ 3 files changed, 290 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile index d01a770d3cba..9c27256a2f67 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-rongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi = b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..053206190ec7 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" + +&pmx0 { + i2c0_pins: i2c0-pins { + pins =3D "PA12", "PA13"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D "PB6", "PB7"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D "PC0", "PC1"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D "PC2", "PC3"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + io_pins: io-pins { + pins =3D "PA10", "PA15", "PB0", "PB1", "PB2", "PD6", "PD7"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins =3D "PA4", "PA11", "PA14"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + mux_dcdc_pins: mux-dcdc-pins { + pins =3D "PA5"; + function =3D "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins =3D "PA6"; + function =3D "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins =3D "PA7"; + function =3D "gpio"; + }; + + spi0_pins: spi0-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5"; + function =3D "func1"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D "PA0", "PA1", "PA2", "PA3"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D "PA8", "PA9"; + function =3D "func1"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D "PB4", "PB5"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D "PC4", "PC5"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart3_pins: uart3-pins { + pins =3D "PC6", "PC7"; + function =3D "func0"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/ri= scv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..21d85c03abe1 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model =3D "Milk-V Titan"; + compatible =3D "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-poweroff { + compatible =3D "gpio-poweroff"; + gpios =3D <&gpio_b 0 GPIO_ACTIVE_LOW>; + active-delay-ms =3D <100>; + + status =3D "disabled"; + }; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio_b 1 GPIO_ACTIVE_LOW>; + active-delay =3D <100>; + + status =3D "disabled"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys_pins>; + + key-wakeup-0 { + label =3D "Wake-Up"; + gpios =3D <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-1 { + label =3D "Power"; + gpios =3D <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-2 { + label =3D "Wake-Up-by-USB"; + gpios =3D <&gpio_a 4 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@68 { + compatible =3D "st,m41t11"; + reg =3D <0x68>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; +}; + +&gpio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&io_pins &mux_dcdc_pins &mux_i2c3_pins &mux_uart0_pins>; +}; + +ðernet { + phy-handle =3D <&phy0>; + /* + * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii". + * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic. + */ + phy-mode =3D "rgmii"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@0 { + reg =3D <0x00>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + label =3D "eth-link"; + reg =3D <0x01>; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + + led@2 { + label =3D "eth-activity"; + reg =3D <0x02>; + color =3D ; + function =3D LED_FUNCTION_ACTIVITY; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; --=20 2.34.1 From nobody Fri Jun 12 12:47:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95C1537106D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k4qWHYA7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5F7B7C4AF0C; Fri, 15 May 2026 01:18:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778807893; bh=jseFc3n5cwC0kdVmMRsSBaoSA7xjf+l4Q0DXJP129kc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=k4qWHYA7Yk+41PPDXrsZapPg/ye7FGUUMaCrgX9528FyDJBqbfStsfWT/vn9sF8ia VEoVycf/kw/BgjiRdwiSoFe3jl2d16uAONW+BMxhx9Rq8inIjRLancdqFNI465MNqA JIopc6IVKHxl+P1lcz20GeUKPwBQtcdw14ea15eNvFAYLQxoaWJ+aYYBFXFSatkR5t Q87PO5QCObH7WjB9xwmI6JeOqeG50K/5CoJ8LdmlSg5AQA2cZ7XD8UPhQ6zY+QI2iR J9UgyAy0KXtFtgHXbe/Kn+3TCBP7hJr6mdI6p0fc4mWLLb3SsNFrghrqDuEiIWyMBC VwN1cqoezvu7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 562FFCD37AC; Fri, 15 May 2026 01:18:13 +0000 (UTC) From: Jia Wang via B4 Relay Date: Fri, 15 May 2026 09:18:05 +0800 Subject: [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260515-ultrarisc-pinctrl-v1-9-bf559589ea8a@ultrarisc.com> References: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Linus Walleij , Bartosz Golaszewski , Samuel Holland Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1778807890; l=681; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=mQUrNpHmImAQll8Ku4hP3FOcTP1mWHcrN/GQ55X+mwU=; b=rW2qhP7IrKxExw+g4gJleU/MrAUEhaKmMhuGcdOG+RtY0KMyatlMSfNTeHSuSxbWMM36rDjGg hsqzqaDJQN0BUcaVrGPI7kuRezqEaJ8TXYPwir9hh3/UGPzd5k3Q2ZQ X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Enable `ARCH_ULTRARISC` in the default RISC-V defconfig. Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-1-98935f6cdfb= 5@ultrarisc.com/ Signed-off-by: Jia Wang --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index c2c37327b987..9fdc4d1831ed 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_SOC_STARFIVE=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_TENSTORRENT=3Dy CONFIG_ARCH_THEAD=3Dy +CONFIG_ARCH_ULTRARISC=3Dy CONFIG_ARCH_VIRT=3Dy CONFIG_ARCH_CANAAN=3Dy CONFIG_SMP=3Dy --=20 2.34.1