From nobody Fri Jun 12 12:48:49 2026 Received: from mail-106121.protonmail.ch (mail-106121.protonmail.ch [79.135.106.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D5313DEACB for ; Fri, 15 May 2026 05:08:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.121 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821722; cv=none; b=L+Rgcna66PUdhCeuOHLlyzbk/D7wo5re0KEjGpgYL7ch2dOTSSaLYJu8RIrBC01DXAK//H2TJKWokP5SAiT1Q10YpG7kAFBjFg1FNag3zkBSiWC0XsZYK5gEYoCG5hftFCav04ucXaHpcpj3LBJcx0ea9HKNe94nJY8jFr1o09A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821722; c=relaxed/simple; bh=ZPDzxzNkMskjLOEcF6bpBPV7fYkrTOkqVFWAURsyI6s=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rW1q0X31K2uMMHgmMZ5AYQ8PjJZvMgvzSAf5D+ia0OJ8MCEVJt4wpaAEGIVlZae8WcgpDnKzoIUUy8cpZeDNt5uBzBCZojYsIDpVRdltvbhWV+QZKm2w2Y8+e3CsNtMPZOxqB8Zj19K0DycLiQjuz6Jh82a0Bpbj3U4WdlNWNRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=X189sRUn; arc=none smtp.client-ip=79.135.106.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="X189sRUn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821712; x=1779080912; bh=pv/F1PPV1Zi+/q9n2GNINyeWZvEso37phWI69dlZ4Wg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=X189sRUnIOmn2B6pl10Bjwu9Pr2mHU8pxOGBiQ2Qh1ci9G81T/uJ3HOC0+qjcBxER rf1OLSPUaGC1dKa7eMluxHFJDugYgK2CQXS+QK/TmwFCbygJt7BUKl7qIK52r4sJCF E/J3Z0nLziLix+MbPHGsEYLEneJ30TSaaLu8yhEQzsZh/y9t8k1Iha1FDiT5CVDG1y +9LDFInHQRsTLhnAxVM2ZaOq3mPs8/ZJOZGI6pWkhl4U0FT83IrkK0GywDI6EObjXp LY6X9auerdYTueyvIopixjSn/QWpq2rsxiaq5Osi64r/U5bMiXTYNCzLOlbBq4pPkj lJPE2aKRdbZrw== Date: Fri, 15 May 2026 05:08:24 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Krzysztof Kozlowski Subject: [PATCH RFC v6 1/7] dt-bindings: display/msm/gmu: Document Adreno 810 GMU Message-ID: <20260515-adreno-810-v6-1-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 7d369594815313d6516ace44ebba579508e341ca Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Adreno 810 GMU in the dt-binding specification. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Koskovich Reviewed-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gmu.yaml | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index 93e5e6e19754..8578c2f8122e 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -300,6 +300,36 @@ allOf: required: - qcom,qmp =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-810.0 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - if: properties: compatible: --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-244103.protonmail.ch (mail-244103.protonmail.ch [109.224.244.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F671175A64 for ; Fri, 15 May 2026 05:17:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.103 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778822274; cv=none; b=lKxk7t4k2IzzUDu9tvg26iMXkFxnQh5g35gU67D/wWGHSXARzcNHXqQU9hPi/GS3HWppprmM7wPyNMCAWh4rKwwj3KHLCBK1T5UkLIAvJwUSRo7gVV4NHc65jFaaPhD8wWrNy1ZSB5TQ5Cgr2HDEfO2sqoFvEwS5+Bp7z0QWC7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778822274; c=relaxed/simple; bh=Azu0XRvCkmyNZahZrQEaamecpEr5Ild99+NQ1TvFI00=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o+xXBBUVkFOiRk/7g+3BYmDcrLwlp63I/DtkyEJy88tk2MPQfKvtJT0BHXmjv/LvzGISn8Kr4QlRJI7nyuUodogvh641eaeiC4OtRozw3WvEaQtOI7qRd28K4lrPNs4UPTgaG5ZLAytwhPsXSAsAdEWLdWT2CqUFYYPNcrUtsj8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=gefiTsHB; arc=none smtp.client-ip=109.224.244.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="gefiTsHB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821719; x=1779080919; bh=tTGGp9tpW+UaiFNc212qlp/NLmpaLC1hIuxmeV+7WaU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=gefiTsHB9uSN8S6Bthb4UwZHzXrD6hE1hsyGiLaqCqmTodq0Y5uzph2XBz+lg+Ws3 T62B8hdJvXPbju4/D1lH15eiiUsWKl1D9eDfvM5gjECfWbXSjuVbZ3boDN5J6MxzzY wRYj4pTeVjxoByxkcQ04RFVaImo7rCiKBn09tx3nQ4YPzVjh3elAzk4ARwKQUkW+Pn 63LsFGeRbPyxKC69xMwuBRZIBUogkrDkQtAp0D45dFNwfdPyAXPNslObmv3HyzuX9g /6Wc1x3TZzubjnOWfR03QxEbuFYWbcuBRq3Gq9BMA81cSCODgkjSq79KW9BY8GhfJg QuPhWZ4O6fAQQ== Date: Fri, 15 May 2026 05:08:35 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH RFC v6 2/7] dt-bindings: display/msm/gpu: Document Adreno 810 GPU Message-ID: <20260515-adreno-810-v6-2-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 28d789b8b45c78c3903495463b1d0d9f6703e962 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the GPU compatible string used for the Adreno 810. Signed-off-by: Alexander Koskovich Reviewed-by: Akhil P Oommen --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index e67cd708dda2..1ee2f1d57f12 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -415,7 +415,9 @@ allOf: properties: compatible: contains: - const: qcom,adreno-44070001 + enum: + - qcom,adreno-44010000 + - qcom,adreno-44070001 then: properties: reg: @@ -450,6 +452,7 @@ allOf: - qcom,adreno-43050a01 - qcom,adreno-43050c01 - qcom,adreno-43051401 + - qcom,adreno-44010000 - qcom,adreno-44070001 =20 then: # Starting with A6xx, the clocks are usually defined in the GMU = node --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54BC437B00E for ; Fri, 15 May 2026 05:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821740; cv=none; b=okKzh+9o6Qytettu8ASko7XrzliUThsw9DHLee5iX0SamAqaoHTKOhHE6ueG2bRT7+bJSRYctFM8m3xqS+CXCJWV29npmwwgn63OEXuBYoZX/XqMpb4K1rnQA6zVejuCvwt2mWeCxPmLAwt+6649W//FBU02fI8fsQsJFkos5mw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821740; c=relaxed/simple; bh=4njR83ReHtTxAGSERtPXE5nz1HwBlMvBBvoWK2UHSoc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B4dQglQnnEJyNNcWjaqeG3U6LvR6O+sPx2xTkiHnbQ39MPn95E72Vb7+u+sTeUJbY6ykniCXBLIrJLYIHQdRUkNRdgho5NmUbNIBkQ1Kx05Y2/ER8UxehdwpnRQFavpA2n85LwK/ZHcjIhRO/jizIEMY5c0wANIGzCZTmhJOikc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=FJbeot6I; arc=none smtp.client-ip=79.135.106.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="FJbeot6I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821731; x=1779080931; bh=b1UN8s0FVtgDhPzEDofNcgA1eauKP3PgpZdT/99HGUo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=FJbeot6I6Vg1YbVdSx0QVHij5KeFb0rkKo0zh0mnCz/ssjixYM7IP08Q1hIR0Ns8a W7eV80YiF5Gegh+QsZhGh8LV2palAQzOm0I6i/s6v916/a88rldSnQvSOOqMCaU/x0 hpAB+MaQiZ2yIdeygh9lBDbDImcnQ893jfr1T2vmYQI2v1lGK5nhcWdD5D2gGAvE6b XCCspW1TlGGe06XZdXB2ag9rOScizxmp0V64V30iQy1qutue5pvH4O9tuAe6ea7uaG eN5nHwWh2AqaaWGbH2qi0/4X9FD+xO7z+3yLyGBuU7V/MJI+ew764n3t8GNF20DYCw LqWsYPf3V3suQ== Date: Fri, 15 May 2026 05:08:46 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v6 3/7] drm/msm/adreno: rename llc_mmio to cx_misc_mmio Message-ID: <20260515-adreno-810-v6-3-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: ceec21b396966db4cd1e35073351dc773a7ecaaa Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This region is used for more than just LLCC, it also provides access to software fuse values (raytracing, etc). Rename relevant symbols from _llc to _cx_misc for use in a follow up change that decouples this from LLCC. Reviewed-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++-------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++------- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 616198a836a4..515656ec06bb 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 @@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) if (!qcom_scm_is_available()) { dev_warn_once(gpu->dev->dev, "SCM is not available, poking fuse register\n"); - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); @@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) * firmware, find out whether that's the case. The scm call * above sets the fuse register. */ - fuse_val =3D a6xx_llc_read(a6xx_gpu, + fuse_val =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); adreno_gpu->has_ray_tracing =3D !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); @@ -1343,7 +1343,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 /* Check to see if we are doing a cold or warm boot */ if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? + status =3D a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) = =3D=3D 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { status =3D gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) =3D=3D 1 ? diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d5aba072f44c..4275c1d726b2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2078,14 +2078,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx= _gpu) * pagetables */ if (!a6xx_gpu->have_mmu500) { - a6xx_llc_write(a6xx_gpu, + a6xx_cx_misc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); =20 /* * Program cacheability overrides to not allocate cache * lines on a write miss */ - a6xx_llc_rmw(a6xx_gpu, + a6xx_cx_misc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); return; } @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_misc_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2151,15 +2151,15 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, of_node_put(phandle); =20 if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->llc_mmio =3D msm_ioremap(pdev, "cx_mem"); + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); else - a6xx_gpu->llc_mmio =3D NULL; + a6xx_gpu->cx_misc_mmio =3D NULL; =20 a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); =20 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); + a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2560,7 +2560,7 @@ static int a6xx_read_speedbin(struct device *dev, str= uct a6xx_gpu *a6xx_gpu, return ret; =20 if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { - *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMI= T_STATUS); + *speedbin =3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_= LIMIT_STATUS); *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*spe= edbin); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eb431e5e00b1..648608c1c98e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -102,7 +102,7 @@ struct a6xx_gpu { =20 bool has_whereami; =20 - void __iomem *llc_mmio; + void __iomem *cx_misc_mmio; void *llc_slice; void *htw_llc_slice; bool have_mmu500; @@ -240,19 +240,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *g= pu) return true; } =20 -static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 ma= sk, u32 or) +static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u3= 2 mask, u32 or) { - return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); + return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or); } =20 -static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) { - return readl(a6xx_gpu->llc_mmio + (reg << 2)); + return readl(a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 -static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 = value) +static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, = u32 value) { - writel(value, a6xx_gpu->llc_mmio + (reg << 2)); + writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2)); } =20 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 9b99ec5ceeb5..d519a29573a1 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -104,7 +104,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) return; } =20 - slice_mask &=3D a6xx_llc_read(a6xx_gpu, + slice_mask &=3D a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); =20 a6xx_gpu->slice_mask =3D slice_mask; --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-05.mail-europe.com (mail-05.mail-europe.com [85.9.206.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 566DA3CF977; Fri, 15 May 2026 05:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.9.206.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821770; cv=none; b=rPvdghHu+JvBFvLphJmmNmuy6aaEufFjmW9YibqTKw1WM+TDN1U77Te8lmIJRKSoUdVGnrSY8BbqEsKvUlBHRo/CF7EFhclCKf6SVUtkPnr/KsyjfdADt9ks99kEy3kOL2h6cydes5/TLzlpTsMwowQFatUia2UcJET+/5Eq6/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821770; c=relaxed/simple; bh=Tpnj9uF4ZKfxDszPrsQeXalLh7hFaXn6bvO+xHvviac=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MoHVUNY5X+AJuwQm79FGKmhgKYFbtm8JLpehu/D2ITl1IEQLbpvqyUr+6drraXjoQFonCCO4YH3c377OY+NK1LYz3lk4WQKMbhSNp454YOYsXe22s0OHhscfcY7VZQreekToS0EHWOS4kNtnrqGJsb6JdNCGUN73GYMTlhOjulo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=mmSf61i2; arc=none smtp.client-ip=85.9.206.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="mmSf61i2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821750; x=1779080950; bh=Tpnj9uF4ZKfxDszPrsQeXalLh7hFaXn6bvO+xHvviac=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=mmSf61i2FA4rJVGVdOSLhpmdvwsyI3z54zwAv5aagWgvpbzwQ8jEJTAObvM1vNRIk gqyfKW9QhHNIjGmhCNUo29wX27CqUbhdYoCi5reSLT/CjcOnM9Cvzl8dwK4l0V/Jvd 0ZQpEoXMI5YQ04k97gGAbU8jmQcpeiJWcwbZFTDzyymvXmOLH8q1vxHJDur2vQ7uuS XNhcGXajsdA0+qAaZAFO0403dGFvdwquEgqYKD/CgO5AulXlRimZUR3lvAPpNHnakA NYsvSJPsQ4R/rSyQX1q3qIJhKJZKQ6reYorVsg23wmCo0MkOTa9xLbnwclQ/CZZvaX 2QpxCMReWEiaw== Date: Fri, 15 May 2026 05:08:56 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v6 4/7] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Message-ID: <20260515-adreno-810-v6-4-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: f8a9fe4628bf3206e3a6fa5585c2375f2a5560a0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 4275c1d726b2..533272e11111 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { - struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) return; =20 - /* - * There is a different programming path for A6xx targets with an - * mmu500 attached, so detect if that is the case - */ - phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); - a6xx_gpu->have_mmu500 =3D (phandle && - of_device_is_compatible(phandle, "arm,mmu-500")); - of_node_put(phandle); - - if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); - else - a6xx_gpu->cx_misc_mmio =3D NULL; - a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; const struct adreno_info *info =3D config->info; + struct device_node *phandle; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2657,6 +2639,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 + /* + * There is a different programming path for A6xx targets with an + * mmu500 attached, so detect if that is the case + */ + phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); + a6xx_gpu->have_mmu500 =3D (phandle && + of_device_is_compatible(phandle, "arm,mmu-500")); + of_node_put(phandle); + + if (is_a7xx || !a6xx_gpu->have_mmu500) + a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); + else + a6xx_gpu->cx_misc_mmio =3D NULL; + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D343C3DE454 for ; Fri, 15 May 2026 05:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821759; cv=none; b=e2IHY6rv+XjAwkle94VD3Zg0aDRsM5qaGQRheJSylILM3RLq4fSRK9ngUYGleZB+j+HqP8Z7C8Nel886HpfnMsq8CJaJsnpiLRHidjkBLIxPTpvVo5Odg+CI9g4uNdPcwaub1t2yWXZAiOelkMCq7+Vgg5zv2aUsQ8AI3iHzp3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821759; c=relaxed/simple; bh=wpiHLX1zWOUy8hBTDFwvSmMkzZNlxTZRLe+LwVa3mZQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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b=Ijru+n1yq4d5K79UiEOOTgNDmbbqldJazRLtiTFMNiV0aEzJHk52zV4v4flBwofmu 9nkUYrEgFphCTZB+igkolrAcEDn0o+N0f7V2dqjq5nJzKlWd3h+W49RTjRta19SYD3 x4UZ+t2oBiD9kY22uIHSBpVkgMPEoeG2dQKVk16wTIT+gDz50ObDeYspr4MZvGF7QY kp6/40NdAkHZA3CAdnLBzG0u3X/Hkp+9uaL9rjHO0QR8E9P5GHUQOhJqPKW2qyvGfm Oc/gdqtrF8kT4GAY1Hhkb9y0M96U4tnTmJ7hsZSC0CkxBOjWdo4lBxi2b9Xcm4dFC5 Y8x9Fsf897FcQ== Date: Fri, 15 May 2026 05:09:08 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v6 5/7] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Message-ID: <20260515-adreno-810-v6-5-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: deabef54c61baff43a06462424b7511c88efdcf4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index d519a29573a1..74802f330ae9 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -265,8 +265,8 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) * Last span feature is only supported on PIPE specific register. * So update those here */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 a8xx_aperture_clear(gpu); } --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-106118.protonmail.ch (mail-106118.protonmail.ch [79.135.106.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2583E3DEAD1 for ; Fri, 15 May 2026 05:09:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821773; cv=none; b=Vvyw482J40tBfD6CrsZkJERi9XA5IRmAvXLwiQhyI+aFUrSAvY76FU80hKON8kE8/mJiKO5f2wSPfhE1PpzqwxANWlAtm2dTP1Cfgrn09AYw5Ku+PfTrEE5GSLI0IGTEpkAYozwoET5h9kqdb1YqeblT2v9ErETPglbzmk8AEZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778821773; c=relaxed/simple; bh=/fZvmPQBnECgiBpRI4YxdLslErM79oMlwBF3AS5qL5o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZiGo2HRZ6weMJYK6iOu9bqiIbS49xVhhVSvySPdwjW9PydPzr1mpuY/NVgqSd2Jd1MRrJiWanrEITbF48snFStE3tZTKLrihpGwAw0y+CP5pIcL6A8nLE62i+1LXERVhPcBo17FouYbpUUp0hf4YN7PBX9DF98+ufH5zmdwr6eA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=eMvHdzX3; arc=none smtp.client-ip=79.135.106.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="eMvHdzX3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1778821768; x=1779080968; bh=/0oIkpOvGi8da+/dPiiWv3td9vDNvzL/PHE/qmbEj10=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=eMvHdzX3u6q4ixYW742xCQyhIcnqzyQ/+iqggVQev2v+ara+B6M4kfSQd70I3XVm2 rOgSPXFO2dnZNKor9hJsfJLOzObCLQ157+nFkt7IkuesCPoji4uhZKAJbQAKeoKH/e qfcC3s9cIsAt21hH/PMywPTLvItjv9sI7qIO4p9Vif29uMqiNjb6ct0+bncYckNfpX Qo9G9/Uhy1KFZj7b1IK3Sh4Keg6Oyy+hSaaHOTU0yozgVtK4eR4VYru+p5QhArPXBJ xI7sVKzCl3iBYzR6zvgPW8vhUUj/Ot9FJB/rXW0dzhYYg1BrdPIGDkTc5kxzKDY2t6 Fr+GOFxTIOqKQ== Date: Fri, 15 May 2026 05:09:20 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH RFC v6 6/7] drm/msm/adreno: add Adreno 810 GPU support Message-ID: <20260515-adreno-810-v6-6-fbe04c7203e1@pm.me> In-Reply-To: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 4fc6189ec4bd361cd6c5b83bd7f467b9ea7e519a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add catalog entry and register configuration for the Adreno 810 found in Qualcomm SM7635 (Milos) based devices. Signed-off-by: Alexander Koskovich Reviewed-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 298 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + 2 files changed, 303 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 550ff3a9b82e..3e6f409d13a2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1799,6 +1799,261 @@ static const struct adreno_reglist_pipe x285_dyn_pw= rup_reglist_regs[] =3D { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); =20 +static const struct adreno_reglist_pipe a810_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partia= l waves at VFD */ + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */ + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* + * BIT(22): Disable PS out of order retire + * BIT(23): Enable half wave mode and MM instruction src&dst is half prec= ision + */ + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + /* Disable write slow pointer in data phase queue */ + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) }, + { }, +}; + +static const u32 a810_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00000, 0x03a3), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0787), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x20000, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0381), + A6XX_PROTECT_NORDWR(0x27882, 0x0001), + A6XX_PROTECT_NORDWR(0x27c02, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a810_protect, 64); + +static const uint32_t a810_pwrup_reglist_regs[] =3D { + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_CCHE_TRAP_BASE, + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_HW_DBG_CNTL, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_READ_SEL, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist); + +static const u32 a810_ifpc_reglist_regs[] =3D { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(46), + REG_A8XX_CP_PROTECT_GLOBAL(47), + REG_A8XX_CP_PROTECT_GLOBAL(48), + REG_A8XX_CP_PROTECT_GLOBAL(49), + REG_A8XX_CP_PROTECT_GLOBAL(50), + REG_A8XX_CP_PROTECT_GLOBAL(51), + REG_A8XX_CP_PROTECT_GLOBAL(52), + REG_A8XX_CP_PROTECT_GLOBAL(53), + REG_A8XX_CP_PROTECT_GLOBAL(54), + REG_A8XX_CP_PROTECT_GLOBAL(55), + REG_A8XX_CP_PROTECT_GLOBAL(56), + REG_A8XX_CP_PROTECT_GLOBAL(57), + REG_A8XX_CP_PROTECT_GLOBAL(58), + REG_A8XX_CP_PROTECT_GLOBAL(59), + REG_A8XX_CP_PROTECT_GLOBAL(60), + REG_A8XX_CP_PROTECT_GLOBAL(61), + REG_A8XX_CP_PROTECT_GLOBAL(62), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist); + +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] =3D { + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE= _BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist); + static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -2193,6 +2448,48 @@ static const struct adreno_info a8xx_gpus[] =3D { { 252, 2 }, { 221, 3 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x44010000), + .family =3D ADRENO_8XX_GEN1, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80300_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80300_gmu.bin", + }, + .gmem =3D SZ_512K + SZ_64K, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs =3D &a8xx_gpu_funcs, + .zapfw =3D "gen80300_zap.mbn", + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &a810_protect, + .nonctxt_reglist =3D a810_nonctxt_regs, + .pwrup_reglist =3D &a810_pwrup_reglist, + .dyn_pwrup_reglist =3D &a810_dyn_pwrup_reglist, + .ifpc_reglist =3D &a810_ifpc_reglist, + .gbif_cx =3D a840_gbif, + .max_slices =3D 1, + .gmu_chipid =3D 0x8030000, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size =3D 4558 * SZ_1K, + .speedbins =3D ADRENO_SPEEDBINS( + { 0, 0 }, + { 242, 1 }, + { 221, 2 }, + ), } }; =20 @@ -2205,4 +2502,5 @@ static inline __always_unused void __build_asserts(vo= id) BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); + BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index ec643b84646b..d88eb8ecf417 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -592,6 +592,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_a810(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44010000; +} + static inline int adreno_is_x285(struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x44070001; --=20 2.53.0 From nobody Fri Jun 12 12:48:49 2026 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF7FE3CF67D; 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charset="utf-8" Add GPU and GMU devicetree nodes for the Adreno 810 GPU found on Qualcomm SM7635 (Milos) based devices. The qcom,kaanapali-gxclkctl.h header can be reused here because Milos uses the same driver and the GX_CLKCTL_GX_GDSC definition is identical. Signed-off-by: Alexander Koskovich Reviewed-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/milos.dtsi | 165 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 0e7cfc12b0d2..71fff0f35093 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss */ =20 +#include #include #include #include @@ -1554,6 +1555,121 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-44010000", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem"; + + interrupts =3D ; + + iommus =3D <&adreno_smmu 0 0x0>; + + operating-points-v2 =3D <&gpu_opp_table>; + + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + qcom,gmu =3D <&gmu>; + #cooling-cells =3D <2>; + + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2-adreno", + "operating-points-v2"; + + opp-264000000 { + opp-hz =3D /bits/ 64 <264000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136718>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0xc8295ffd>; + }; + + opp-362000000 { + opp-hz =3D /bits/ 64 <362000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136718>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0xc02c5ffd>; + }; + + opp-510000000 { + opp-hz =3D /bits/ 64 <510000000>; + opp-level =3D ; + opp-peak-kBps =3D <3972656>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0x882b5ffd>; + }; + + opp-644000000 { + opp-hz =3D /bits/ 64 <644000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0x882a5ffd>; + }; + + opp-688000000 { + opp-hz =3D /bits/ 64 <688000000>; + opp-level =3D ; + opp-peak-kBps =3D <6074218>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0x882a5ffd>; + }; + + opp-763000000 { + opp-hz =3D /bits/ 64 <763000000>; + opp-level =3D ; + opp-peak-kBps =3D <6671875>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0xa8295ffd>; + }; + + opp-895000000 { + opp-hz =3D /bits/ 64 <895000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0x88295ffd>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0xa8285ffd>; + }; + + opp-1050000000 { + opp-hz =3D /bits/ 64 <1050000000>; + opp-level =3D ; + opp-peak-kBps =3D <18597656>; + opp-supported-hw =3D <0x7>; + qcom,opp-acd-level =3D <0x88285ffd>; + }; + + opp-1150000000 { + opp-hz =3D /bits/ 64 <1150000000>; + opp-level =3D ; + opp-peak-kBps =3D <18597656>; + opp-supported-hw =3D <0x3>; + qcom,opp-acd-level =3D <0xa02f5ffd>; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible =3D "qcom,milos-gxclkctl"; reg =3D <0x0 0x03d64000 0x0 0x6000>; @@ -1564,6 +1680,55 @@ gxclkctl: clock-controller@3d64000 { #power-domain-cells =3D <1>; }; =20 + gmu: gmu@3d6c000 { + compatible =3D "qcom,adreno-gmu-810.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6c000 0x0 0x32000>; + reg-names =3D "gmu"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", + "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names =3D "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub"; + + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + iommus =3D <&adreno_smmu 5 0x0>; + + qcom,qmp =3D <&aoss_qmp>; + + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-350000000 { + opp-hz =3D /bits/ 64 <350000000>; + opp-level =3D ; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + opp-level =3D ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,milos-gpucc"; reg =3D <0x0 0x03d90000 0x0 0x9800>; --=20 2.53.0