From nobody Fri Jun 12 13:58:49 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C7333E0730; Thu, 14 May 2026 15:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778771639; cv=none; b=QF9vvGxLbt7Cv85QUhvXLXpTHgKE556P/QKFJirYE8cPry5TKC7DY2Roqbh1hZ1QN0hvtEeOFX1PPRDWUqUstAq1NZj7OKwhUgGtOuOgTYivR9TuYT20LmF+Aw9GByxlJ1nlS68dEpYf2OXsk28MSmXcHTE2xMoAINwhe0mY5bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778771639; c=relaxed/simple; bh=waINsKFbSyXcxAqUAzgj9r8Ga8BceWjqseF36ALPBz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dr9ZwFgKRbXQir0SsFRaEewQuNK4nbhTt6v0fF+YLtCfwi/a63SdEBqDAgMjOjOtxM4bzspMvi3cjpwnHspDALCv7066Tv5kg3LZW1wW4Q9tUhkbWmt2A7WiLqkutGNPvdGjk+9pM+MswAJo+DjRWAUs/uV3jDGnaCmPv7RhgOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=rC99kBpE; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="rC99kBpE" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8A12A3DE9FD; Thu, 14 May 2026 17:13:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778771619; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=IXgx7gfpsPR0kF8ck7MRUn7Q28yaC8th/9vky8kZIes=; b=rC99kBpEKBGa64ABDuQPgBe81fMPPr6gfCljJMEdZ5GznYse2DToXnWL74StzfSuu3RU+H Hv4CJ7RPv5blLgrh4mrM7qqVhvBHTcB/qHT07fAZy7AYk9OPP3XlBtQzW1Hcvqs4bzrJfU yfILM5+CV9zgoYVEK7bzfMHE3YqFE0VBJiptVNZdOMetLiAbF4dNdeIQk2FZC57VmWTFKQ WSUcjAJ2IxYtH3DMhQ0XVqeQY7U09FCYjLtt5jNAVWkYp2tvvHgchbbFGYjLIjAZHyQfkS PL5dy0e9RS0K2QVdYPXQotyEAvqYBjXP0hhZRR/gpsvfHthsA5XqlGsp1FaEIQ== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, helgaas@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle , Conor Dooley Subject: [PATCH v7 1/2] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Date: Thu, 14 May 2026 15:13:17 +0000 Message-Id: <20260514151318.3444959-2-cjd@cjdns.fr> In-Reply-To: <20260514151318.3444959-1-cjd@cjdns.fr> References: <20260514151318.3444959-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce EcoNet EN7528 SoC compatible in MediaTek PCIe controller binding. EcoNet PCIe controller has the same configuration model as Mediatek v2 but is initialized more similarly to an MT7621 PCIe. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/pci/mediatek-pcie.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index 0b8c78ec4f91..c009a7a52bc6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - airoha,an7583-pcie + - econet,en7528-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -226,6 +227,31 @@ allOf: =20 mediatek,pbus-csr: false =20 + - if: + properties: + compatible: + contains: + const: econet,en7528-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + resets: false + + reset-names: false + + power-domains: false + + mediatek,pbus-csr: false + + required: + - phys + - phy-names + unevaluatedProperties: false =20 examples: --=20 2.39.5 From nobody Fri Jun 12 13:58:49 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AD4B3112AD; Thu, 14 May 2026 15:13:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778771639; cv=none; b=VHpPbut8SvJnEFcZp3Sq43pr5NiyZ0GRYI30Y+m9HQuYfh8S7EvJGNUin9xJk85Q51O7i+RxnRnlx8AMxnIE8gzsy/3wNyEN3JRTQJbQDAO341L2Dl3/5PWwKw+fhHOU2wzRIqlsWgGRHKFcyBfRGuexLheUiuYCmuts4yOxEp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778771639; c=relaxed/simple; bh=2vxVWbCEFhroNy6FC1SCInMlHyLocFTO0lIu7nTbaV8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dvbOK2zG0E00T4h5FY6NvqQSbLV7UFlBt5apjOvu4Gqh5Ns3fjyX7vxCXugMvzzs54pegGngPQ2Km9GsMYNAzstBPsfgiiVVRQdUW5u6ygpMCm+YIi8UG03kY5SXqt/EcrfLqA++WslgyI6mFhLkKHoSbFltg7iqPX9D/9JGkMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=d7HHbXcB; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="d7HHbXcB" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D85A43DF5A3; Thu, 14 May 2026 17:13:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778771623; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=5YiLLvhj0LrC++mIg5Uun2rSHvq7Hc6ZeS3hm3nXW+Y=; b=d7HHbXcB4McBS/Q5wYwNAAxQ1pUntqKIFzhq0itPi7avZcI6So+ZQlOSqGTSq1BlH1Oa7O QLWklWR6hsV0Xlt0L9THKpDoY3BvodIrfbULiftm0UMewKdvs0UmF3Z0aViPOGTW0OAl5g dDagLHpLVvExr4eKgUkFGspaP4rK482nwLF55CTsdF7HiyfGveOf98+S9ZtsYjWocZFrdd Yqd2Y7tKbL7HWApIfA+uag36KLxJmKOO1q8U0SFG9x75sQN/4gpKYEYrndUcg6lHq3I5Mb lgzSHtsROT8UO7VMfB/Bwc2TY/ydqsMuU8K2w5ul5Bp+rDP1mYkfxwtwB8VQkw== From: Caleb James DeLisle To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com, ryder.lee@mediatek.com, helgaas@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ansuelsmth@gmail.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Caleb James DeLisle Subject: [PATCH v7 2/2] PCI: mediatek: Add support for EcoNet EN7528 SoC Date: Thu, 14 May 2026 15:13:18 +0000 Message-Id: <20260514151318.3444959-3-cjd@cjdns.fr> In-Reply-To: <20260514151318.3444959-1-cjd@cjdns.fr> References: <20260514151318.3444959-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs. These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports require re-training after startup. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef Signed-off-by: Caleb James DeLisle --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek.c | 155 +++++++++++++++++++++++++ 2 files changed, 156 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 2247709ef6d6..8a3a31b2bc12 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -209,7 +209,7 @@ config PCI_MVEBU =20 config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST depends on OF depends on PCI_MSI select IRQ_MSI_LIB diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 75722524fe74..3d5e2279286a 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -9,11 +9,13 @@ =20 #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -77,6 +79,7 @@ =20 #define PCIE_CONF_VEND_ID 0x100 #define PCIE_CONF_DEVICE_ID 0x102 +#define PCIE_CONF_REV_CLASS 0x104 #define PCIE_CONF_CLASS_ID 0x106 =20 #define PCIE_INT_MASK 0x420 @@ -89,6 +92,11 @@ #define MSI_MASK BIT(23) #define MTK_MSI_IRQS_NUM 32 =20 +#define EN7528_HOST_MODE 0x00804201 +#define EN7528_LINKUP_REG 0x50 +#define EN7528_RC0_LINKUP BIT(1) +#define EN7528_RC1_LINKUP BIT(2) + #define PCIE_AHB_TRANS_BASE0_L 0x438 #define PCIE_AHB_TRANS_BASE0_H 0x43c #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) @@ -148,12 +156,15 @@ struct mtk_pcie_port; * @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed * @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external = block * @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe + * @MTK_PCIE_RETRAIN: Retrain link to bridge after startup because some + * Gen2-capable devices start as Gen1. */ enum mtk_pcie_quirks { MTK_PCIE_FIX_CLASS_ID =3D BIT(0), MTK_PCIE_FIX_DEVICE_ID =3D BIT(1), MTK_PCIE_NO_MSI =3D BIT(2), MTK_PCIE_SKIP_RSTB =3D BIT(3), + MTK_PCIE_RETRAIN =3D BIT(4), }; =20 /** @@ -753,6 +764,135 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) return 0; } =20 +static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + struct resource *mem =3D NULL; + struct resource_entry *entry; + u32 val, link_mask; + int err; + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (entry) + mem =3D entry->res; + if (!mem) + return -EINVAL; + + if (!pcie->cfg) { + dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n"); + return -EINVAL; + } + + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + msleep(PCIE_T_PVPERL_MS); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, + port->base + PCIE_CONF_REV_CLASS); + writel(EN7528_HOST_MODE, port->base); + + link_mask =3D (port->slot =3D=3D 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINK= UP; + + /* 100ms timeout value should be enough for Gen1/2 training */ + err =3D regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val, + !!(val & link_mask), 20, + PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); + if (err) { + dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot); + return -ETIMEDOUT; + } + + /* Activate INTx interrupts */ + val =3D readl(port->base + PCIE_INT_MASK); + val &=3D ~INTX_MASK; + writel(val, port->base + PCIE_INT_MASK); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + + /* Set AHB to PCIe translation windows */ + val =3D lower_32_bits(mem->start) | + AHB2PCIE_SIZE(fls(resource_size(mem))); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); + + val =3D upper_32_bits(mem->start); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); + + writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0); + + if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK)) + dev_info(pcie->dev, + "module not built-in, Gen2 unavailable even if supported\n"); + + return 0; +} + +/** + * mtk_pcie_retrain - retrain the root bridge link if needed + * @dev: The device, for use in logging + * @host: The host bridge which contains the link + * + * Due to what is likely a hardware bug, some devices (notably EcoNet) sta= rt up + * as Gen1, and must be retrained once after initial configuration in orde= r to + * reach Gen2. + * + * These devices always self-identify as Gen2 capable, but sometimes the P= HY is + * only capable of Gen1 operation, and sometimes the PCIe card (e.g. wifi)= is + * only Gen1 capable. Therefore it is most convenient to retrain every port + * after startup. + */ +static int mtk_pcie_retrain(struct device *dev, struct pci_host_bridge *ho= st) +{ + struct pci_dev *rp; + int ret =3D -ENOENT; + u16 lnksta =3D 0; + u32 speed; + + /* Should already have been warned about during startup_port */ + if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK)) + return 0; + + for_each_pci_bridge(rp, host->bus) { + if (pci_pcie_type(rp) =3D=3D PCI_EXP_TYPE_ROOT_PORT) + goto found_port; + } + + /* Should not happen */ + return dev_err_probe(dev, ret, "root port not found\n"); + +found_port: + +#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK) + ret =3D pcie_retrain_link(rp, true); +#endif + + if (ret) + return dev_err_probe(dev, ret, "failed to retrain port\n"); + + pcie_capability_read_word(rp, PCI_EXP_LNKSTA, &lnksta); + speed =3D lnksta & PCI_EXP_LNKSTA_CLS; + + dev_info(dev, "link retrained, speed %s\n", + pci_speed_string(pcie_link_speed[speed])); + + return 0; +} + static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { @@ -1149,6 +1289,13 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + /* + * Ignore error because pci_host_probe() was already called, and in any + * case it is possible that the port will still work as Gen1. + */ + if (pcie->soc->quirks & MTK_PCIE_RETRAIN) + mtk_pcie_retrain(dev, host); + return 0; =20 put_resources: @@ -1264,8 +1411,16 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_en7528 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_en7528, + .setup_irq =3D mtk_pcie_setup_irq, + .quirks =3D MTK_PCIE_RETRAIN, +}; + static const struct of_device_id mtk_pcie_ids[] =3D { { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, + { .compatible =3D "econet,en7528-pcie", .data =3D &mtk_pcie_soc_en7528 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.39.5