From nobody Fri Jun 12 15:51:11 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5FCF33C4565; Thu, 14 May 2026 06:28:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; cv=none; b=iV6Plys83PsvNrVKikqy7zlO0dva0VTmGvuvqY3L1LGacfyygRCO5A+S2ucjrkkUYriMNw/Cr80SEOSTveYhpdmZY0AdV6MZHvuUr43ec7FrtkNRtpvsTz2u9mX8B/2ZB4bumIzs0OWWgvPl0v1hDF9JJpWl3squK+uitRoSlgc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; c=relaxed/simple; bh=1Z45y6YkvajUY4vScnh8VyWtFxSWdQ8zz7hnto/hpgA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sWOGl8+8T5czSKK/z6/iJQrfs6916XVIR9/7SZiOEaVOr9T+UFaoJGm/fm5aeBpErrTYGRXE6ibOmC7tYDdCyxLZGhXzcfL8DZtZLtNrp+SLEHJ8MLAuJ2ZmDdxIIK/u6KT9fMZ02Scqi5H4VXal6hwQTSZNmNgNXo1pn8UOaQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxQ_CKawVqSrwJAA--.29653S3; Thu, 14 May 2026 14:28:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcKJawVqIQqCAA--.48503S3; Thu, 14 May 2026 14:28:26 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] LoongArch: KVM: Check irq validility in kvm_vcpu_ioctl_interrupt() Date: Thu, 14 May 2026 14:28:20 +0800 Message-Id: <20260514062824.1378373-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260514062824.1378373-1-maobibo@loongson.cn> References: <20260514062824.1378373-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcKJawVqIQqCAA--.48503S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Function kvm_vcpu_ioctl_interrupt() can be called from userspace, here add irq validility cheking in kvm_vcpu_ioctl_interrupt(). Also add msgint feature checking if irq number is INT_AVEC. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 5 ----- arch/loongarch/kvm/vcpu.c | 22 +++++++++++++++------- 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index a18c60dffbba..48dd56aa4dc5 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -36,8 +36,6 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigne= d int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; dmsintc_inject_irq(vcpu); fallthrough; case INT_TI: @@ -75,9 +73,6 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned = int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; - fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index e28084c49e68..dc2a1f56650b 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1487,15 +1487,23 @@ void kvm_lose_fpu(struct kvm_vcpu *vcpu) int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *= irq) { int intr =3D (int)irq->irq; + int vector; =20 - if (intr > 0) - kvm_queue_irq(vcpu, intr); - else if (intr < 0) - kvm_dequeue_irq(vcpu, -intr); - else { - kvm_err("%s: invalid interrupt ioctl %d\n", __func__, irq->irq); + vector =3D intr; + if (intr < 0) + vector =3D -intr; + + if (vector >=3D EXCCODE_INT_NUM) return -EINVAL; - } + + if (!kvm_guest_has_msgint(&vcpu->arch) && (vector =3D=3D INT_AVEC)) + return -EINVAL; + + /* Clear irq function with intr =3D=3D 0 is missing... */ + if (intr >=3D 0) + kvm_queue_irq(vcpu, vector); + else + kvm_dequeue_irq(vcpu, vector); =20 kvm_vcpu_kick(vcpu); =20 --=20 2.39.3 From nobody Fri Jun 12 15:51:11 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5FD8D3C5523; Thu, 14 May 2026 06:28:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; cv=none; b=u+LArHYUfaLxM9mw6jfskkhCzt9ZvAk3W3TuaISEYJnYMHF2ga7n3vjEjG3NsEN2xIKi01AqWig0ysGH6jOAtXkynp6rd0Ng78XV2NhOG2vmVz8om8mukZrr+14E/Xku6mxPfgU1sQNPjF4TKc4Udg8Hg8Esj1pFSy9JS4VayJ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; c=relaxed/simple; bh=YISmOzW69R6NywwnUrgH9R9rYD/Lmn+RBVgzyh/G060=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=az3tdfreEjTie3HFRwwIelvOSbuISqZW/Q15NE/UT5/MgTDYY9I+BRJMD7/knbl+E3hBeg0F29U1ra8ZsUNJNHzbDSJ5enhnKtq8OrQkMqxEnStxH2Q1yP1rFnBtFCxG4VehToeIDlCuDISI0d1lo0i0LhUDP0n6cbudvgoiJBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxI_CKawVqT7wJAA--.29423S3; Thu, 14 May 2026 14:28:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcKJawVqIQqCAA--.48503S4; Thu, 14 May 2026 14:28:26 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] LoongArch: KVM: Use existing macro about interrupt bit mask Date: Thu, 14 May 2026 14:28:21 +0800 Message-Id: <20260514062824.1378373-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260514062824.1378373-1-maobibo@loongson.cn> References: <20260514062824.1378373-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcKJawVqIQqCAA--.48503S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With interrupt post, register CSR_GINTC and CSR_GSTAT is used, and CSR_GSTAT is used for percpu interrupt injection and CSR_GINTC is for external hardware interrupt injection. Here use existing macro about interrupt bit of register CSR_GINTC and CSR_GSTAT, rather than hard coded constant value. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 43 ++++++++++++++++++--------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index 3784ab4ccdb5..efe26b04b35f 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -10,22 +10,37 @@ #include =20 /* Controlled by 0x5 guest estat */ -#define CPU_SIP0 (_ULCAST_(1)) -#define CPU_SIP1 (_ULCAST_(1) << 1) -#define CPU_PMU (_ULCAST_(1) << 10) -#define CPU_TIMER (_ULCAST_(1) << 11) -#define CPU_IPI (_ULCAST_(1) << 12) -#define CPU_AVEC (_ULCAST_(1) << 14) +#define CPU_SIP0 BIT(INT_SWI0) +#define CPU_SIP1 BIT(INT_SWI1) +#define CPU_HWI0 BIT(INT_HWI0) +#define CPU_HWI1 BIT(INT_HWI1) +#define CPU_HWI2 BIT(INT_HWI2) +#define CPU_HWI3 BIT(INT_HWI3) +#define CPU_HWI4 BIT(INT_HWI4) +#define CPU_HWI5 BIT(INT_HWI5) +#define CPU_HWI6 BIT(INT_HWI6) +#define CPU_HWI7 BIT(INT_HWI7) +#define CPU_PMU BIT(INT_PCOV) +#define CPU_TIMER BIT(INT_TI) +#define CPU_IPI BIT(INT_IPI) +#define CPU_AVEC BIT(INT_AVEC) +#define KVM_ESTAT_IRQ_MASK (CPU_SIP0 | CPU_SIP1 | CPU_PMU | CPU_TIMER \ + | CPU_IPI | CPU_AVEC) +#define KVM_ESTAT_HWI_MASK (CPU_HWI0 | CPU_HWI1 | CPU_HWI2 | CPU_HWI3 \ + | CPU_HWI4 | CPU_HWI5 | CPU_HWI6 | CPU_HWI7) =20 /* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */ -#define CPU_IP0 (_ULCAST_(1)) -#define CPU_IP1 (_ULCAST_(1) << 1) -#define CPU_IP2 (_ULCAST_(1) << 2) -#define CPU_IP3 (_ULCAST_(1) << 3) -#define CPU_IP4 (_ULCAST_(1) << 4) -#define CPU_IP5 (_ULCAST_(1) << 5) -#define CPU_IP6 (_ULCAST_(1) << 6) -#define CPU_IP7 (_ULCAST_(1) << 7) +#define GINTC_VIP_DELTA (INT_HWI0 - CSR_GINTC_VIP_SHIFT) +#define CPU_IP0 BIT(INT_HWI0 - GINTC_VIP_DELTA) +#define CPU_IP1 BIT(INT_HWI1 - GINTC_VIP_DELTA) +#define CPU_IP2 BIT(INT_HWI2 - GINTC_VIP_DELTA) +#define CPU_IP3 BIT(INT_HWI3 - GINTC_VIP_DELTA) +#define CPU_IP4 BIT(INT_HWI4 - GINTC_VIP_DELTA) +#define CPU_IP5 BIT(INT_HWI5 - GINTC_VIP_DELTA) +#define CPU_IP6 BIT(INT_HWI6 - GINTC_VIP_DELTA) +#define CPU_IP7 BIT(INT_HWI7 - GINTC_VIP_DELTA) +#define KVM_GINTC_IRQ_MASK (CPU_IP0 | CPU_IP1 | CPU_IP2 | CPU_IP3 \ + | CPU_IP4 | CPU_IP5 | CPU_IP6 | CPU_IP7) =20 #define MNSEC_PER_SEC (NSEC_PER_SEC >> 20) =20 --=20 2.39.3 From nobody Fri Jun 12 15:51:11 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD92A3C5526; Thu, 14 May 2026 06:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740113; cv=none; b=ebk4P4ZUjqDrvuLfnrsoJm+eLJiAM6o1BmmT6/f/5Tv9kSpxVZAVIt25OsuqgyEAXdhe6xVn1wmYz8FqNZ2LWzKC/mpYUSgLfRpiLwxXwWB8gW99SVJ+pEU+kVTELxAzFmsersymaov6mC4lObc8M69FApjUy9ny2yHO7xr2064= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740113; c=relaxed/simple; bh=wj/qtmUBFDJXJl+feziJsWCY0e3g91f1/I35t8+55Bk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GFoFOunN3KNKxQHkDAcNded103M0xmHT6WU+LiSDWZ0OH0F1fQ6K6IRxKXd3Tm5uXJdUzFtInDO6US9b/6QyZPqhBSnZvwnTQU52nzgK11SbfZtbQw08J9vKbkGL1hOExakyH8/qru1Fe6gb0RBXkWiz7c5LUSrCua5N1MBuU9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxnOmKawVqU7wJAA--.27608S3; Thu, 14 May 2026 14:28:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxfcKJawVqIQqCAA--.48503S5; Thu, 14 May 2026 14:28:26 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] LoongArch: KVM: Inject interrupt with batch method Date: Thu, 14 May 2026 14:28:22 +0800 Message-Id: <20260514062824.1378373-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260514062824.1378373-1-maobibo@loongson.cn> References: <20260514062824.1378373-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxfcKJawVqIQqCAA--.48503S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With bitmask method, interrupt can be injected with batch mode, rather than one by one. Also remove unused array priority_to_irqp[] here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 95 ++++++++++------------------------ 1 file changed, 28 insertions(+), 67 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 48dd56aa4dc5..380aabb3d4d0 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -9,39 +9,16 @@ #include #include =20 -static unsigned int priority_to_irq[EXCCODE_INT_NUM] =3D { - [INT_TI] =3D CPU_TIMER, - [INT_IPI] =3D CPU_IPI, - [INT_SWI0] =3D CPU_SIP0, - [INT_SWI1] =3D CPU_SIP1, - [INT_HWI0] =3D CPU_IP0, - [INT_HWI1] =3D CPU_IP1, - [INT_HWI2] =3D CPU_IP2, - [INT_HWI3] =3D CPU_IP3, - [INT_HWI4] =3D CPU_IP4, - [INT_HWI5] =3D CPU_IP5, - [INT_HWI6] =3D CPU_IP6, - [INT_HWI7] =3D CPU_IP7, - [INT_AVEC] =3D CPU_AVEC, -}; - -static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_pending); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - dmsintc_inject_irq(vcpu); - fallthrough; - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { + if (irq & CPU_AVEC) + dmsintc_inject_irq(vcpu); + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -49,34 +26,20 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - set_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + set_csr_gintc(irq); } =20 -static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_clear); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -84,30 +47,28 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigne= d int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - clear_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + clear_csr_gintc(irq); } =20 void kvm_deliver_intr(struct kvm_vcpu *vcpu) { - unsigned int priority; - unsigned long *pending =3D &vcpu->arch.irq_pending; - unsigned long *pending_clr =3D &vcpu->arch.irq_clear; + unsigned long mask; =20 - for_each_set_bit(priority, pending_clr, EXCCODE_INT_NUM) - kvm_irq_clear(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + kvm_irq_clear(vcpu, mask); + } =20 - for_each_set_bit(priority, pending, EXCCODE_INT_NUM) - kvm_irq_deliver(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + kvm_irq_deliver(vcpu, mask); + } } =20 int kvm_pending_timer(struct kvm_vcpu *vcpu) --=20 2.39.3 From nobody Fri Jun 12 15:51:11 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 845573BE15C; Thu, 14 May 2026 06:28:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; cv=none; b=upOS1W4dR80XAnfQcSBsPOXyBdPCNpMAek7h7xOpk9ZxKHwictoWuvUuKCmKFUfc4VOlO5oJZZZd/SDAbEpXV6TxAq0m9uq2gIUcnydIBHQypY9Q33kuCxjZ3VkCopy9k2Z8ehaOjkrbL0kM22xatKXmqkixoCWfQ/roNdbTvHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740112; c=relaxed/simple; bh=YhjnOYMa/9tgKeawi7kAJ7iHfJj/jWCQwkIAZ+JxuIg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gaebxCniAPzdCvPbEmQdKyEQQXFHNXx8dAsxT1CileYQLmLTeEAXU+MyDTuhEJpPsihzu9//ZG5L33puZ1LQTpEMJZpFr0iT3V5OAjWhR7sT6qAXMxBEmpkI58FuymbFPDGnt/5/vFj0TvmHR/m3w9C/M838KgHLPbZmMe/RkpA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx+HiNawVqWLwJAA--.4996S3; Thu, 14 May 2026 14:28:29 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxHMKMawVqJAqCAA--.49521S2; Thu, 14 May 2026 14:28:28 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] LoongArch: KVM: Add valid bit check when set ESTAT CSR register Date: Thu, 14 May 2026 14:28:23 +0800 Message-Id: <20260514062824.1378373-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260514062824.1378373-1-maobibo@loongson.cn> References: <20260514062824.1378373-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxHMKMawVqJAqCAA--.49521S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When set ESTAT CSR register in function _kvm_setcsr(), valid bit check is added here. Also interrupt CPU_AVEC is checked by msgint feature. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/vcpu.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index dc2a1f56650b..2f4fd6fa5b0e 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -602,7 +602,7 @@ struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm,= int cpuid) =20 static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val) { - unsigned long gintc; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -621,8 +621,9 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) preempt_enable(); =20 /* ESTAT IP0~IP7 get from GINTC */ - gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; - *val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2); + gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & KVM_GINTC_IRQ_MAS= K; + estat =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) & ~KVM_ESTAT_HWI_MA= SK; + *val =3D estat | (gintc << 2); return 0; } =20 @@ -637,7 +638,8 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned = int id, u64 *val) =20 static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) { - int ret =3D 0, gintc; + int ret =3D 0; + unsigned long gintc, estat; struct loongarch_csrs *csr =3D vcpu->arch.csr; =20 if (get_gcsr_flag(id) & INVALID_GCSR) @@ -648,11 +650,15 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigne= d int id, u64 val) =20 if (id =3D=3D LOONGARCH_CSR_ESTAT) { /* ESTAT IP0~IP7 inject through GINTC */ - gintc =3D (val >> 2) & 0xff; + gintc =3D (val >> 2) & KVM_GINTC_IRQ_MASK; kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); =20 - gintc =3D val & ~(0xffUL << 2); - kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc); + /* only set valid ESTAT bits */ + estat =3D val & ~KVM_ESTAT_HWI_MASK; + estat &=3D CSR_ESTAT_IS | CSR_ESTAT_EXC | CSR_ESTAT_ESUBCODE; + if (!kvm_guest_has_msgint(&vcpu->arch)) + estat &=3D ~CPU_AVEC; + kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, estat); =20 return ret; } --=20 2.39.3 From nobody Fri Jun 12 15:51:11 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 380B73C061E; Thu, 14 May 2026 06:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740205; cv=none; b=P402piNlpqRvMjBMNAB9dd+LADdOKkkM5CtT1V3iyIrSsHx+KT9tymYNUn0AY820d4vAs7ByFbDGSn8zGjHi+u5IC0DdGo+z7l2YK+ANgoNkQPnUoKkT+bpfG3QVIWDzm4GgxbI8QCe/RHXEhqCH9ZOLWPODKCmCxX0o7bKWmLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778740205; c=relaxed/simple; bh=hkh36XRsen/JnuQoDrHsOoB+jd9jICKmgtz0Og7gyEY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P/6AjqL2/ulGmcIHoRjbqeVO4FmrnmNH9datoemvKOT4/JUxnI1JCyRzXWABiNlOxPDLEJ0RREgu7ErT4mvo0N8kqaUHJ+nuuIbfJgt47PYiQ6HZXUDSnU89Uce94Qarg5YeAaO6DtXGiTuFTDbWKG7ZUnMBvoNG4z4yl8liCNc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxI_CNawVqXLwJAA--.29424S3; Thu, 14 May 2026 14:28:29 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxHMKMawVqJAqCAA--.49521S3; Thu, 14 May 2026 14:28:29 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] LoongArch: KVM: Simple interrupt status acquire interface Date: Thu, 14 May 2026 14:28:24 +0800 Message-Id: <20260514062824.1378373-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260514062824.1378373-1-maobibo@loongson.cn> References: <20260514062824.1378373-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxHMKMawVqJAqCAA--.49521S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When VM is migrating, interrupts status are stored in software CSR estat register, also new injected interrupts are cached in vcpu::arch::irq_pending. With interrupt status acquire interface, there is expensive vcpu_load() and vcpu_put() function call to sync cached vcpu::arch::irq_pending. Here new internal API kvm_vcpu_sync_intr() is added to sync cached pending irq to software CSR estat register. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 1 + arch/loongarch/kvm/interrupt.c | 42 +++++++++++++++++++++++++++ arch/loongarch/kvm/vcpu.c | 15 ++++++---- 3 files changed, 52 insertions(+), 6 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index efe26b04b35f..e78bb2527329 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -64,6 +64,7 @@ int kvm_emu_idle(struct kvm_vcpu *vcpu); int kvm_pending_timer(struct kvm_vcpu *vcpu); int kvm_handle_fault(struct kvm_vcpu *vcpu, int fault); void kvm_deliver_intr(struct kvm_vcpu *vcpu); +void kvm_vcpu_sync_intr(struct kvm_vcpu *vcpu); void kvm_deliver_exception(struct kvm_vcpu *vcpu); =20 void kvm_own_fpu(struct kvm_vcpu *vcpu); diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 380aabb3d4d0..24925c238a65 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -71,6 +71,48 @@ void kvm_deliver_intr(struct kvm_vcpu *vcpu) } } =20 +void kvm_vcpu_sync_intr(struct kvm_vcpu *vcpu) +{ + struct loongarch_csrs *csr =3D vcpu->arch.csr; + unsigned long mask, val; + + if (!csr) + return; + + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + + /* + * sync cached irq_clear to sw state + * + * When VM is migrated to other physical machines or + * snapshot is created, cached irq pending state should + * be synced + */ + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT); + val &=3D ~(mask & KVM_ESTAT_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, val); + + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC); + val &=3D ~((mask >> 2) & KVM_GINTC_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, val); + } + + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + /* sync cached irq_pending to sw state */ + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT); + val |=3D (mask & KVM_ESTAT_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, val); + + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC); + val |=3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, val); + } +} + int kvm_pending_timer(struct kvm_vcpu *vcpu) { return test_bit(INT_TI, &vcpu->arch.irq_pending); diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 2f4fd6fa5b0e..5f94360e8a4b 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -610,14 +610,11 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigne= d int id, u64 *val) =20 if (id =3D=3D LOONGARCH_CSR_ESTAT) { preempt_disable(); - vcpu_load(vcpu); /* * Sync pending interrupts into ESTAT so that interrupt * remains during VM migration stage */ - kvm_deliver_intr(vcpu); - vcpu->arch.aux_inuse &=3D ~KVM_LARCH_SWCSR_LATEST; - vcpu_put(vcpu); + kvm_vcpu_sync_intr(vcpu); preempt_enable(); =20 /* ESTAT IP0~IP7 get from GINTC */ @@ -1649,6 +1646,14 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int= cpu) =20 /* Restore timer state regardless */ kvm_restore_timer(vcpu); + + /* + * Restore Root.GINTC from unused Guest.GINTC register + * + * SW state about LOONGARCH_CSR_GINTC is updated with get_csr() + * ioctl command only. Update HW state from changed SW state. + */ + write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); =20 /* Don't bother restoring registers multiple times unless necessary */ @@ -1711,8 +1716,6 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int = cpu) kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR3); } =20 - /* Restore Root.GINTC from unused Guest.GINTC register */ - write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); write_csr_gstat(csr->csrs[LOONGARCH_CSR_GSTAT]); =20 /* --=20 2.39.3