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Signed-off-by: Varadarajan Narayanan --- Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 3 += ++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.ya= ml index f60804687412..1ac31439c20a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,ipq5210-qmp-gen3x1-pcie-phy - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy @@ -24,10 +25,12 @@ properties: - qcom,ipq9574-qmp-gen3x2-pcie-phy - items: - enum: + - qcom,ipq5210-qmp-gen3x1-pcie-phy - qcom,ipq5424-qmp-gen3x1-pcie-phy - const: qcom,ipq9574-qmp-gen3x1-pcie-phy - items: - enum: + - qcom,ipq5210-qmp-gen3x2-pcie-phy - qcom,ipq5424-qmp-gen3x2-pcie-phy - const: qcom,ipq9574-qmp-gen3x2-pcie-phy =20 --=20 2.34.1 From nobody Fri Jun 12 15:39:51 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 603253ACF1D for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5bd5fe44sm8313965ad.11.2026.05.13.20.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 20:58:42 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 14 May 2026 09:28:29 +0530 Subject: [PATCH 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-pci-phy-v1-2-482429192746@oss.qualcomm.com> References: <20260514-pci-phy-v1-0-482429192746@oss.qualcomm.com> In-Reply-To: <20260514-pci-phy-v1-0-482429192746@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDAzNiBTYWx0ZWRfX7qlpK0hSsvkd q9SBNEDWHxY6NAkbaGar1lzxfxUPysXMIUFjPwew8mDKGGDfVjuVpwfIz+3BA5TYm0biiAZU9ow wzNKg+zW3Qb7VatTqCFDQjXN4KAvEs7VceWyLINGGWFF7sja9Hv7+/sKXCESQTsBPiAkSfE8vbq zT9SGor8h5swzehNsBS/FQK/Pcyeg3kQr6QneIty2P0txIMlPUU3z4235xOiS2T9erXwEuePqe2 80n/Mv7oGgM/IQQJ+P3zdTQD/idsi9rrk2blczPkL4uHTadcJE8zmMGQNOxyUzSJCvRHL8eozuJ xMIOk4feTo8ob7p+K2rrirLdACuqJA5xpkpjwBxq1rJzH/gIPsVBcrKO//vg1KLusJQYU6dCvGf fhyGWk3H4AKpylQ4TteXPRRBJTmp0gr1oYJR62SpMOFNhD0jF+R5XVDGGwcMknnnuuXyM62r4sd l+XqGx+R5LZ5e6s7DRg== X-Proofpoint-ORIG-GUID: Y408BAOdrtYhwJmtmuz7tDr8nos6Ergx X-Authority-Analysis: v=2.4 cv=Iba3n2qa c=1 sm=1 tr=0 ts=6a054873 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=Ac_ZsHBJicUw-6snl2sA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: Y408BAOdrtYhwJmtmuz7tDr8nos6Ergx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140036 Add support for a PCIe phys found on Qualcomm ipq5210 platform. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 152 +++++++++++++++++++++++++++= ++++ 1 file changed, 152 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb311..5887306eb67b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -514,6 +514,105 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen= 3_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; =20 +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_serdes_tbl[] = =3D { + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x10), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_misc_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x04), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4, 0xff), +}; + static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), @@ -654,6 +753,13 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_pc= ie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), }; =20 +static const struct qmp_phy_init_tbl ipq9574_pcie_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), +}; + static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), @@ -3613,6 +3719,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = =3D { .phy_status =3D PHYSTATUS, }; =20 +static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v4x1, + + .tbls =3D { + .serdes =3D ipq9574_gen3x1_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), + .tx =3D ipq9574_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq9574_pcie_tx_tbl), + .rx =3D ipq9574_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq9574_pcie_rx_tbl), + .pcs =3D ipq9574_gen3x1_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), + .pcs_misc =3D ipq9574_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), + }, + + .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D ipq5210_gen3x1_pcie_ep_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl), + .tx =3D ipq5210_gen3x1_pcie_ep_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_tx_tbl), + .rx =3D ipq5210_gen3x1_pcie_ep_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl), + .pcs =3D ipq5210_gen3x1_pcie_ep_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_tbl), + .pcs_misc =3D ipq5210_gen3x1_pcie_ep_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl), + }, + + .reset_list =3D ipq8074_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list =3D NULL, + .num_vregs =3D 0, + .regs =3D pciephy_v4_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .pipe_clock_rate =3D 250000000, +}; + static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -5404,6 +5553,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible =3D "qcom,ipq5210-qmp-gen3x1-pcie-phy", + .data =3D &ipq5210_gen3x1_pciephy_cfg, }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, --=20 2.34.1