From nobody Fri Jun 12 15:51:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E356E3ACA6B for ; Thu, 14 May 2026 04:13:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778731997; cv=none; b=DN9gUxyI016WpTbiMDGoegLOgKYQ/xXYsONX7YLLPyyY/NmTjcDBizob1pI5qcz4psdtsfoaPTYnzQ21NvKK1awzkUMbirxD6a9aervEmxH7DydMtIinX+3ou3kvjtkp8xnmk6MOa3pklFg6lJM0KzFT0Tt+l8xtMIJcSDqtvP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778731997; c=relaxed/simple; bh=JwW41K8IdkdgFGE2IHpnYGuhMsXkm8hjOGtwlDbRcpM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YIqcTB6UTlHN9O7+V2o9K8cAFi4357x3nItsgccvKcTLUzF8+6aPFVl7ZsdbWVLv2Xp9ih5Kc6riR8rTQgqJ1lU3vMNKCYt6sxZEYpx145nxA8d18KkeHJN0xU5MAvtaytey4FIoYIXu8lZU3DGkSPtdoCx4d4O4OpKlu8VrWGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Qxs3bZch; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=LeMuY62y; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Qxs3bZch"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="LeMuY62y" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64E35WFD1096610 for ; Thu, 14 May 2026 04:13:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Drn7srxvV0vFK1yAhzD7aPenQzPVdFLlBpIYOLOBz4A=; b=Qxs3bZchewyCJxYh kqnp+jnlp3WTeHVJq3hIiuQkRYsZ1bsFMXkISbWRq9UivlByFhCYRP1jVdZcXidF zJ+pWWFrm2vABIsGELi1B5Sd7RbqtO4pxeXkawKuBSQcdLm7RKjFdmWrzezoFbgh np5AkAUyA0g6xKGLtQ5LfkcMzZr5FtS92p98PV/5ru1qeKLN6YTZPis/ozz7RBtR pZKjTHLlhPs4E02rr4mm9qwPvtMe0rq9MxBB4xMIcd59JJFsThq0oVB1GIzg29ad AaudpBZAJAcKIsgV5q1O0Oa0sl2Q7EEM8Uv22T+8HP5QV4AEK6ZQLDnRQjVl0XyJ xpkD6A== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e566bg61t-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 14 May 2026 04:13:14 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-83536dc3be5so8350010b3a.1 for ; Wed, 13 May 2026 21:13:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778731994; x=1779336794; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Drn7srxvV0vFK1yAhzD7aPenQzPVdFLlBpIYOLOBz4A=; b=LeMuY62yfCol4oJe9gOSCg/zDkagssZ4sL87I9SKRByqgYAepiPHWT/Dv++pZyjXx9 NTLFRHjzq6tthfCIskSgsDMrdvhOZi2jZt9UWhUQxpGP9MASwX5wchAnUF73tx/AsP+5 YbM/pLpaRDLeAIy5smpGrKbkPQmpocZ4mzDLDkxdhGIDEzrRQYYTjsg95H8dqvIzLx4x gWuZw8b+/gTGgkuwk5bbRYJCPxe6kADrqrlgZMDv3+y39Wg99uQSMy147t/Gb63sm9S1 yDKsgEP1SNbu4a9bYhQ8VCwsuTST8UdJZx0kAohZNWY5UGsCNbejXALYNlKQhUSujUFn YeuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778731994; x=1779336794; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Drn7srxvV0vFK1yAhzD7aPenQzPVdFLlBpIYOLOBz4A=; b=WXFQhQA7+EabZumzhd4HE2a+09cMuFYwpy2Q2F2mwsK4lQD3NS//jWde9Et4kuOhHY DGBPYdwNphgu6RIrC1b8yc8Joh+iydkW7fuNaWwzasQFOj7dpoKOWfhUIfEg7vNRAXFY +DzDZJ0HBR3aIPuTj2tBTDPZA4r8Ta/SDF2BlzP7FtCeqMCtNxXANbpkrUkakm+UaH1X sJZd9ImkUr5GwGOt5IboiJ/5TZgoA6aIOiZrzKACfbUGObhz8/+IJOQ/3K9F6WVxPvRN rj5n2WocKkmbQNYsiCWhnmeYnvgvf5UY86Mrtpr8r0k//iPvdWcGoChoI+/jtZS3/lN+ O8xQ== X-Forwarded-Encrypted: i=1; AFNElJ/C2+VRc9YoATY+xdaZJPyj+qvweZuBsOtpfnDQN7pgkglPCz7A97/VxBOwIKU9ATIBDzqrwGWZxP3fMuc=@vger.kernel.org X-Gm-Message-State: AOJu0YyseOLk631rAeJp78K9ky0Brdo4P9Ior0f/hSJAmckqoE427i3H 1sL+tKBRetw13MCJxRkno5ZwJc0oCxSF2QxPyxgLgX0OW4WQN2U3wcFkimXCvRA66v01jHTde6V cB7qrBdXphK2pq+hX4/NFvSu0vt2MqhaOC7lCe5/Hdob8gitKWwAjzDuBOM/uh0XepEY= X-Gm-Gg: Acq92OGXXXDpWi03KcFj9/05e+hMQjgtlvJ1P5pLhwSOI/ItmHymUeIKxoukMchwqiU gbapix//9BcmYOAhNqhgyfsdinlUXS8eP+j5+kD0vI6kegNHrRSSPawEqEFC99xakD0Zsn+RYs6 Zvw2vf+mSMdnwuEm3T4oCrcWkTk4m7Gsi/YRC41R9rbDt0gBBdjP1jTMVYa4HBEyfWkmXyTq5rQ mMNpYBD3F9EA7G+I789LMhtOlcN+VI8aJ+cAGhYRuzNwDaRun2QIkiCMApq6qdzkBusts0YPMtb Z28pKZ3GyXQc96n0tjtr7tSQD2aGnr0fTn0oG8AHYJG9rhO9Xrx7KxVhzkncncf9XiZSXoO6s7t tFlvVPJouZdG92n2IgzmAsikDWFfzqjqZExh+WFrFrQZ0Z3qHV5SaL/YvSF/wgw0X6nKThNJ/kI mEb0l2VQy8e2ojMf6xTBmjy612JVBWCb+tDABxH+lrnPAOeTOi3ko= X-Received: by 2002:a05:6a00:909f:b0:835:532a:3468 with SMTP id d2e1a72fcca58-83f0546e833mr6386240b3a.20.1778731993946; Wed, 13 May 2026 21:13:13 -0700 (PDT) X-Received: by 2002:a05:6a00:909f:b0:835:532a:3468 with SMTP id d2e1a72fcca58-83f0546e833mr6386211b3a.20.1778731993466; Wed, 13 May 2026 21:13:13 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c5be71sm1075432b3a.39.2026.05.13.21.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 21:13:13 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 14 May 2026 09:43:01 +0530 Subject: [PATCH 1/2] dt-bindings: PCI: qcom,pcie-ipq9574: Document the ipq5210 pcie controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-pci-ipq5210-v1-1-a09436200b35@oss.qualcomm.com> References: <20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com> In-Reply-To: <20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: MOehyxahgMGAkSbUNnndegZDjsbMsPA6 X-Authority-Analysis: v=2.4 cv=WsMb99fv c=1 sm=1 tr=0 ts=6a054bda cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=QcxusUPE0xsQWomV07wA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDAzOCBTYWx0ZWRfX2ayuuGtZIsK+ BXBfN/kdUOISa3gPl5s0vls/CCfphT0/kNfdmqLP5DH5Cbp0zOcG3fVUFk9UBWzYqb93vEOyPCy zAYtopdBgvTAim+wkuUseIbekm2Kd7N81CMlwsPgl41NrQFsqxpUfVBbZ7wZtQAr75SVzZHO+R5 Cj8aOV5H7lzzFBEGIKwmOenm2c/5juGEvu7p7uz8NMnGywCmhNakoq5RKuUZwn0130ewBkGcb7Q dKLnVFTP3XeynZBT2gbKj5R2n40MbfRZTsOEerMuwezKnNOUNe3k4k4BKwOOlyLPMjGJrdw98KM JOGRJa+rUmh5C0qhtOfWvBr5Z5tklziXFGkeZfXIODrMxPJrI0YeIcMkk0i/67PNA/6blUQohGQ 8nYhN+5r/Quh9wnJYUfhy53pUAx0JItyMSoy2iOn4pm1521R/yxIySKLb5KGdom7e38emJE4d7L E0huea7/bMzYCh6zZ5A== X-Proofpoint-GUID: MOehyxahgMGAkSbUNnndegZDjsbMsPA6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140038 Document the ipq5210 PCIe controller using ipq9574 as fallback compatible. Signed-off-by: Varadarajan Narayanan --- Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml index 4be342cc04e1..a75ff554c283 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml @@ -17,6 +17,7 @@ properties: - qcom,pcie-ipq9574 - items: - enum: + - qcom,pcie-ipq5210 - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - const: qcom,pcie-ipq9574 --=20 2.34.1 From nobody Fri Jun 12 15:51:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC53D3ACA62 for ; Thu, 14 May 2026 04:13:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778732002; cv=none; b=AoxGc25WMmNL9KAp9DnEmmd6mPRil8D2wme92cxAMpDL+m5exdOHPl97RcK9vd8JZVO9qiIpPjfU+cyKqaC+AAxdsNn/J1s7EEFGRAigdgsb1rz5HJPz8XTFus5qj4wN1mwz2Lu1GQfXWyyxeE6k6Lqpki/hTaywTAueJWqJJXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778732002; c=relaxed/simple; bh=EZdQZIxDlFZqrv4hdcB+DHnhLKJkamJatT8pTwXJ4LE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bxnloyKRvx25eHERY5uRrwSJWFqohHvaCxZegkGYP9RzaJyTqjkD21L5YEkZiBA83e8gOGtEhlvkdplQ5DQsMmpNCWFMZPe4Ozve3m7wEult30Rjn3xbrFzAFfl+lFiW7Yser8FY3ttURVbUGibAjCnPIPrpHEQ1UYod6p1zDfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nVO+ex5v; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZNGau+Nq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nVO+ex5v"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZNGau+Nq" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64E37bv83430151 for ; Thu, 14 May 2026 04:13:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +24qlReIO49CXzcVPRFP++HqwH5zbI8hgVyfLdPoEgY=; b=nVO+ex5v4UQYr5F/ Ydu1NsBfDoRbaI4U/IzGieXwIIN/b9pQaINk2Xwti3ToX8vr7oGPE77L4z37mEkL D+kElrF0bi4yUX0vS+9PdSWpY2GwUfRBq90igqvYcQ4Vcqs1FTG48bgM/nFR4sa8 oG3H8iDK7wSt0ky6ZODDlOluS8B534+UO8kyEnAy9BCVjh8dPpzCyovIbRJ+CWQv HpzldYyD7nNIhP2IPDIsosuCiKb6gnlZSNlF/Y1X1kwhqWE9YhTuI0ghnwTovZpA IigLwfjMP7SiK9korCZyzpoQ/NEdkJkzpkdQ3wlbtl+8JLjDxuyEVYHIGg1Qwarq GUC56A== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e4qmckjym-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 14 May 2026 04:13:19 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-837c4eb3bdfso5132226b3a.2 for ; Wed, 13 May 2026 21:13:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778731999; x=1779336799; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+24qlReIO49CXzcVPRFP++HqwH5zbI8hgVyfLdPoEgY=; b=ZNGau+Nq3rLAjuyZsaGwJXXZoOepljyYHkZy+a4nBPhwS8A4ALEZDUvPxfXziAN6Px ahDcc0iRnytBZxLHMN9hlRTd0Lfi0+6gAJARKm4lPenQpf2aAWLzNLXXh50RAJCsMQP0 23hMXtsUls9Rx7o3SOIg0EJRYo3td8vY2Bd81j6PHWF5gX0A8XALI/fmzypSWDa5HSnQ PeszJIdFqOnolgRa40x9UOFXBR9pDF+GTCOxTIBGup4D3iXIBYvxEMZ8XpkuII8WG542 zexvNMKhj6Q7cPHfomozVwa+jxHaLw8oyLzWoW31f0adCLl/eL8S1LedhFwTakQm5F83 Pp3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778731999; x=1779336799; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+24qlReIO49CXzcVPRFP++HqwH5zbI8hgVyfLdPoEgY=; b=l3HChwjk5CYnQD5JgBF+0inLX/93cgs4wiL7j6LIpVkEmpmlcr3etJZ2R8W2upGsEK wzLKG43GQanXqYL9f/cHUgoi1r+DGkhaI4kfHAPgnqpsnnBUEL+EGbt0IA8AUys3weV8 /Alc6cWHVHGKcXEZy7xhdDBjaPcdXckP8xrMvjABqjxAUfFODe6uyKz7bgWWC18c+VqD /yiyYjUGoCguqIQpgtbTsCrmj+Jh7ZITdKJQcSBZWXr0vyCJ/ZBGvWe4QJXKeqv9jYMm mLg17FmiOeJoFtyftNQS04XkUKkYdxqPc0/r7AAc41AQuovDRtiRRfqylMig9dIgk2uI +//w== X-Forwarded-Encrypted: i=1; AFNElJ/Mf8kykI2Q4LXna/yVceYZ66A/P61YGStrmW+qsOJBrrYkIvp2b5WJAENGv9HblcayfME2fsNMIpB6HHM=@vger.kernel.org X-Gm-Message-State: AOJu0YwfxEnPlzXXaTlaUC/L0fIxOKS3bHF/dTd7afmFE3RVA2Rz65wV LdfHfoyBWTfdo5GmRzmFiZ/IYS4om4Igi3kcxPRA7t6+6QO1HCS+Q7/NoASnvy9H84ezB85o3E0 yf9qvHJ2CoLeiL5mr4Zsf9jHFgPG2GMHvn1zr65q/6oYDyB7cm5oyT4hYSnCz2Qj1LqY= X-Gm-Gg: Acq92OFac/IIghGp6TA6wJBj0+3pWgmiNE3YJ6kc5t4pt72LxJy45YjzrrT0VFT5MUE JbJUkAutFDRnfTECFh6GkzZw6W0C5lTDPsyXpgwJk8wC6S6URG2lTvfLjJxqjhKz00gOFn4Taxf uZIulsXvRct135nw9n6VD4Haad73Jx2HIRJimi6qZ04zQeDeRvGw/N1eFUIMAIVxQXK6L0sWIVz SyFPlWfWhaf+NooSACRtxQObxd+16IT+wDm9EE9IBlLbXNcU/Q3KrUmokAqqq1Eoq4MfOR4u0Nq ura9QlvoV855Bpopm3wWah/U4oqlSkrsx1Ejg+51i99LV4elh7Kn1SEeGMcIC+F2EQgeaj2Rkzo GXuBCyEaKh1r1XLKB1zi6dbglAIb2Udor7Tbi2Q92IyPuDt6iCT2WjfjRXZaCwjUJuGUEl7wlNG SUu/sgfoIWIANkCHyk16ThsbBhHbyR6cBB+K7Wy516MCoPdFmHV+M= X-Received: by 2002:a05:6a00:f8f:b0:82f:6e7:152d with SMTP id d2e1a72fcca58-83f0579be02mr6070353b3a.21.1778731998549; Wed, 13 May 2026 21:13:18 -0700 (PDT) X-Received: by 2002:a05:6a00:f8f:b0:82f:6e7:152d with SMTP id d2e1a72fcca58-83f0579be02mr6070324b3a.21.1778731998036; Wed, 13 May 2026 21:13:18 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c5be71sm1075432b3a.39.2026.05.13.21.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 21:13:17 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 14 May 2026 09:43:02 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: ipq5210: Enable PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-pci-ipq5210-v1-2-a09436200b35@oss.qualcomm.com> References: <20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com> In-Reply-To: <20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-GUID: 9WHmQxBSjkPTrfSUJy3cK6Vi6d428oSJ X-Authority-Analysis: v=2.4 cv=Hu5G3UTS c=1 sm=1 tr=0 ts=6a054bdf cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=-SdU90OiLOdpC9A8V0EA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDAzOCBTYWx0ZWRfXx7x1eWEJcsxc FLehkNJU7stcnU3muE+ebRpxx0VfzSmxKvM93h7nmczcg+DKGwn0C/DYmquBKrwKCNcJC6GDgTu QYpsYDQoWuCaHuGm5mWdUXk+Wanpyyq3S/yJFDLxJCDjIIZEYUlYaGahG9gvDlkNgMjwAMIfn+y cKOLmAGBv0M9atiVy0kQfWU8SFQpqCso6BNKVNS5OdiIm/vW1pdY/qCRZ0XDUdNoErNB+Ru9ilU V0nSCkOarZU4FFhKMwdW3Nfsp2oByGc+9wr3BqNDjGMseN5vFOUHx3S5aFualW2lQbUgTiE6TbX KqT1LBlXaYdcwdier+q52ZRWL9pI+WK/IhZ4sdaAeHiK12eU9rwc05XiMcZJH5a8GXq4SSK9TiZ c+UwUvtLpejaF72iayxtSG/NMw9Htz8VCUa9rfVPk67VTmL5Urz/pjq07W0110rhP1ChWa3h601 wvifCfLK0MRjhq3GDpA== X-Proofpoint-ORIG-GUID: 9WHmQxBSjkPTrfSUJy3cK6Vi6d428oSJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140038 Add DT entries to enable the PCIe controllers found in ipq5210. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 43 +++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 261 ++++++++++++++++++++++++= +++- 2 files changed, 302 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..5e599a1cea3f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -5,6 +5,7 @@ =20 /dts-v1/; =20 +#include #include "ipq5210.dtsi" =20 / { @@ -20,6 +21,32 @@ chosen { }; }; =20 +&pcie0_phy { + status =3D "okay"; +}; + +&pcie0_rp { + reset-gpios =3D <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + status =3D "okay"; +}; + +&pcie1_phy { + status =3D "okay"; +}; + +&pcie1_rp { + reset-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 =3D <&pcie1_default_state>; + status =3D "okay"; +}; + &sdhc { max-frequency =3D <192000000>; bus-width =3D <4>; @@ -36,6 +63,22 @@ &sleep_clk { }; =20 &tlmm { + pcie0_default_state: pcie0-default-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + output-low; + }; + + pcie1_default_state: pcie1-default-state { + pins =3D "gpio29"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + output-low; + }; + qup_uart1_default_state: qup-uart1-default-state { pins =3D "gpio38", "gpio39"; function =3D "qup_se1"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 3761eb03ab24..ec1c9a8c08e0 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include =20 / { @@ -13,6 +14,18 @@ / { interrupt-parent =3D <&intc>; =20 clocks { + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <250000000>; + #clock-cells =3D <0>; + }; + + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <250000000>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -130,6 +143,54 @@ soc@0 { dma-ranges =3D <0 0 0 0 0x10 0>; ranges =3D <0 0 0 0 0x10 0>; =20 + pcie0_phy: phy@84000 { + compatible =3D "qcom,ipq5210-qmp-gen3x1-pcie-phy", + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg =3D <0x0 0x00084000 0x0 0x1000>; + + clocks =3D <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "gcc_pcie0_pipe_clk_src"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie1_phy: phy@f4000 { + compatible =3D "qcom,ipq5210-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000f4000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE1_AUX_CLK>, <&gcc GCC_PCIE1_AHB_CLK>; + assigned-clock-rates =3D <20000000>, <100000000>; + + resets =3D <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "gcc_pcie1_pipe_clk_src"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5210-tlmm"; reg =3D <0x0 0x01000000 0x0 0x300000>; @@ -146,8 +207,8 @@ gcc: clock-controller@1800000 { reg =3D <0x0 0x01800000 0x0 0x40000>; clocks =3D <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, <0>, <0>; #clock-cells =3D <1>; @@ -299,6 +360,202 @@ frame@b128000 { status =3D "disabled"; }; }; + + pcie1: pcie@50000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x81000000 0x0 0x50200000 0x0 0x50200000 0x0 0x00100000>, + <0x82000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + clocks =3D <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie1_rp: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + phys =3D <&pcie1_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x81000000 0x0 0x70200000 0x0 0x70200000 0x0 0x00100000>, + <0x82000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + clocks =3D <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie0_rp: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + phys =3D <&pcie0_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; }; =20 timer { --=20 2.34.1