From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4064F39DBE6; Thu, 14 May 2026 09:28:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778750915; cv=pass; b=A8ImTpZRqBNfDqyOS0AizAEGYNM9z5JKcDJpkZcTy1zBPu8LeSwX0+rFQ2d2IYrJ/SUh31ov4owJiOkmZJ/+7kUAyoKdIx2d7s2ZNneuqfpRHhNzetugioGpD+1g9fz+MK+1DvlcHpog/tDs0YOhxT54P0WcjajB2SMoOVBiyM8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778750915; c=relaxed/simple; bh=GC/JrZxzAO+rxsVxcWTATynI7wEQhuCoJL54aWi+NWM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ml5XUPkIyudoSZXnbedqVzN4NLclltqrLdvXymogE6+obyixJqOuKP9+u6zHOQMZssTLrMs9ZHyRFD2AB/Sn7BRLFHIH48Yen5fscW+RMIRSWvThQecT36gyN9Nu9Tz7LjRgKJQMZvqpKZs2POPYmVFyrIpFgdXHbJlVbpoRK6w= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=g3HQ9HiW; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="g3HQ9HiW" ARC-Seal: i=1; a=rsa-sha256; t=1778750882; cv=none; d=zohomail.com; s=zohoarc; b=horYZKYMvsRUbB5Sx9tAHV7nLNY6zYRaZtV+Ctv0AvRqpYrws+WZgvfGoBsf7y4xp10RIKxYHlRP9NsFM3/fywhZuCxt7TRtMXumn7e8b3Ngi4nu1vxkcPgMrX23D0upO4JTW6iEntP6ophqreAMu37mKLcRYNY5shujmRPk29s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778750882; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=zPMcKoG5I9qnPtHQDgthnEdvM17iSNpvGtYFLktKU+4=; b=iHqClzVTBHKnJthoM9ZoOOztuTFn889PHN7TM17wg+QZJYRMl/mFFjn37Zgz+YH1dYZuVtr4QlGjVy8GoGFOWAVQubCMARdmr0gLb5WI4oNva0LT2txyJu5+d3ApIiKVW1MW57w8QQhEV74qXxcBKNJLoq01pYZxoatLhRDBp30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1778750882; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=zPMcKoG5I9qnPtHQDgthnEdvM17iSNpvGtYFLktKU+4=; b=g3HQ9HiW5783Xz7Gz5p08i/qEt2Yn82ue4rg0PA1kyDuK48HmFAOtmjxOVyFGI4Z uotMXAn/ok0VYMa5H07ym6dzAWbpWcxAUoFWsrYVJB8npV0VHZaSComp+C06XucB+4H jiWnswHWhYnDeOtu+kyv3lJNgHRfRap6d25Ps6/E= Received: by mx.zohomail.com with SMTPS id 1778750879948411.16321020159114; Thu, 14 May 2026 02:27:59 -0700 (PDT) From: Junhui Liu Date: Thu, 14 May 2026 17:27:17 +0800 Subject: [PATCH v5 1/6] clk: correct clk_div_mask() return value for width == 32 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-dr1v90-cru-v5-1-34f3021aab51@pigmoral.tech> References: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> In-Reply-To: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Troy Mitchell , Brian Masney X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778750853; l=1738; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=GC/JrZxzAO+rxsVxcWTATynI7wEQhuCoJL54aWi+NWM=; b=qI8aod5XO4PE0z8UDYWgNMJM9IflnI/HKy+dSi+Ho7ZEaVQCm8/G90+GtNjfteefzqWKMg3gC EU+l2UtUC2FBHHMkCsh+VXvKtAxI92rPUzXcieahuf7/Wsn2jy8rJ9r X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The macro clk_div_mask() currently wraps to zero when width is 32 due to 1 << 32 being undefined behavior. This leads to incorrect mask generation and prevents correct retrieval of register field values for 32-bit-wide dividers. Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely on a 32-bit val entry in their div_table to match a div, so providing a full 32-bit mask is necessary. Fix this by using the standard GENMASK() macro. This safely resolves the undefined behavior on both 32-bit and 64-bit architectures, while also benefiting from the built-in compile-time type and bounds checking provided by the GENMASK() macro. Cc: Troy Mitchell Cc: Brian Masney Signed-off-by: Junhui Liu Reviewed-by: Brian Masney Reviewed-by: Troy Mitchell --- Hi Troy and Brian, I dropped your Reviewed-by tags in this version because the implementation has changed (to use GENMASK()) and requires re-evaluation IMO. --- include/linux/clk-provider.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b01a38fef8cf..b986cc054d82 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -6,6 +6,7 @@ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H =20 +#include #include #include =20 @@ -714,7 +715,7 @@ struct clk_divider { spinlock_t *lock; }; =20 -#define clk_div_mask(width) ((1 << (width)) - 1) +#define clk_div_mask(width) GENMASK((width) - 1, 0) #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) =20 #define CLK_DIVIDER_ONE_BASED BIT(0) --=20 2.54.0 From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9EC93A71A4; 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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1778750896; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=jKJdbyXrw9VTi0yEwx04OeNrLBgPlknmx6N2taLjqjU=; b=AEbZy3gmqNCGQSqy3bjBRcMhsX0cUY4d90mEV5ffv4RBlOUabKfcYbvrW/Ngpjv0 HezbX+9XRkZfjZH19V34bQ47/4549vQpGEEIkF9wsCVcCz1LyXxzR2+WCI+RnoOKeVQ Mm6Qo869hF218zLcFPpvNYnRrcSzOr4pWJLCAvgw= Received: by mx.zohomail.com with SMTPS id 1778750894589707.3429527761551; Thu, 14 May 2026 02:28:14 -0700 (PDT) From: Junhui Liu Date: Thu, 14 May 2026 17:27:18 +0800 Subject: [PATCH v5 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-dr1v90-cru-v5-2-34f3021aab51@pigmoral.tech> References: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> In-Reply-To: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778750853; l=5045; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=88jiGfzMakks4bYP+7RcAmlZMDkHMNAvLD8mDKc1xmI=; b=m5dNSagAVeYMl0bQ6YIPZf4W1jlFAeb1IBVuJVKC0GkhV5kB5L6OYPi5eQWzR4h7pcO2foD3f XgnVQSwsb6BDRxAdjIH0GWg5Y4hDV12TCQG9H9sVnbyjAZVjvAxY6EE X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, which is responsible for clock and reset management. Reviewed-by: Conor Dooley Signed-off-by: Junhui Liu --- .../bindings/clock/anlogic,dr1v90-cru.yaml | 60 ++++++++++++++++++= ++++ include/dt-bindings/clock/anlogic,dr1v90-cru.h | 46 +++++++++++++++++ include/dt-bindings/reset/anlogic,dr1v90-cru.h | 41 +++++++++++++++ 3 files changed, 147 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/anlogic,dr1v90-cru.yam= l b/Documentation/devicetree/bindings/clock/anlogic,dr1v90-cru.yaml new file mode 100644 index 000000000000..11a92588e494 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/anlogic,dr1v90-cru.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/anlogic,dr1v90-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic DR1V90 Clock and Reset Unit (CRU) + +maintainers: + - Junhui Liu + +properties: + compatible: + const: anlogic,dr1v90-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: Main oscillator + - description: External CAN clock + - description: External WDT clock + + clock-names: + items: + - const: osc + - const: can_ext + - const: wdt_ext + + "#clock-cells": + const: 1 + description: + Refer for valid indices. + + "#reset-cells": + const: 1 + description: + Refer for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@f8801000 { + compatible =3D "anlogic,dr1v90-cru"; + reg =3D <0xf8801000 0x400>; + clocks =3D <&osc>, <&can_ext>, <&wdt_ext>; + clock-names =3D "osc", "can_ext", "wdt_ext"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/anlogic,dr1v90-cru.h b/include/dt-bi= ndings/clock/anlogic,dr1v90-cru.h new file mode 100644 index 000000000000..664daf3946a7 --- /dev/null +++ b/include/dt-bindings/clock/anlogic,dr1v90-cru.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024-2025 Anlogic, Inc. + * Copyright (C) 2025 Junhui Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_ +#define _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_ + +#define CLK_OSC_DIV2 0 +#define CLK_CPU_PLL 1 +#define CLK_CPU_PLL_4X 2 +#define CLK_CPU_4X 3 +#define CLK_CPU_2X 4 +#define CLK_CPU_1X 5 +#define CLK_IO_PLL 6 +#define CLK_IO_1000M 7 +#define CLK_IO_400M 8 +#define CLK_IO_25M 9 +#define CLK_IO_80M 10 +#define CLK_IO_400M_DIV2 11 +#define CLK_IO_400M_DIV4 12 +#define CLK_IO_400M_DIV8 13 +#define CLK_IO_400M_DIV16 14 +#define CLK_QSPI 15 +#define CLK_SPI 16 +#define CLK_SMC 17 +#define CLK_SDIO 18 +#define CLK_GPIO_DB 19 +#define CLK_EFUSE 20 +#define CLK_TVS 21 +#define CLK_TRNG 22 +#define CLK_OSC_DIV 23 +#define CLK_PWM 24 +#define CLK_FCLK0 25 +#define CLK_FCLK1 26 +#define CLK_FCLK2 27 +#define CLK_FCLK3 28 +#define CLK_WDT_SEL 29 +#define CLK_EFUSE_SEL 30 +#define CLK_CAN_SEL 31 +#define CLK_CPU_SEL 32 +#define CLK_CAN0 33 +#define CLK_CAN1 34 + +#endif /* _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_ */ diff --git a/include/dt-bindings/reset/anlogic,dr1v90-cru.h b/include/dt-bi= ndings/reset/anlogic,dr1v90-cru.h new file mode 100644 index 000000000000..c5b7aae1ab6a --- /dev/null +++ b/include/dt-bindings/reset/anlogic,dr1v90-cru.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Junhui Liu + */ + +#ifndef _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_ +#define _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_ + +#define RESET_OCM 0 +#define RESET_QSPI 1 +#define RESET_SMC 2 +#define RESET_WDT 3 +#define RESET_DMAC_AXI 4 +#define RESET_DMAC_AHB 5 +#define RESET_NPU 6 +#define RESET_JPU 7 +#define RESET_DDRBUS 8 +#define RESET_NIC_HP0 9 +#define RESET_NIC_HP1 10 +#define RESET_NIC_GP0M 11 +#define RESET_NIC_GP1M 12 +#define RESET_GPIO 13 +#define RESET_IPC 14 +#define RESET_USB0 15 +#define RESET_USB1 16 +#define RESET_GBE0 17 +#define RESET_GBE1 18 +#define RESET_SDIO0 19 +#define RESET_SDIO1 20 +#define RESET_UART0 21 +#define RESET_UART1 22 +#define RESET_SPI0 23 +#define RESET_SPI1 24 +#define RESET_CAN0 25 +#define RESET_CAN1 26 +#define RESET_TTC0 27 +#define RESET_TTC1 28 +#define RESET_I2C0 29 +#define RESET_I2C1 30 + +#endif /* _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_ */ --=20 2.54.0 From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC243A3E7A; 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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1778750910; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=bWHe3VodtX1rhhHHnKnmLpBDRLZOjnaCCMIR23WizCs=; b=IOWXDlK/ZnJUvB760nWWeGg1KFQtOC4zh49yK2zAstamyfyHSstLI1VuucgeomHc NfdhTBAsOhYY982kEUOGAl25Lt8KMv3PEzBCuUEHhS7ylEWpaaSHM+NDlUUIiZdfGI4 xXyEtPkOGtbSVAPmsnDNDU2mbun3PweM1cemoBsg= Received: by mx.zohomail.com with SMTPS id 1778750908767535.9619023440181; Thu, 14 May 2026 02:28:28 -0700 (PDT) From: Junhui Liu Date: Thu, 14 May 2026 17:27:19 +0800 Subject: [PATCH v5 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-dr1v90-cru-v5-3-34f3021aab51@pigmoral.tech> References: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> In-Reply-To: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778750853; l=21537; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=9esyhwB585+e/WXXrlLaGJKwzjMCa3RZuOfg0lxVt1k=; b=f1wjVc0/8oHl/hBT2+x+j3xxXHuNHc3P0v5pF6f048yJ683Yf9HQfS5ndVWOO6N7Nt5Ho6UtT e6eApkaVfD1DFwducVHkiCso1F4hP+uKR3799wUidZslhhXSYDX0a22 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The Clock and Reset Unit (CRU) in the Anlogic DR1V90 SoC provides management for the clock and reset. The clock driver includes support for: - Generic clocks: fixed-factor, divider, mux and gate. - PLL: "nm" type (parent * n / m) and "c" type (parent / c). These PLLs are set up by the FSBL and mared as "don't touch" in the datasheet, so only the recal_rate() op is provided. - Divider with gate: support both division and gating (by setting value to 0); some of them require a minimum divider value to avoid timing issues. This also prepares the structure for the reset controller support, registering an auxiliary device for resets. Signed-off-by: Junhui Liu --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/anlogic/Kconfig | 21 ++++ drivers/clk/anlogic/Makefile | 7 ++ drivers/clk/anlogic/cru-dr1v90.c | 192 +++++++++++++++++++++++++++++++++ drivers/clk/anlogic/cru_dr1.c | 226 +++++++++++++++++++++++++++++++++++= ++++ drivers/clk/anlogic/cru_dr1.h | 117 ++++++++++++++++++++ 7 files changed, 565 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..0eacde13c40d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -501,6 +501,7 @@ config COMMON_CLK_RPMI =20 source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" +source "drivers/clk/anlogic/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/eswin/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..814d5531f313 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o # please keep this section sorted lexicographically by directory path name obj-y +=3D actions/ obj-y +=3D analogbits/ +obj-y +=3D anlogic/ obj-y +=3D aspeed/ obj-$(CONFIG_COMMON_CLK_AT91) +=3D at91/ obj-$(CONFIG_ARCH_ARTPEC) +=3D axis/ diff --git a/drivers/clk/anlogic/Kconfig b/drivers/clk/anlogic/Kconfig new file mode 100644 index 000000000000..b3b17540176d --- /dev/null +++ b/drivers/clk/anlogic/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config ANLOGIC_DR1_CRU + tristate "Clock support for Anlogic DR1 series SoCs" + depends on ARCH_ANLOGIC || COMPILE_TEST + select AUXILIARY_BUS + default ARCH_ANLOGIC + help + Say Y to enable clock controller unit support for Anlogic DR1 series + SoCs. + +if ANLOGIC_DR1_CRU + +config ANLOGIC_DR1V90_CRU + tristate "Anlogic DR1V90 clock support" + depends on ARCH_ANLOGIC || COMPILE_TEST + default ARCH_ANLOGIC + help + Support for the Clock and Reset Unit in Anlogic DR1V90 SoCs. + +endif diff --git a/drivers/clk/anlogic/Makefile b/drivers/clk/anlogic/Makefile new file mode 100644 index 000000000000..fab7f29bb097 --- /dev/null +++ b/drivers/clk/anlogic/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_ANLOGIC_DR1_CRU) +=3D anlogic-dr1-cru.o +anlogic-dr1-cru-y +=3D cru_dr1.o + +obj-$(CONFIG_ANLOGIC_DR1V90_CRU) +=3D anlogic-dr1v90-cru.o +anlogic-dr1v90-cru-y +=3D cru-dr1v90.o diff --git a/drivers/clk/anlogic/cru-dr1v90.c b/drivers/clk/anlogic/cru-dr1= v90.c new file mode 100644 index 000000000000..b513dfba3dbd --- /dev/null +++ b/drivers/clk/anlogic/cru-dr1v90.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 Anlogic, Inc. + * Copyright (C) 2026 Junhui Liu + */ + +#include +#include +#include +#include +#include + +#include "cru_dr1.h" + +#include + +static const struct clk_div_table cru_div_table_24[] =3D { + { 0xFFFFFF, 1 }, { 0x555555, 2 }, { 0x249249, 3 }, { 0x111111, 4 }, + { 0x084210, 5 }, { 0x041041, 6 }, { 0x020408, 7 }, { 0x010101, 8 }, + { 0x008040, 9 }, { 0x004010, 10 }, { 0x002004, 11 }, { 0x001001, 12 }, + { 0x000800, 13 }, { 0x000400, 14 }, { 0x000200, 15 }, { 0x000100, 16 }, + { 0x000080, 17 }, { 0x000040, 18 }, { 0x000020, 19 }, { 0x000010, 20 }, + { 0x000008, 21 }, { 0x000004, 22 }, { 0x000002, 23 }, { 0x000001, 24 }, + { /* sentinel */ } +}; + +static const struct clk_div_table cru_div_table_32[] =3D { + { 0xFFFFFFFF, 1 }, { 0x55555555, 2 }, { 0x24924924, 3 }, + { 0x11111111, 4 }, { 0x08421084, 5 }, { 0x04104104, 6 }, + { 0x02040810, 7 }, { 0x01010101, 8 }, { 0x00804020, 9 }, + { 0x00401004, 10 }, { 0x00200400, 11 }, { 0x00100100, 12 }, + { 0x00080040, 13 }, { 0x00040010, 14 }, { 0x00020004, 15 }, + { 0x00010001, 16 }, { 0x00008000, 17 }, { 0x00004000, 18 }, + { 0x00002000, 19 }, { 0x00001000, 20 }, { 0x00000800, 21 }, + { 0x00000400, 22 }, { 0x00000200, 23 }, { 0x00000100, 24 }, + { 0x00000080, 25 }, { 0x00000040, 26 }, { 0x00000020, 27 }, + { 0x00000010, 28 }, { 0x00000008, 29 }, { 0x00000004, 30 }, + { 0x00000002, 31 }, { 0x00000001, 32 }, { /* sentinel */ } +}; + +CLK_FIXED_FACTOR_FW_NAME(osc_div2, "osc_div2", "osc", 2, 1, 0); + +CRU_PLL_NM_DEFINE(cpu_pll, CRU_PARENT_NAME(osc), 0x120); +CRU_PLL_C_DEFINE(cpu_pll_4x, CRU_PARENT_HW(cpu_pll), 0x14c); + +CRU_DIV_DEFINE(cpu_4x_div1, CRU_PARENT_HW(cpu_pll_4x), 0x010, 0, 24, + cru_div_table_24, CLK_DIVIDER_READ_ONLY); +CRU_DIV_DEFINE(cpu_4x_div2, CRU_PARENT_HW(cpu_pll_4x), 0x014, 0, 24, + cru_div_table_24, CLK_DIVIDER_READ_ONLY); +CRU_DIV_DEFINE(cpu_4x_div4, CRU_PARENT_HW(cpu_pll_4x), 0x018, 0, 24, + cru_div_table_24, CLK_DIVIDER_READ_ONLY); + +CRU_PLL_NM_DEFINE(io_pll, CRU_PARENT_NAME(osc), 0x220); +CRU_PLL_C_DEFINE(io_1000m, CRU_PARENT_HW(io_pll), 0x248); +CRU_PLL_C_DEFINE(io_400m, CRU_PARENT_HW(io_pll), 0x24c); +CRU_PLL_C_DEFINE(io_25m, CRU_PARENT_HW(io_pll), 0x250); +CRU_PLL_C_DEFINE(io_80m, CRU_PARENT_HW(io_pll), 0x254); + +CRU_DIV_DEFINE(io_400m_div2, CRU_PARENT_HW(io_400m), 0x020, 0, 32, + cru_div_table_32, CLK_DIVIDER_READ_ONLY); +CRU_DIV_DEFINE(io_400m_div4, CRU_PARENT_HW(io_400m), 0x024, 0, 32, + cru_div_table_32, CLK_DIVIDER_READ_ONLY); +CRU_DIV_DEFINE(io_400m_div8, CRU_PARENT_HW(io_400m), 0x028, 0, 32, + cru_div_table_32, CLK_DIVIDER_READ_ONLY); +CRU_DIV_DEFINE(io_400m_div16, CRU_PARENT_HW(io_400m), 0x02c, 0, 32, + cru_div_table_32, CLK_DIVIDER_READ_ONLY); + +CRU_DIV_GATE_DEFINE(qspi, CRU_PARENT_HW(io_1000m), 0x030, 0, 6, NULL, 0, 2= ); +CRU_DIV_GATE_DEFINE(spi, CRU_PARENT_HW(io_1000m), 0x030, 8, 6, NULL, 0, 4); +CRU_DIV_GATE_DEFINE(smc, CRU_PARENT_HW(io_1000m), 0x030, 16, 6, NULL, 0, 4= ); +CRU_DIV_DEFINE(sdio, CRU_PARENT_HW(io_400m), 0x030, 24, 6, NULL, 0); + +CRU_DIV_GATE_DEFINE(gpio_db, CRU_PARENT_HW(io_25m), 0x034, 0, 6, NULL, 0, = 1); +CRU_DIV_GATE_DEFINE(efuse, CRU_PARENT_HW(io_25m), 0x034, 8, 6, NULL, 0, 1); +CRU_DIV_GATE_DEFINE(tvs, CRU_PARENT_HW(io_25m), 0x034, 16, 6, NULL, 0, 1); +CRU_DIV_GATE_DEFINE(trng, CRU_PARENT_HW(io_25m), 0x034, 24, 7, NULL, 0, 1); + +CRU_DIV_GATE_DEFINE(osc_div, CRU_PARENT_NAME(osc), 0x038, 0, 6, NULL, 0, 1= ); +CRU_DIV_GATE_DEFINE(pwm, CRU_PARENT_NAME(osc), 0x038, 8, 12, NULL, 0, 1); + +CRU_DIV_GATE_DEFINE(fclk0, CRU_PARENT_HW(io_400m), 0x03c, 0, 6, NULL, 0, 1= ); +CRU_DIV_GATE_DEFINE(fclk1, CRU_PARENT_HW(io_400m), 0x03c, 8, 6, NULL, 0, 1= ); +CRU_DIV_GATE_DEFINE(fclk2, CRU_PARENT_HW(io_400m), 0x03c, 16, 6, NULL, 0, = 1); +CRU_DIV_GATE_DEFINE(fclk3, CRU_PARENT_HW(io_400m), 0x03c, 24, 6, NULL, 0, = 1); + +static const struct clk_parent_data wdt_parents[] =3D { + CRU_PARENT_HW(osc_div2), + CRU_PARENT_NAME(wdt_ext) +}; +CRU_MUX_DEFINE(wdt_sel, wdt_parents, 0x040, 1, 1); + +static const struct clk_parent_data efuse_parents[] =3D { + CRU_PARENT_NAME(osc), + CRU_PARENT_DIV_HW(efuse) +}; +CRU_MUX_DEFINE(efuse_sel, efuse_parents, 0x040, 2, 1); + +static const struct clk_parent_data can_parents[] =3D { + CRU_PARENT_HW(io_80m), + CRU_PARENT_NAME(can_ext) +}; +CRU_MUX_DEFINE(can_sel, can_parents, 0x040, 3, 1); + +static const struct clk_parent_data cpu_parents[] =3D { + CRU_PARENT_HW(cpu_4x_div1), + CRU_PARENT_HW(cpu_4x_div2) +}; +CRU_MUX_DEFINE(cpu_sel, cpu_parents, 0x040, 5, 1); + +CRU_GATE_DEFINE(can0, CRU_PARENT_HW(can_sel), 0x08c, 20, CLK_GATE_SET_TO_D= ISABLE); +CRU_GATE_DEFINE(can1, CRU_PARENT_HW(can_sel), 0x08c, 21, CLK_GATE_SET_TO_D= ISABLE); + +static const struct cru_clk dr1v90_cru_clks[] =3D { + [CLK_OSC_DIV2] =3D { &osc_div2.hw, NULL }, + [CLK_CPU_PLL] =3D { &cpu_pll.hw, &cpu_pll.reg }, + [CLK_CPU_PLL_4X] =3D { &cpu_pll_4x.hw, &cpu_pll_4x.reg }, + [CLK_CPU_4X] =3D { &cpu_4x_div1.hw, &cpu_4x_div1.reg }, + [CLK_CPU_2X] =3D { &cpu_4x_div2.hw, &cpu_4x_div2.reg }, + [CLK_CPU_1X] =3D { &cpu_4x_div4.hw, &cpu_4x_div4.reg }, + [CLK_IO_PLL] =3D { &io_pll.hw, &io_pll.reg }, + [CLK_IO_1000M] =3D { &io_1000m.hw, &io_1000m.reg }, + [CLK_IO_400M] =3D { &io_400m.hw, &io_400m.reg }, + [CLK_IO_25M] =3D { &io_25m.hw, &io_25m.reg }, + [CLK_IO_80M] =3D { &io_80m.hw, &io_80m.reg }, + [CLK_IO_400M_DIV2] =3D { &io_400m_div2.hw, &io_400m_div2.reg }, + [CLK_IO_400M_DIV4] =3D { &io_400m_div4.hw, &io_400m_div4.reg }, + [CLK_IO_400M_DIV8] =3D { &io_400m_div8.hw, &io_400m_div8.reg }, + [CLK_IO_400M_DIV16] =3D { &io_400m_div16.hw, &io_400m_div16.reg }, + [CLK_QSPI] =3D { &qspi.divider.hw, &qspi.divider.reg }, + [CLK_SPI] =3D { &spi.divider.hw, &spi.divider.reg }, + [CLK_SMC] =3D { &smc.divider.hw, &smc.divider.reg }, + [CLK_SDIO] =3D { &sdio.hw, &sdio.reg }, + [CLK_GPIO_DB] =3D { &gpio_db.divider.hw, &gpio_db.divider.reg }, + [CLK_EFUSE] =3D { &efuse.divider.hw, &efuse.divider.reg }, + [CLK_TVS] =3D { &tvs.divider.hw, &tvs.divider.reg }, + [CLK_TRNG] =3D { &trng.divider.hw, &trng.divider.reg }, + [CLK_OSC_DIV] =3D { &osc_div.divider.hw, &osc_div.divider.reg }, + [CLK_PWM] =3D { &pwm.divider.hw, &pwm.divider.reg }, + [CLK_FCLK0] =3D { &fclk0.divider.hw, &fclk0.divider.reg }, + [CLK_FCLK1] =3D { &fclk1.divider.hw, &fclk1.divider.reg }, + [CLK_FCLK2] =3D { &fclk2.divider.hw, &fclk2.divider.reg }, + [CLK_FCLK3] =3D { &fclk3.divider.hw, &fclk3.divider.reg }, + [CLK_WDT_SEL] =3D { &wdt_sel.hw, &wdt_sel.reg }, + [CLK_EFUSE_SEL] =3D { &efuse_sel.hw, &efuse_sel.reg }, + [CLK_CAN_SEL] =3D { &can_sel.hw, &can_sel.reg }, + [CLK_CPU_SEL] =3D { &cpu_sel.hw, &cpu_sel.reg }, + [CLK_CAN0] =3D { &can0.hw, &can0.reg }, + [CLK_CAN1] =3D { &can1.hw, &can1.reg } +}; + +static int dr1v90_cru_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + ret =3D dr1_cru_clk_register(dev, base, dr1v90_cru_clks, + ARRAY_SIZE(dr1v90_cru_clks)); + if (ret) + return dev_err_probe(dev, ret, "failed to register clocks\n"); + + ret =3D dr1_cru_reset_register(dev, base); + if (ret) + return dev_err_probe(dev, ret, "failed to register resets\n"); + + return 0; +} + +static const struct of_device_id dr1v90_cru_ids[] =3D { + { .compatible =3D "anlogic,dr1v90-cru" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dr1v90_cru_ids); + +static struct platform_driver dr1v90_cru_driver =3D { + .driver =3D { + .name =3D "dr1v90-cru", + .of_match_table =3D dr1v90_cru_ids, + }, + .probe =3D dr1v90_cru_probe, +}; +module_platform_driver(dr1v90_cru_driver); + +MODULE_AUTHOR("Fushan Zeng "); +MODULE_AUTHOR("Junhui Liu "); +MODULE_DESCRIPTION("Anlogic DR1V90 CRU driver"); +MODULE_IMPORT_NS("CLK_ANLOGIC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/anlogic/cru_dr1.c b/drivers/clk/anlogic/cru_dr1.c new file mode 100644 index 000000000000..10f8751a8838 --- /dev/null +++ b/drivers/clk/anlogic/cru_dr1.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 Anlogic, Inc. + * Copyright (C) 2026 Junhui Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cru_dr1.h" + +static unsigned long cru_pll_nm_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cru_pll *pll =3D hw_to_cru_pll(hw); + u32 mult, div; + + div =3D FIELD_GET(GENMASK(6, 0), readl(pll->reg)) + 1; + mult =3D FIELD_GET(GENMASK(6, 0), readl(pll->reg + 4)) + 1; + + return parent_rate * mult / div; +} + +const struct clk_ops dr1_cru_pll_nm_ops =3D { + .recalc_rate =3D cru_pll_nm_recalc_rate, +}; +EXPORT_SYMBOL_NS_GPL(dr1_cru_pll_nm_ops, "CLK_ANLOGIC"); + +static unsigned long cru_pll_c_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cru_pll *pll =3D hw_to_cru_pll(hw); + u32 div; + + div =3D FIELD_GET(GENMASK(30, 24), readl(pll->reg)) + 1; + + return parent_rate / div; +} + +const struct clk_ops dr1_cru_pll_c_ops =3D { + .recalc_rate =3D cru_pll_c_recalc_rate, +}; +EXPORT_SYMBOL_NS_GPL(dr1_cru_pll_c_ops, "CLK_ANLOGIC"); + +static void cru_div_gate_endisable(struct clk_hw *hw, int enable) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + u32 reg; + + reg =3D readl(divider->reg); + reg &=3D ~(clk_div_mask(divider->width) << divider->shift); + + if (enable) + reg |=3D div_gate->val << divider->shift; + + writel(reg, divider->reg); +} + +static int cru_div_gate_enable(struct clk_hw *hw) +{ + cru_div_gate_endisable(hw, 1); + + return 0; +} + +static void cru_div_gate_disable(struct clk_hw *hw) +{ + cru_div_gate_endisable(hw, 0); +} + +static int cru_div_gate_is_enabled(struct clk_hw *hw) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + u32 val; + + val =3D readl(divider->reg) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return !!val; +} + +static unsigned long cru_div_gate_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + unsigned int val; + + val =3D readl(divider->reg) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + if (val < div_gate->min) + return 0; + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static int cru_div_gate_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + unsigned long maxdiv, mindiv; + int div =3D 0; + + maxdiv =3D clk_div_mask(divider->width) + 1; + mindiv =3D div_gate->min + 1; + + div =3D DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate); + div =3D div > maxdiv ? maxdiv : div; + div =3D div < mindiv ? mindiv : div; + + req->rate =3D DIV_ROUND_UP_ULL(req->best_parent_rate, div); + + return 0; +} + +static int cru_div_gate_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + int value; + u32 reg; + + if (!__clk_is_enabled(hw->clk)) + return 0; + + value =3D divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (value < div_gate->min) + value =3D div_gate->min; + + reg =3D readl(divider->reg); + reg &=3D ~(clk_div_mask(divider->width) << divider->shift); + reg |=3D (u32)value << divider->shift; + writel(reg, divider->reg); + + div_gate->val =3D value; + + return 0; +} + +static int cru_div_gate_init(struct clk_hw *hw) +{ + struct cru_div_gate *div_gate =3D hw_to_cru_div_gate(hw); + struct clk_divider *divider =3D &div_gate->divider; + u32 val; + + val =3D readl(divider->reg) >> divider->shift; + val &=3D clk_div_mask(divider->width); + div_gate->val =3D val; + + return 0; +} + +const struct clk_ops dr1_cru_div_gate_ops =3D { + .enable =3D cru_div_gate_enable, + .disable =3D cru_div_gate_disable, + .is_enabled =3D cru_div_gate_is_enabled, + .recalc_rate =3D cru_div_gate_recalc_rate, + .determine_rate =3D cru_div_gate_determine_rate, + .set_rate =3D cru_div_gate_set_rate, + .init =3D cru_div_gate_init, +}; +EXPORT_SYMBOL_NS_GPL(dr1_cru_div_gate_ops, "CLK_ANLOGIC"); + +int dr1_cru_clk_register(struct device *dev, void __iomem *base, + const struct cru_clk *clks, int nr_clks) +{ + struct clk_hw_onecell_data *priv; + int i, ret; + + priv =3D devm_kzalloc(dev, struct_size(priv, hws, nr_clks), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + for (i =3D 0; i < nr_clks; i++) { + const struct cru_clk *clk =3D &clks[i]; + + if (clk->reg) + *(clk->reg) +=3D (uintptr_t)base; + + ret =3D devm_clk_hw_register(dev, clk->hw); + if (ret) + return ret; + + priv->hws[i] =3D clk->hw; + } + + priv->num =3D nr_clks; + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + dev_err(dev, "failed to add clock hardware provider\n"); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(dr1_cru_clk_register, "CLK_ANLOGIC"); + +int dr1_cru_reset_register(struct device *dev, void __iomem *base) +{ + struct auxiliary_device *adev; + + adev =3D devm_auxiliary_device_create(dev, "reset", base); + if (!adev) + return -ENODEV; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(dr1_cru_reset_register, "CLK_ANLOGIC"); + +MODULE_DESCRIPTION("Anlogic DR1 CRU driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/anlogic/cru_dr1.h b/drivers/clk/anlogic/cru_dr1.h new file mode 100644 index 000000000000..5386aed9e9f3 --- /dev/null +++ b/drivers/clk/anlogic/cru_dr1.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024-2025 Anlogic, Inc. + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _CRU_DR1_H_ +#define _CRU_DR1_H_ + +#include + +struct cru_pll { + struct clk_hw hw; + void __iomem *reg; +}; + +struct cru_div_gate { + struct clk_divider divider; + u32 val; /* Cached divider value for restoring on enable */ + u8 min; /* Minimum divider value to avoid timing issues */ +}; + +struct cru_clk { + struct clk_hw *hw; + void **reg; +}; + +#define CRU_PARENT_NAME(_name) { .fw_name =3D #_name } +#define CRU_PARENT_HW(_parent) { .hw =3D &_parent.hw } +#define CRU_PARENT_DIV_HW(_parent) { .hw =3D &_parent.divider.hw } + +#define CRU_INITHW(_name, _parent, _ops) \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .parent_data =3D (const struct clk_parent_data[]) \ + { _parent }, \ + .num_parents =3D 1, \ + .ops =3D &_ops, \ + } + +#define CRU_INITHW_PARENTS(_name, _parents, _ops) \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA(#_name, _parents, &_ops, 0) + +#define CRU_PLL_NM_DEFINE(_name, _parent, _reg) \ +static struct cru_pll _name =3D { \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW(_name, _parent, dr1_cru_pll_nm_ops), \ +} + +#define CRU_PLL_C_DEFINE(_name, _parent, _reg) \ +static struct cru_pll _name =3D { \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW(_name, _parent, dr1_cru_pll_c_ops), \ +} + +#define CRU_DIV_DEFINE(_name, _parent, _reg, _shift, _width, _table, \ + _flags) \ +static struct clk_divider _name =3D { \ + .shift =3D _shift, \ + .width =3D _width, \ + .flags =3D _flags, \ + .table =3D _table, \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW(_name, _parent, clk_divider_ops), \ +} + +#define CRU_DIV_GATE_DEFINE(_name, _parent, _reg, _shift, _width, \ + _table, _flags, _min) \ +static struct cru_div_gate _name =3D { \ + .min =3D _min, \ + .divider =3D { \ + .shift =3D _shift, \ + .width =3D _width, \ + .flags =3D _flags, \ + .table =3D _table, \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW(_name, _parent, dr1_cru_div_gate_ops), \ + } \ +} + +#define CRU_MUX_DEFINE(_name, _parents, _reg, _shift, _width) \ +static struct clk_mux _name =3D { \ + .shift =3D _shift, \ + .mask =3D GENMASK(_width - 1, 0), \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW_PARENTS(_name, _parents, clk_mux_ops) \ +} + +#define CRU_GATE_DEFINE(_name, _parent, _reg, _bit_idx, _flags) \ +static struct clk_gate _name =3D { \ + .bit_idx =3D _bit_idx, \ + .flags =3D _flags, \ + .reg =3D (void __iomem *)(_reg), \ + CRU_INITHW(_name, _parent, clk_gate_ops) \ +} + +static inline struct cru_pll *hw_to_cru_pll(struct clk_hw *hw) +{ + return container_of(hw, struct cru_pll, hw); +} + +static inline struct cru_div_gate *hw_to_cru_div_gate(struct clk_hw *hw) +{ + struct clk_divider *divider =3D to_clk_divider(hw); + + return container_of(divider, struct cru_div_gate, divider); +} + +extern const struct clk_ops dr1_cru_pll_nm_ops; +extern const struct clk_ops dr1_cru_pll_c_ops; +extern const struct clk_ops dr1_cru_div_gate_ops; + +int dr1_cru_clk_register(struct device *dev, void __iomem *base, + const struct cru_clk *clks, int nr_clks); +int dr1_cru_reset_register(struct device *dev, void __iomem *base); + +#endif /* _CRU_DR1_H_ */ --=20 2.54.0 From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C2C23A3E86; Thu, 14 May 2026 09:29:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; 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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1778750922; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=uM82xqu0AusXULaIJ+x/zNC09+MvS/PQE5kIVt6UpkI=; b=FP9Z8YN8X9eWWvfQL7q60OEecisA5X8VvcCCGdC7Y17sdfl+t+cdAZjuQpBDwsAX s7szPO8l14Am8uCH3KcD6XV/oaH0Y5Qng/CVKF3nzXWHaDq9OGyF/SPt05HxP7BGHMN UM8bnTTHNLhGNdN2yJQiokGtDhRalQMToQoQjS7E= Received: by mx.zohomail.com with SMTPS id 1778750920414559.4090568898675; Thu, 14 May 2026 02:28:40 -0700 (PDT) From: Junhui Liu Date: Thu, 14 May 2026 17:27:20 +0800 Subject: [PATCH v5 4/6] reset: anlogic: add support for Anlogic DR1V90 resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-dr1v90-cru-v5-4-34f3021aab51@pigmoral.tech> References: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> In-Reply-To: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778750853; l=6076; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=cTtXPYejpQ6UE0vczng1fEqCuFjSh3psTTgpWrmeTmA=; b=bPXAh0O0ScunhxNAnarQORw8vkE7LeGP/QEY4V4bCfvkZxhnYaCgUFHjP9ZscfaVKEgS/xgHl QYKbzjjJ0/UDeiPBAY+G0B/togsyP0Z2h+IQiyayHJDLKX3kU6KKIOV X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add reset controller support for the Anlogic DR1V90 SoC, which is an auxiliary device associated with the Clock and Reset Unit (CRU). All resets are active-low. Signed-off-by: Junhui Liu --- drivers/reset/Kconfig | 10 ++++ drivers/reset/Makefile | 1 + drivers/reset/reset-dr1v90.c | 140 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 151 insertions(+) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..0bc1723224a4 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -73,6 +73,16 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216 or the BCM2712. =20 +config RESET_DR1V90 + tristate "Anlogic DR1V90 reset controller" + depends on ARCH_ANLOGIC || COMPILE_TEST + depends on ANLOGIC_DR1V90_CRU + select AUXILIARY_BUS + default ARCH_ANLOGIC + help + This enables the reset controller driver for Anlogic DR1V90 SoCs + provided by the CRU unit. + config RESET_EIC7700 bool "Reset controller driver for ESWIN SoCs" depends on ARCH_ESWIN || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..ab2bbc917b73 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_BCM6345) +=3D reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) +=3D reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) +=3D reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) +=3D reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_DR1V90) +=3D reset-dr1v90.o obj-$(CONFIG_RESET_EIC7700) +=3D reset-eic7700.o obj-$(CONFIG_RESET_EYEQ) +=3D reset-eyeq.o obj-$(CONFIG_RESET_GPIO) +=3D reset-gpio.o diff --git a/drivers/reset/reset-dr1v90.c b/drivers/reset/reset-dr1v90.c new file mode 100644 index 000000000000..daa99c797b1a --- /dev/null +++ b/drivers/reset/reset-dr1v90.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include +#include +#include +#include +#include + +#include + +struct dr1v90_reset_map { + u32 offset; + u32 bit; +}; + +struct dr1v90_reset_controller { + struct reset_controller_dev rcdev; + void __iomem *base; + spinlock_t lock; /* protect register read-modify-write */ +}; + +static inline struct dr1v90_reset_controller * +to_dr1v90_reset_controller(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct dr1v90_reset_controller, rcdev); +} + +static const struct dr1v90_reset_map dr1v90_resets[] =3D { + [RESET_OCM] =3D { 0x74, BIT(4)}, + [RESET_QSPI] =3D { 0x74, BIT(5)}, + [RESET_SMC] =3D { 0x74, BIT(6)}, + [RESET_WDT] =3D { 0x74, BIT(7)}, + [RESET_DMAC_AXI] =3D { 0x74, BIT(8)}, + [RESET_DMAC_AHB] =3D { 0x74, BIT(9)}, + [RESET_NPU] =3D { 0x74, BIT(12)}, + [RESET_JPU] =3D { 0x74, BIT(13)}, + [RESET_DDRBUS] =3D { 0x74, BIT(14)}, + [RESET_NIC_HP0] =3D { 0x78, BIT(0)}, + [RESET_NIC_HP1] =3D { 0x78, BIT(1)}, + [RESET_NIC_GP0M] =3D { 0x78, BIT(4)}, + [RESET_NIC_GP1M] =3D { 0x78, BIT(5)}, + [RESET_GPIO] =3D { 0x78, BIT(8)}, + [RESET_IPC] =3D { 0x78, BIT(12)}, + [RESET_USB0] =3D { 0x7C, BIT(0)}, + [RESET_USB1] =3D { 0x7C, BIT(1)}, + [RESET_GBE0] =3D { 0x7C, BIT(4)}, + [RESET_GBE1] =3D { 0x7C, BIT(5)}, + [RESET_SDIO0] =3D { 0x7C, BIT(8)}, + [RESET_SDIO1] =3D { 0x7C, BIT(9)}, + [RESET_UART0] =3D { 0x7C, BIT(12)}, + [RESET_UART1] =3D { 0x7C, BIT(13)}, + [RESET_SPI0] =3D { 0x7C, BIT(16)}, + [RESET_SPI1] =3D { 0x7C, BIT(17)}, + [RESET_CAN0] =3D { 0x7C, BIT(20)}, + [RESET_CAN1] =3D { 0x7C, BIT(21)}, + [RESET_TTC0] =3D { 0x7C, BIT(24)}, + [RESET_TTC1] =3D { 0x7C, BIT(25)}, + [RESET_I2C0] =3D { 0x7C, BIT(28)}, + [RESET_I2C1] =3D { 0x7C, BIT(29)} +}; + +static int dr1v90_reset_control_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct dr1v90_reset_controller *rstc =3D to_dr1v90_reset_controller(rcdev= ); + u32 offset =3D dr1v90_resets[id].offset; + u32 bit =3D dr1v90_resets[id].bit; + u32 reg; + + guard(spinlock_irqsave)(&rstc->lock); + + reg =3D readl(rstc->base + offset); + if (assert) + reg &=3D ~bit; + else + reg |=3D bit; + writel(reg, rstc->base + offset); + + return 0; +} + +static int dr1v90_reset_control_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return dr1v90_reset_control_update(rcdev, id, true); +} + +static int dr1v90_reset_control_deassert(struct reset_controller_dev *rcde= v, + unsigned long id) +{ + return dr1v90_reset_control_update(rcdev, id, false); +} + +static const struct reset_control_ops dr1v90_reset_control_ops =3D { + .assert =3D dr1v90_reset_control_assert, + .deassert =3D dr1v90_reset_control_deassert, +}; + +static int dr1v90_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct dr1v90_reset_controller *rstc; + struct device *dev =3D &adev->dev; + + rstc =3D devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); + if (!rstc) + return -ENOMEM; + + spin_lock_init(&rstc->lock); + + rstc->base =3D dev->platform_data; + rstc->rcdev.dev =3D dev; + rstc->rcdev.nr_resets =3D ARRAY_SIZE(dr1v90_resets); + rstc->rcdev.of_node =3D dev->parent->of_node; + rstc->rcdev.ops =3D &dr1v90_reset_control_ops; + rstc->rcdev.owner =3D THIS_MODULE; + + return devm_reset_controller_register(dev, &rstc->rcdev); +} + +static const struct auxiliary_device_id dr1v90_reset_ids[] =3D { + { + .name =3D "anlogic_dr1_cru.reset" + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, dr1v90_reset_ids); + +static struct auxiliary_driver dr1v90_reset_driver =3D { + .probe =3D dr1v90_reset_probe, + .id_table =3D dr1v90_reset_ids, +}; +module_auxiliary_driver(dr1v90_reset_driver); + +MODULE_AUTHOR("Junhui Liu "); +MODULE_DESCRIPTION("Anlogic DR1V90 reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 625B439734B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-dr1v90-cru-v5-5-34f3021aab51@pigmoral.tech> References: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> In-Reply-To: <20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778750853; l=3292; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=eIpyAVYU/GO0Xd5JaTDqfJlrG1CSuXkafJ6v4JOY3TY=; b=Wes30KbXAJ5MR3vT+KB+6Vc5vOYzqJL/n2KiDUns/Kz7H1iLtpFd0yf9O80YatYCp/jWUJDwx 8IQxH5Y9+zYCkKFkl1+x0ZBdrRUYehq9V1zFOIJ4xfntjb+p5KUm0iJ X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add clocks and introduce the CRU (Clock and Reset) unit node for Anlogic DR1V90 SoC, providing both clock and reset support. The DR1V90 SoC uses three external clocks: - A crystal oscillator as the main system clock. - Two optional external clocks (via IO) for the CAN and WDT modules. The main crystal oscillator frequency is board-dependent. For the dr1v90-mlkpai-fs01 board, a 33.33 MHz oscillator is used and defined accordingly. Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 4 +++ arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 40 ++++++++++++++++++= ++-- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/risc= v/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts index 597407655efd..af78f1a4eecc 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -23,6 +23,10 @@ memory@0 { }; }; =20 +&osc { + clock-frequency =3D <33333333>; +}; + &uart1 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi index 9fe183f5f5c8..574c6608aef0 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -3,6 +3,9 @@ * Copyright (C) 2025 Junhui Liu */ =20 +#include +#include + /dts-v1/; / { #address-cells =3D <2>; @@ -40,6 +43,26 @@ cpu0_intc: interrupt-controller { }; }; =20 + clocks { + can_ext: clock-ext-can { + compatible =3D "fixed-clock"; + clock-output-names =3D "can_ext"; + #clock-cells =3D <0>; + }; + + osc: clock-osc { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc"; + #clock-cells =3D <0>; + }; + + wdt_ext: clock-ext-wdt { + compatible =3D "fixed-clock"; + clock-output-names =3D "wdt_ext"; + #clock-cells =3D <0>; + }; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -81,21 +104,34 @@ plic: interrupt-controller@6c000000 { uart0: serial@f8400000 { compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xf8400000 0x0 0x1000>; - clock-frequency =3D <50000000>; + clocks =3D <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D <71>; reg-io-width =3D <4>; reg-shift =3D <2>; + resets =3D <&cru RESET_UART0>; status =3D "disabled"; }; =20 uart1: serial@f8401000 { compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xf8401000 0x0 0x1000>; - clock-frequency =3D <50000000>; + clocks =3D <&cru CLK_IO_400M_DIV8>, <&cru CLK_CPU_1X>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D <72>; reg-io-width =3D <4>; reg-shift =3D <2>; + resets =3D <&cru RESET_UART1>; status =3D "disabled"; }; + + cru: clock-controller@f8801000 { + compatible =3D "anlogic,dr1v90-cru"; + reg =3D <0x0 0xf8801000 0 0x400>; + clocks =3D <&osc>, <&can_ext>, <&wdt_ext>; + clock-names =3D "osc", "can_ext", "wdt_ext"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; }; --=20 2.54.0 From nobody Fri Jun 12 14:21:42 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0840939D6E7; Thu, 14 May 2026 09:29:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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a=ed25519-sha256; t=1778750853; l=912; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=3bKVlzCRSrUWEZ3gCwiFPOq+BkySOj+CH4yCIImMNMk=; b=eC16vayzbk3SlGcWQ+Jj6qjY7iw8dENwzpW8fCvLtkLSNLi6FaYxcxvY4MK/PhQTBDVGrnP5a Nbm25L6BBqKDCKyeZ7jVSWk8AFSqrK64j4EKygiu3xZ53J94fqiBaAj X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add a MAINTAINERS entry for the Anlogic DR1V90 Clock and Reset Unit (CRU) drivers. Signed-off-by: Junhui Liu --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..4861bf96b996 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1898,6 +1898,15 @@ M: Jiaxun Yang S: Supported F: drivers/rtc/rtc-goldfish.c =20 +ANLOGIC DR1V90 CRU DRIVER +M: Junhui Liu +S: Maintained +F: Documentation/devicetree/bindings/clock/anlogic,dr1v90-cru.yaml +F: drivers/clk/anlogic/cru?dr1* +F: drivers/reset/reset-dr1v90.c +F: include/dt-bindings/clock/anlogic,dr1v90-cru.h +F: include/dt-bindings/reset/anlogic,dr1v90-cru.h + AOA (Apple Onboard Audio) ALSA DRIVER M: Johannes Berg L: linuxppc-dev@lists.ozlabs.org --=20 2.54.0