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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19c7c008sm1461826b3a.46.2026.05.13.23.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 23:39:40 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 14 May 2026 12:09:29 +0530 Subject: [PATCH v5] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260514-bam-fix-v5-1-58f6edb34969@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIACBuBWoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyTHUUlJIzE vPSU3UzU4B8JSMDIzMDU0MT3aTEXN20zApdQxOjRIPUVAsDU/NUJaDqgqJUoDDYpOjY2loAr5Q WZ1kAAAA= X-Change-ID: 20260514-bam-fix-142a0ee8057e To: Vinod Koul , Frank Li , Abhishek Sahu Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Md Sadre Alam , Lakshmi Sowjanya D , Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: WwHC6d-VJHEbPLa6ZL_qawGXvhTPWsV_ X-Authority-Analysis: v=2.4 cv=WsMb99fv c=1 sm=1 tr=0 ts=6a056e2e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Y3rUfbXbY1px-OtE684A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDA2MyBTYWx0ZWRfX46ABNLEwQDAH eJZQDMmOH/lP0icxcbcWMPjJs9EUSMENXZUhQGyqoVvWbfw+uzfPK3Kd+9R8YKyVe5LCw70WEzV qofi3wXhEAhCr8Hp28Xr0mKqZ/NsCssDHDnVmzHBqv6Sgqj+Qv5M9m2is6DCbMqBMVuMdyHZr+B bDA0sIU28NWFzS0RFtaMU7FO8gsxGznb5XDMY2a+aPL9+H8PFactj7bllQYqdYgIFfxXdi07ujX Qlb92zCuvAMW4uPYC1zukMepJYN97G+ufZ2kBW38tMuGT4FWTTiDkDWnCKjVWjFvHMV80TLExEP 8kDGCsRsKR5guR3l1Q7VPHyIOkDlmQLaWc2zNPYbId2ZaqTSImqpauFyKto8n42pWbDua0itvl/ l4PcjP2eFp7jp3TCQgQDo/isz7cvUnW8AoCjf47YvPayLIGsoX5jqrRpAyOWlbFtqnzE+pMtUfg AYEERt4VrGnl+VVqx4w== X-Proofpoint-GUID: WwHC6d-VJHEbPLa6ZL_qawGXvhTPWsV_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140063 From: Md Sadre Alam BAM version 1.6.0 and later changed the behavior of the mask field in command elements for read operations. In newer BAM versions, the mask field for read commands contains the upper 4 bits of the destination address to support 36-bit addressing, while for write commands it continues to function as a traditional write mask. This change causes NAND enumeration failures on platforms like IPQ5424 that use BAM v1.6.0+, because the current code sets mask=3D0xffffffff for all commands. For read commands on newer BAM versions, this results in the hardware interpreting the destination address as 0xf_xxxxxxxx (invalid high memory) instead of the intended 0x0_xxxxxxxx address. Fixed this issue by: 1. Updating the bam_cmd_element structure documentation to reflect the dual purpose of the mask field 2. Modifying bam_prep_ce_le32() to set appropriate mask values based on command type: - For read commands: mask =3D 0 (32-bit addressing, upper bits =3D 0) - For write commands: mask =3D 0xffffffff (traditional write mask) 3. Maintaining backward compatibility with older BAM versions This fix enables proper NAND functionality on IPQ5424 and other platforms using BAM v1.6.0+ while preserving compatibility with existing systems. Fixes: dfebb055f73a2 ("dmaengine: qcom: bam_dma: wrapper functions for comm= and descriptor") Tested-by: Lakshmi Sowjanya D Signed-off-by: Md Sadre Alam Signed-off-by: Varadarajan Narayanan --- Change in [v5] - Split the driver change into a separate patch - Update commit log with 'Fixes' tag Change in [v4] - https://lore.kernel.org/linux-arm-msm/20260206100202.41383= 4-2-quic_mdalam@quicinc.com/ * No change Change in [v3] * Added Tested-by tag Change in [v2] * No change Change in [v1] * Updated bam_prep_ce_le32() to set the mask field conditionally based on command type * Enhanced kernel-doc comments to clarify mask behavior for BAM v1.6.0+ --- include/linux/dma/qcom_bam_dma.h | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_= dma.h index 68fc0e643b1b..d9d07a9ab313 100644 --- a/include/linux/dma/qcom_bam_dma.h +++ b/include/linux/dma/qcom_bam_dma.h @@ -13,9 +13,12 @@ * supported by BAM DMA Engine. * * @cmd_and_addr - upper 8 bits command and lower 24 bits register address. - * @data - for write command: content to be written into peripheral regist= er. - * for read command: dest addr to write peripheral register value. - * @mask - register mask. + * @data - For write command: content to be written into peripheral regist= er. + * For read command: lower 32 bits of destination address. + * @mask - For write command: register write mask. + * For read command on BAM v1.6.0+: upper 4 bits of destination address. + * For read command on BAM < v1.6.0: ignored by hardware. + * Setting to 0 ensures 32-bit addressing compatibility. * @reserved - for future usage. * */ @@ -42,6 +45,10 @@ enum bam_command_type { * @addr: target address * @cmd: BAM command * @data: actual data for write and dest addr for read in le32 + * + * For BAM v1.6.0+, the mask field behavior depends on command type: + * - Write commands: mask =3D write mask (typically 0xffffffff) + * - Read commands: mask =3D upper 4 bits of destination address (0 for 32= -bit) */ static inline void bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr, @@ -50,7 +57,11 @@ bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 add= r, bam_ce->cmd_and_addr =3D cpu_to_le32((addr & 0xffffff) | ((cmd & 0xff) << 24)); bam_ce->data =3D data; - bam_ce->mask =3D cpu_to_le32(0xffffffff); + if (cmd =3D=3D BAM_READ_COMMAND) + bam_ce->mask =3D cpu_to_le32(0x0); /* 32-bit addressing */ + else + bam_ce->mask =3D cpu_to_le32(0xffffffff); /* Write mask */ + bam_ce->reserved =3D 0; } =20 /* @@ -60,7 +71,7 @@ bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr, * @bam_ce: BAM command element * @addr: target address * @cmd: BAM command - * @data: actual data for write and dest addr for read + * @data: actual data for write and destination address for read */ static inline void bam_prep_ce(struct bam_cmd_element *bam_ce, u32 addr, --- base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83 change-id: 20260514-bam-fix-142a0ee8057e Best regards, --=20 Varadarajan Narayanan