From nobody Fri Jun 12 15:58:04 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7FBF383C7F for ; Wed, 13 May 2026 22:46:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778712393; cv=none; b=ZChfmHSuYo7PQ8qrFV5fixRhaQM64uxZ1WabRjpH9So4az+KYatvGKNzGZAm2fc+Uih2mIw+23udQhnWcioftheEKpHVFQZ/fgMguV1aG4TXlI80XVxbYuNfBLxO9W/KTAmAzIo0VvMtsEdRNZGfJts6gM1W9p30rRP17IHt5pI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778712393; c=relaxed/simple; bh=TsWC0ET4/TTTZpeKufKAYDUSKiijDOZz/NUXPah0mYs=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=IGQVY5+8UfBetEPakS5iJH9Nyas54or+rMQc49cGNVv034kS1vo9kfZQKz1XLj/ZaCgic/LW+S97Ihhr07+gvkmYV1wMt5U9wsaeEw88OaifZMPnRUAhDl47zbrJVvcj7xCZUH6XylsEaTLF/sDwvvjw7ID6rnjgLhv6tQhTcjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mLr5p90l; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mLr5p90l" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-2baf7378ad0so60612835ad.0 for ; Wed, 13 May 2026 15:46:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1778712391; x=1779317191; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=3g3SaFXHY3K+SPEAZURdBPeWggmHxUXUovXGkSt9CYM=; b=mLr5p90lBGE8k5u1pb2IiJzyoQJ3/UDThu4YlyjUXM3yz3pM+hfetLwso4H1IHuWY4 27E59erQWoXIcL+8bEXUygVdN6hHAZABwGIVkqCeSTcXok3i00FYIxmV7yq5F5Gkl4ox yYaNdTS5SAHpS0SENDybTKXuw5U0b0O7ZEeos8J7cEExNBCc2kzpyjtN39ICWm7p+Srx lNoHyhUF5tF85DJQmahgSV50kzjV4366OLSEQO8lTgBoIXfZTzatX41VLJ58f/9yBju0 zgYf30tNUZcwg6s1FAy9nY97SIVuAHvhlrydnGqJ4tI4lYjVAni2LVjLwJxGwdrN4YFr dcbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778712391; x=1779317191; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3g3SaFXHY3K+SPEAZURdBPeWggmHxUXUovXGkSt9CYM=; b=A+x+D/x0XwT0QiQ7LXI2bnOaaJDs2+JgY81ASh/mfHNZ5LO67SB/CjMhoLTkG2cmIX zyiSTsupjdc3xQFQIMDwO8+S+gz9/H9Kuwu4QBmsRhRJYxQMVifmdeVf3egVvcN9ZPj/ RGWAA6l4eQDtVgcVsQbRaAZDM2Bb1+e7E4KwN0CFtEeaj4M43W98AaEDE53XqzYcN4bc aBV5Wh5yihTE9QevI/2J3vfvmg6AHALHoKNYzS0hrkZbDmydSntGNHgcCWRv+dlTnSAM WlcaXZKS4h409FBGMPDzrFG4LamQgH/vyt9dBKP7IEoVf1bXJbxAncVEvxuPu4er2v+T 1tKA== X-Forwarded-Encrypted: i=1; AFNElJ/eSf/r1Nkhgu9mG+tS69i+oPKHtpQfA9NoBtZy70BZnSYloKdQzMHQrrl87pQIHV8v7PqlYfxwwpWhYss=@vger.kernel.org X-Gm-Message-State: AOJu0YyxDA3Ldz5wr1l9rTW93/mzcbU3LkaaApcxyd3+/O9E3p9u/GK8 mKV02HXfloSNbECIPpVhKJkA3BaRiGu9cBLtBwuW8TqvPt9CUQax6BW7BYv75xru04ItqyQNxU4 yemRU6XDOBn0SFA== X-Received: from plbjw10.prod.google.com ([2002:a17:903:278a:b0:2bd:2c15:348]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:9cf:b0:2b4:65d8:6a20 with SMTP id d9443c01a7336-2bd2f4cc122mr46800755ad.2.1778712390818; Wed, 13 May 2026 15:46:30 -0700 (PDT) Date: Wed, 13 May 2026 15:46:04 -0700 In-Reply-To: <20260513224608.1859737-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260513224608.1859737-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.631.ge1b05301d1-goog Message-ID: <20260513224608.1859737-2-jmattson@google.com> Subject: [PATCH v3 1/4] KVM: x86: Consolidate CPUID fault handling for emulator and interception logic From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Extract the logic for emulating CPUID faulting (where CPUID #GPs at CPL>0 outside of SMM) into a dedicated helper and use the helper for both the full emulator and the intercepted-CPUID paths. Opportunistically drop kvm_require_cpl(), as kvm_require_cpl() was the one and only user. No functional change intended. Signed-off-by: Sean Christopherson Signed-off-by: Jim Mattson Reviewed-by: Binbin Wu --- arch/x86/include/asm/kvm_host.h | 1 - arch/x86/kvm/cpuid.c | 5 +++-- arch/x86/kvm/cpuid.h | 8 ++++++++ arch/x86/kvm/emulate.c | 6 +----- arch/x86/kvm/kvm_emulate.h | 1 + arch/x86/kvm/x86.c | 18 ++++++------------ 6 files changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index c470e40a00aa..a9005c61619b 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2285,7 +2285,6 @@ void kvm_requeue_exception(struct kvm_vcpu *vcpu, uns= igned int nr, void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fa= ult); void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); -bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); =20 static inline int __kvm_irq_line_state(unsigned long *irq_state, diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e69156b54cff..1c95d1fa3ead 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -2161,9 +2161,10 @@ int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) { u32 eax, ebx, ecx, edx; =20 - if (!is_smm(vcpu) && cpuid_fault_enabled(vcpu) && - !kvm_require_cpl(vcpu, 0)) + if (!kvm_is_cpuid_allowed(vcpu)) { + kvm_queue_exception_e(vcpu, GP_VECTOR, 0); return 1; + } =20 eax =3D kvm_rax_read(vcpu); ecx =3D kvm_rcx_read(vcpu); diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index 039b8e6f40ba..bc4a8428b836 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -7,6 +7,8 @@ #include #include =20 +#include "smm.h" + extern u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; extern bool kvm_is_configuring_cpu_caps __read_mostly; =20 @@ -192,6 +194,12 @@ static inline bool cpuid_fault_enabled(struct kvm_vcpu= *vcpu) MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; } =20 +static inline bool kvm_is_cpuid_allowed(struct kvm_vcpu *vcpu) +{ + return !cpuid_fault_enabled(vcpu) || is_smm(vcpu) || + !kvm_x86_call(get_cpl)(vcpu); +} + static __always_inline void kvm_cpu_cap_clear(unsigned int x86_feature) { unsigned int x86_leaf =3D __feature_leaf(x86_feature); diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index c8c6cc0406d6..3ba09093b5ab 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -3593,12 +3593,8 @@ static int em_sti(struct x86_emulate_ctxt *ctxt) static int em_cpuid(struct x86_emulate_ctxt *ctxt) { u32 eax, ebx, ecx, edx; - u64 msr =3D 0; =20 - ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); - if (!ctxt->ops->is_smm(ctxt) && - (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT) && - ctxt->ops->cpl(ctxt)) + if (!ctxt->ops->is_cpuid_allowed(ctxt)) return emulate_gp(ctxt, 0); =20 eax =3D reg_read(ctxt, VCPU_REGS_RAX); diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 0abff36d0994..45d4a03b202e 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -225,6 +225,7 @@ struct x86_emulate_ops { struct x86_instruction_info *info, enum x86_intercept_stage stage); =20 + bool (*is_cpuid_allowed)(struct x86_emulate_ctxt *ctxt); bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool exact_only); bool (*guest_has_movbe)(struct x86_emulate_ctxt *ctxt); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0a1b63c63d1a..01c6b18d1fe5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1021,18 +1021,6 @@ void kvm_queue_exception_e(struct kvm_vcpu *vcpu, un= signed nr, u32 error_code) } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_queue_exception_e); =20 -/* - * Checks if cpl <=3D required_cpl; if true, return true. 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Wed, 13 May 2026 15:46:31 -0700 (PDT) Date: Wed, 13 May 2026 15:46:05 -0700 In-Reply-To: <20260513224608.1859737-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260513224608.1859737-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.631.ge1b05301d1-goog Message-ID: <20260513224608.1859737-3-jmattson@google.com> Subject: [PATCH v3 2/4] KVM: x86: Remove supports_cpuid_fault() helper From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function, supports_cpuid_fault(), tests specifically for guest support of Intel's CPUID faulting feature. It does not test for guest support of AMD's CPUID faulting feature. To avoid confusion, remove the helper. Signed-off-by: Jim Mattson Reviewed-by: Binbin Wu --- arch/x86/kvm/cpuid.h | 5 ----- arch/x86/kvm/x86.c | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index bc4a8428b836..95d09ccbf951 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -183,11 +183,6 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu= *vcpu) return x86_stepping(best->eax); } =20 -static inline bool supports_cpuid_fault(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.msr_platform_info & MSR_PLATFORM_INFO_CPUID_FAULT; -} - static inline bool cpuid_fault_enabled(struct kvm_vcpu *vcpu) { return vcpu->arch.msr_misc_features_enables & diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 01c6b18d1fe5..c60773349f35 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4252,7 +4252,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_MISC_FEATURES_ENABLES: if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && - !supports_cpuid_fault(vcpu))) + !(vcpu->arch.msr_platform_info & MSR_PLATFORM_INFO_CPUID_FAULT))) return 1; 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charset="utf-8" On AMD CPUs, CPUID faulting support is advertised via CPUID.80000021H:EAX.CpuidUserDis[bit 17] and enabled by setting HWCR.CpuidUserDis[bit 35]. Advertise the feature to userspace regardless of host CPU support. Allow writes to HWCR to set bit 35 when the guest CPUID advertises CpuidUserDis. Update cpuid_fault_enabled() to check HWCR.CpuidUserDis as well as MSR_FEATURE_ENABLES.CPUID_GP_ON_CPL_GT_0. Signed-off-by: Jim Mattson Reported-by: Sashiko:gemini/gemini-3.1-pro-preview --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/cpuid.h | 5 +++-- arch/x86/kvm/x86.c | 18 ++++++++++++------ 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 6673601246b3..0eeae121b0a6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -888,6 +888,7 @@ #define MSR_K7_HWCR_IRPERF_EN_BIT 30 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35 +#define MSR_K7_HWCR_CPUID_USER_DIS BIT_ULL(MSR_K7_HWCR_CPUID_USER_DIS_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 #define MSR_K7_HWCR_CPB_DIS_BIT 25 diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 1c95d1fa3ead..8e5340dd2621 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1248,7 +1248,7 @@ void kvm_initialize_cpu_caps(void) F(AUTOIBRS), EMULATED_F(NO_SMM_CTL_MSR), /* PrefetchCtlMsr */ - /* GpOnUserCpuid */ + EMULATED_F(GP_ON_USER_CPUID), /* EPSF */ F(PREFETCHI), F(AVX512_BMM), diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index 95d09ccbf951..fc96ba86c644 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -185,8 +185,9 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu = *vcpu) =20 static inline bool cpuid_fault_enabled(struct kvm_vcpu *vcpu) { - return vcpu->arch.msr_misc_features_enables & - MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; + return (vcpu->arch.msr_misc_features_enables & + MSR_MISC_FEATURES_ENABLES_CPUID_FAULT) || + (vcpu->arch.msr_hwcr & MSR_K7_HWCR_CPUID_USER_DIS); } =20 static inline bool kvm_is_cpuid_allowed(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c60773349f35..6581018db16b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3990,22 +3990,28 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) break; case MSR_EFER: return set_efer(vcpu, msr_info); - case MSR_K7_HWCR: - data &=3D ~(u64)0x40; /* ignore flush filter disable */ - data &=3D ~(u64)0x100; /* ignore ignne emulation enable */ - data &=3D ~(u64)0x8; /* ignore TLB cache disable */ - + case MSR_K7_HWCR: { /* * Allow McStatusWrEn and TscFreqSel. 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Wed, 13 May 2026 15:46:33 -0700 (PDT) Date: Wed, 13 May 2026 15:46:07 -0700 In-Reply-To: <20260513224608.1859737-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260513224608.1859737-1-jmattson@google.com> X-Mailer: git-send-email 2.54.0.631.ge1b05301d1-goog Message-ID: <20260513224608.1859737-5-jmattson@google.com> Subject: [PATCH v3 4/4] KVM: selftests: Update hwcr_msr_test for CPUID faulting bit From: Jim Mattson To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, ctpence@google.com Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add BIT_ULL(35) (CpuidUserDis) to the valid mask in hwcr_msr_test, now that KVM accepts writes to this bit when the guest CPUID advertises CpuidUserDis. Signed-off-by: Jim Mattson --- tools/testing/selftests/kvm/include/x86/processor.h | 1 + tools/testing/selftests/kvm/x86/hwcr_msr_test.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 77f576ee7789..9cb1efd910ec 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -209,6 +209,7 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) +#define X86_FEATURE_GP_ON_USER_CPUID KVM_X86_CPU_FEATURE(0x80000021, 0, EA= X, 17) #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX,= 2) =20 diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testin= g/selftests/kvm/x86/hwcr_msr_test.c index 8e20a03b3329..53b7971aa072 100644 --- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c +++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c @@ -11,12 +11,17 @@ void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit) { const u64 ignored =3D BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); - const u64 valid =3D BIT_ULL(18) | BIT_ULL(24); - const u64 legal =3D ignored | valid; + u64 valid =3D BIT_ULL(18) | BIT_ULL(24); u64 val =3D BIT_ULL(bit); u64 actual; + u64 legal; int r; =20 + if (kvm_cpu_has(X86_FEATURE_GP_ON_USER_CPUID)) + valid |=3D BIT_ULL(35); + + legal =3D ignored | valid; + r =3D _vcpu_set_msr(vcpu, MSR_K7_HWCR, val); TEST_ASSERT(val & ~legal ? !r : r =3D=3D 1, "Expected KVM_SET_MSRS(MSR_K7_HWCR) =3D 0x%lx to %s", --=20 2.54.0.631.ge1b05301d1-goog