From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DF3F43DA42 for ; Wed, 13 May 2026 13:10:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677850; cv=none; b=ec0whJoqUO1EviRFWuFn5OrWYhqvHoWLMqdgwdsrsRDBY0lGapUiSa1dsV7qylo8ITeY7WNciD7IHc99pYRtPzt/Mp2cWPHP0fQbwMlxky6o4cZa1pqrA8l3i9uk9sVF5+uWDtEHhLL9gVNQiWVQ2gmsp4KtwcLNAUZpyrKDpBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677850; c=relaxed/simple; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uf3CbG7XGF914uTH66oUIMhgQQ1uCzc5OdZSUAQGoVvz63q5zxD327h7ngTEXHc+Sy1d+1a/Y4r7jslGYLzFRXtTRNzQwT/fMBOG6dQSVdqn/LFzzv727cJdqTguKGdzfDZs8jGTRLpRdCfPgSWzSt66ELlVd6ee9MhXHqXkWTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=SDOP71TE; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="SDOP71TE" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7B472C6C; Wed, 13 May 2026 15:10:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677833; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SDOP71TE7aXTczPRQ2Oi8CMp25ioNDbS7ZIneDlsb5noTp/2RIXvzkiugIGRzpYrT xn+28JMbd95/oXWR0Z3pNLpFIrKNLAT5FnIPcgMPXhsXARfby7AxsvwLPHXZYwuzAv KpgG1jKt39xEHpRqHxDx8tPpFtIKfOL4m9JduPH4= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:10 +0300 Subject: [PATCH v3 01/13] drm/bridge: tc358762: Clean up register defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-1-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2518; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqBHhKWJGWS0f43L0Ypn8/YwO++dxwkWGJDZf+7 yyNWQxyK/mJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCagR4SgAKCRD6PaqMvJYe 9Yu3EACfIiFmS8Ilz5qtw0z4fxk30MGTx3jqaV+hSNB/omHnpHiYdrAvzeB+mzpuvZpZVT/kEJb vrizuqad0mA4tyPB2SAXUxCyeCCH7NKXydiZ0/lI4w+mtvGYSZjiT9GqHK36VUJcwZUrrwNEzFY pMJvWulfo9TtWKm5BiN5OQQZ+K2BWN1V/Yj11JUFf83ajUK0RC9UfZQjmyA5vCLwh9y410w2aBv FpDXcC63nmZVCE2juty11K7Oh6HtXm18ol7wVacfyVD9XurByBdnEUp7Jsh4qcdk92Oe7nvQ/Kp LRADyqTWR8V0LNWRcXS6XjgjncEljwqJMfwt0pjawebLLtqM+SbKAu/5LhVhsrKTQEB3nH0/T0X aW5K9uajLBJtw0zhtbU9m2Th22YZ9kKWH2C5fYJN7suV2Lgych2W5/4y7kZ+yZEkOUYC32ZYfBF 8K3OdGW9LKl8Z3uhe0gWIjNAdS1JzUnF6z4Jn5oILZQZUqbUUAfdM5G4pNxnJHuVeS+PsruTm1l Eop87NWlCYchrGGmfnBJLTg7IYhdPgbDv99NUjJxfLKyiOv5YbeYllsm5xw+OvTAelBLxZgVxQ0 S5u7c2NiwGamQ1xMO3mF5HSgl1WH6grQBvn3epr6zuSMYbTQHUs4Dei8i8JVXc6Kqqf4VhS9AM6 p04Y69e2sTMUwjg== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Move the defines around and rename for clarity and consistency. No functional change. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 98df3e667d4a..833fd9913c75 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -29,17 +29,22 @@ =20 /* PPI layer registers */ #define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_STARTPPI_STARTPPI BIT(0) + #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ #define PPI_D0S_ATMR 0x0144 #define PPI_D1S_ATMR 0x0148 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ -#define PPI_START_FUNCTION 1 =20 /* DSI layer registers */ #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_STARTDSI_STARTDSI BIT(0) + #define DSI_LANEENABLE 0x0210 /* Enables each lane */ -#define DSI_RX_START 1 +#define DSI_LANEENABLE_CLEN BIT(0) +#define DSI_LANEENABLE_L0EN BIT(1) +#define DSI_LANEENABLE_L1EN BIT(2) =20 /* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 = */ #define LCDCTRL 0x0420 /* Video Path Control */ @@ -60,14 +65,8 @@ /* System Controller Registers */ #define SYSCTRL 0x0464 =20 -/* System registers */ #define LPX_PERIOD 3 =20 -/* Lane enable PPI and DSI register bits */ -#define LANEENABLE_CLEN BIT(0) -#define LANEENABLE_L0EN BIT(1) -#define LANEENABLE_L1EN BIT(2) - struct tc358762 { struct device *dev; struct drm_bridge bridge; @@ -118,7 +117,7 @@ static int tc358762_init(struct tc358762 *ctx) u32 lcdctrl; =20 tc358762_write(ctx, DSI_LANEENABLE, - LANEENABLE_L0EN | LANEENABLE_CLEN); + DSI_LANEENABLE_L0EN | DSI_LANEENABLE_CLEN); tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D0S_ATMR, 0); @@ -141,8 +140,8 @@ static int tc358762_init(struct tc358762 *ctx) tc358762_write(ctx, SYSCTRL, 0x040f); msleep(100); =20 - tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); - tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START); + tc358762_write(ctx, PPI_STARTPPI, PPI_STARTPPI_STARTPPI); + tc358762_write(ctx, DSI_STARTDSI, DSI_STARTDSI_STARTDSI); =20 msleep(100); =20 --=20 2.43.0 From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0159444B663 for ; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Define SYSCTRL fields. No functional changes. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 833fd9913c75..c8b9984ff301 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -10,6 +10,7 @@ * Eric Anholt */ =20 +#include #include #include #include @@ -64,6 +65,19 @@ =20 /* System Controller Registers */ #define SYSCTRL 0x0464 +#define SYSCTRL_DPIDATA_IO_MASK GENMASK_U32(1, 0) +#define SYSCTRL_DPIDATA_IO_1MA 0 +#define SYSCTRL_DPIDATA_IO_2MA 1 +#define SYSCTRL_DPIDATA_IO_3MA 2 +#define SYSCTRL_DPIDATA_IO_4MA 3 +#define SYSCTRL_DPISTB_IO_MASK GENMASK_U32(3, 2) +#define SYSCTRL_DPISTB_IO_1MA 0 +#define SYSCTRL_DPISTB_IO_2MA 1 +#define SYSCTRL_DPISTB_IO_3MA 2 +#define SYSCTRL_DPISTB_IO_4MA 3 +#define SYSCTRL_PCLKDIV_MASK GENMASK_U32(11, 8) +#define SYSCTRL_PCLKDIV_DIV_2 2 +#define SYSCTRL_PCLKDIV_DIV_3 4 =20 #define LPX_PERIOD 3 =20 @@ -137,7 +151,11 @@ static int tc358762_init(struct tc358762 *ctx) =20 tc358762_write(ctx, LCDCTRL, lcdctrl); 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Wed, 13 May 2026 15:10:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677835; bh=SvGr15LIkhTg2rbMsXyqYuERM2cP+iPiWWKsOCPGKDM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tbg0yfkl28MegPUR/DCcFtoe3i+gfmk1BhSjrwmtcThNmOJ+MrjQV4P/zcD0UfqGc S6LKDwhOjZG/HzD6xjkL3d4kx73V2niuVS0OUMofxhwunWHJb/EO3kfUBn9yJ7Iga0 v/C0ncu1vyDZ6MJk8ERNxiYSSeCjsNy03cBQTexU= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:12 +0300 Subject: [PATCH v3 03/13] drm/bridge: tc358762: Improve LCDCTRL defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-3-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 LCDCTRL fields are quite wrong in the driver. Fix the field defines. A few notes about the wrong fields: LCDCTRL_VSDELAY(1) actually sets LCDCTRL_DCLK_POL LCDCTRL_UNK6 | LCDCTRL_VTGEN actually set LCDCTRL_PXLFORM_RGB888 LCDCTRL_RGB888 actually sets LCDCTRL_DPI_EN The total still resulted in a working display even if the defines were quite wrong. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index c8b9984ff301..669052074974 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -47,17 +47,22 @@ #define DSI_LANEENABLE_L0EN BIT(1) #define DSI_LANEENABLE_L1EN BIT(2) =20 -/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 = */ +/* LCDC/DPI Registers */ #define LCDCTRL 0x0420 /* Video Path Control */ #define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */ -#define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */ -#define LCDCTRL_UNK6 BIT(6) /* Unknown */ -#define LCDCTRL_EVTMODE BIT(5) /* Event mode */ -#define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */ -#define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ -#define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */ -#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ -#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */ +#define LCDCTRL_VTGEN BIT(1) /* Use chip clock for timing */ +#define LCDCTRL_PXLFORM GENMASK_U32(6, 4) +#define LCDCTRL_PXLFORM_RGB666 0 /* x:R:G:B 6:8:8:8 */ +#define LCDCTRL_PXLFORM_RGB666_24 1 /* x:R:x:G:x:B 2:6:2:6:2:6 */ +#define LCDCTRL_PXLFORM_RGB565 2 /* x:R:G:B 8:5:6:5 */ +#define LCDCTRL_PXLFORM_RGB565_1 3 /* x:R:x:G:x:B 3:5:2:6:3:5 */ +#define LCDCTRL_PXLFORM_RGB565_2 4 /* x:R:x:G:x:B:x 2:5:3:6:2:5:1 */ +#define LCDCTRL_PXLFORM_RGB888 5 /* R:G:B 8:8:8 */ +#define LCDCTRL_DPI_EN BIT(8) +#define LCDCTRL_HSYNC_POL BIT(17) /* Polarity of HSYNC signal */ +#define LCDCTRL_DE_POL BIT(18) /* Polarity of DE signal */ +#define LCDCTRL_VSYNC_POL BIT(19) /* Polarity of VSYNC signal */ +#define LCDCTRL_DCLK_POL BIT(20) /* Polarity of pixel clock */ =20 /* SPI Master Registers */ #define SPICMR 0x0450 @@ -140,14 +145,16 @@ static int tc358762_init(struct tc358762 *ctx) =20 tc358762_write(ctx, SPICMR, 0x00); =20 - lcdctrl =3D LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 | - LCDCTRL_UNK6 | LCDCTRL_VTGEN; + lcdctrl =3D FIELD_PREP(LCDCTRL_PXLFORM, LCDCTRL_PXLFORM_RGB888) | + LCDCTRL_DPI_EN; + + lcdctrl |=3D LCDCTRL_DCLK_POL; =20 if (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC) - lcdctrl |=3D LCDCTRL_HSPOL; + lcdctrl |=3D LCDCTRL_HSYNC_POL; =20 if (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC) - lcdctrl |=3D LCDCTRL_VSPOL; + lcdctrl |=3D LCDCTRL_VSYNC_POL; =20 tc358762_write(ctx, LCDCTRL, lcdctrl); =20 --=20 2.43.0 From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18622466B5E for ; Wed, 13 May 2026 13:10:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677856; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 SYSCTRL affects the DPI output and the clock tree, but we configure it late, when the DPI output is already enabled and clocks are running. Move the SYSCTRL configuration to the beginning, before anything is enabled. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 669052074974..d119e399f7a2 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -135,6 +135,13 @@ static int tc358762_init(struct tc358762 *ctx) { u32 lcdctrl; =20 + tc358762_write(ctx, SYSCTRL, + FIELD_PREP(SYSCTRL_DPIDATA_IO_MASK, SYSCTRL_DPIDATA_IO_4MA) | + FIELD_PREP(SYSCTRL_DPISTB_IO_MASK, SYSCTRL_DPISTB_IO_4MA) | + FIELD_PREP(SYSCTRL_PCLKDIV_MASK, SYSCTRL_PCLKDIV_DIV_3)); + + msleep(100); + tc358762_write(ctx, DSI_LANEENABLE, DSI_LANEENABLE_L0EN | DSI_LANEENABLE_CLEN); tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); @@ -158,13 +165,6 @@ static int tc358762_init(struct tc358762 *ctx) =20 tc358762_write(ctx, LCDCTRL, lcdctrl); =20 - tc358762_write(ctx, SYSCTRL, - FIELD_PREP(SYSCTRL_DPIDATA_IO_MASK, SYSCTRL_DPIDATA_IO_4MA) | - FIELD_PREP(SYSCTRL_DPISTB_IO_MASK, SYSCTRL_DPISTB_IO_4MA) | - FIELD_PREP(SYSCTRL_PCLKDIV_MASK, SYSCTRL_PCLKDIV_DIV_3)); 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Wed, 13 May 2026 15:10:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677837; bh=6zcLMRl7/3+FLXDobuB5DdCoAuM7Hiugvtoz8PSqVtg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HC4D6ZsUeDD5QMTPh1EI9txIa+OBD8/ryH+SaZgjs52XZsmM1g+PRxk10Rpp4fG1E 2iJ91TCV2DdJVq2Km+2vqywu4OmnyHW8GSpuyZTkm5UxQ/g1yj/CBFHqn3uSM9Np04 l16ScwaCTNr2G8vmqAy+RGxZs/3B2KN8o3XakXUA= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:14 +0300 Subject: [PATCH v3 05/13] drm/bridge: tc358762: Drop SPICMR write Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-5-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Drop write to SPICMR. It's unclear why the write is there, as SPI is not supported in the driver, and it's mostly just writing zeroes to already zero fields (reset defaults). None of the zero bits written disable anything wrt. SPI. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index d119e399f7a2..a9c30acf1b14 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -150,8 +150,6 @@ static int tc358762_init(struct tc358762 *ctx) tc358762_write(ctx, PPI_D1S_ATMR, 0); tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD); =20 - tc358762_write(ctx, SPICMR, 0x00); - lcdctrl =3D FIELD_PREP(LCDCTRL_PXLFORM, LCDCTRL_PXLFORM_RGB888) | LCDCTRL_DPI_EN; =20 --=20 2.43.0 From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C39D5477986 for ; Wed, 13 May 2026 13:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677859; cv=none; b=uYZZPxwVNBoRbIiF8ti41JWQpy7yVUfVvnymMyT2UEo/ScCYnQyBcPjM1uKvngc9RYTbsWIod/wy8pgQNCgkaya7ftjx0b1PKBNdEC81VNLsTSRR8sh5E2lel5EzfrjHv7B6G+DQdyQHlMBRHAWPoegyWYZ1Y4LdA3s/fidVm88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677859; c=relaxed/simple; bh=bGsU16PnfHUZUKFcdLSxXUytLC8RK1SYoTTCPWtBrT4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fKBSJpa1PuaWgC2oHGPxscZqNulViV/w1uN2JSVrIltClhjLZni003NVA0VCM1h0TvfuAF0gniacw2rSSNL+mQ1LoMaYRKswy32ILC+tnywS1wfitPwtqnBMHDSlgNuhl49PVwy6K1ihh1peVee2j7V1glM9KrncqNwIEebWugc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=e4cAPxk5; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="e4cAPxk5" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 8ACC223B9; Wed, 13 May 2026 15:10:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677838; bh=bGsU16PnfHUZUKFcdLSxXUytLC8RK1SYoTTCPWtBrT4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=e4cAPxk5MefRvrxv3ogR4+nEGHXuj4xwXIwl/pD8LSHF/HonhVfyBZVAPJ0ID/n2A FAPli3YWv8hRZYAQJYikqvzB/2ughnxQdCRRQgaph2cpwhkmyZTOIO+ejXumpa17HR wWZKShLH5Bb2TY4U05aKxs96Z/DPG35V21dOVAKo= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:15 +0300 Subject: [PATCH v3 06/13] drm/bridge: tc358762: Improve DPI enable handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-6-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1676; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=bGsU16PnfHUZUKFcdLSxXUytLC8RK1SYoTTCPWtBrT4=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqBHhMlfg9a3mr0GcykUQc1mvvw6dRO51DRjw+f kDY/RYu26qJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCagR4TAAKCRD6PaqMvJYe 9WRhEACizursv9RIz9xKubsC0U+qYmJE8qg1fJ0OgpLpMUjqVuxT2ub6522ziWhWiipq3rzUoyr /NB2PEBfy5aNDPNyOgj4Ggs01kPWCNiRXgiXNCcjUABwqEtrrIjqFLU5FxYULHeFZZxsKk52rKT PzgSVmM4lgBSrwL7Y/z5Cnsc4/2dz/Xy1Xfwyob9UjDNgddZRTgfOEcAVG95itElw6QDHI+jPvN JpvFgo7ZhiVQemM44Qifg0xWx80KqBvCkBfaeUx0kDNdHIc2ObdY1Yv6IkDRs3pvAFMPn9bnWv0 cSaPLS3/jUtx2a3kbdOW/+f8PBkWqFPlQzVtmLIyfZAaIzrmX6zNLwxoYhZyIfHeBYTROiB9TqS JqaWnxxoi71ZSe0SjkhFMo796vu/7jH6KtHUrJ8O0FkouGeXb+oOMqaW1f3MwX8RvuGax1v1mnr XmS6zf9CS8Qh56/qdhHL4zchP1u8Fh3bKZfAOdsR+bct8Kj8xDBITorPE663A9NHfbSCBvBVcYf 9BI/sCF5rFSbE5uFaeOa9nUA9IZzM/Uh3jpUV3G6LCtqowAqX7qoW/Ybs0673TiBOi/qS6Hyh61 z0uqVz9fnrcuHtR11fSQhCI5SsPqBWk52xYWLMnL0tblCvL2A9wlRbmvHj0Wyq0dWQQKPXXW1IE ponzYgZfEMZBekA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 The HW reset defaults has DPIENABLE bit as set. In the current driver we configure and enable various things while DPIENABLE is set. This results in a temporary DPI output with wrong timings, which may cause artifacts on the panel. Fix this by clearing DPIEANBLE as the first thing when we start to enable the display. DPIENABLE is set later with the rest of the LCDCTRL configuration, and at that time we have done all the other configurations. Also, for symmetry and possibly improving the DPI output at disable time, explicitly disable DPIENABLE when disabling the bridge. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index a9c30acf1b14..7840ab3454f6 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -135,6 +135,12 @@ static int tc358762_init(struct tc358762 *ctx) { u32 lcdctrl; =20 + /* + * DPIENABLE has reset default of 1. Make sure we don't output on + * DPI until we have finished the coniguration. + */ + tc358762_write(ctx, LCDCTRL, 0); + tc358762_write(ctx, SYSCTRL, FIELD_PREP(SYSCTRL_DPIDATA_IO_MASK, SYSCTRL_DPIDATA_IO_4MA) | FIELD_PREP(SYSCTRL_DPISTB_IO_MASK, SYSCTRL_DPISTB_IO_4MA) | @@ -186,6 +192,9 @@ static void tc358762_post_disable(struct drm_bridge *br= idge, =20 ctx->pre_enabled =3D false; =20 + /* Turn off the DPI output */ + tc358762_write(ctx, LCDCTRL, 0); + if (ctx->reset_gpio) gpiod_set_value_cansleep(ctx->reset_gpio, 0); =20 --=20 2.43.0 From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E64C047798F for ; Wed, 13 May 2026 13:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677859; cv=none; b=P/suEXPmxnXOubR0j4krzwo8SvqNaijbHmeaFmEsvteTumUN3HKs69BHreJM3SLmbvdDvP+6vtrkXJyVDRk5GUpAE2BWntuwLKEzSehr1ZL8l41WY84Dfft0QWozKLnnTHnaguYa6jXZ2HYPrXbjELed6Bfzl5KgHxWXdYkdduQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677859; c=relaxed/simple; bh=JR1XaCynAqkLEsI0fyomn5txwykOGGzcMsQKm/y2zys=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rbMDgy9M52rOYjVZYBCIxhIl6kYrEr6lVf0ymltBjKSuaNh4oDG5ACh0qJPqU5M+qSNa5n/KFnXT9SHM/Qc7rKHl0Gouv8h1qIYgbIc44ZPgVURM5NG7TYoGdwxwCvCYXQHJpCNBPd4LmF+sQ31co1t+qX5Rygws7AU6WdAON70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=MYL7M+Av; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="MYL7M+Av" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 8966C266F; Wed, 13 May 2026 15:10:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677839; bh=JR1XaCynAqkLEsI0fyomn5txwykOGGzcMsQKm/y2zys=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MYL7M+AvEt5RMit16C0Ua3VY5YSoTluk+6GDXFAAq90T9wW2TrYWrK2o2YRPUoGEm 4O+maRrbxy+w4QWMtr9hv6zbiJza0Fabk6iyUFl3bgQrJU0TJ3QdD2dLitlMko8/Vd 9uYBadzZntDlVQ2HbUh/5WykzL2kqX+7DeZ7t30g= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:16 +0300 Subject: [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1121; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=JR1XaCynAqkLEsI0fyomn5txwykOGGzcMsQKm/y2zys=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqBHhMEz+LoP63lR/6OSzHGt0ddSh6P874/4XGF RwELM9trFKJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCagR4TAAKCRD6PaqMvJYe 9epsD/439EkhD9+3YZGy9F2AL83IXY4QQ1paEqec2sGfhftvvQvl62N2PRoaWcHTuw6W5WMPmDW k5KMFszGFmthmMNGA+wGm0lmpcLMyofhJk1K256MlxmGy8DQRbhWpgLNX+wsLi6JRrspgjJV7ny 1ZXH8srTogNVLpcrVoVNjNF/IVRP83bwBFQffJe6NsLSxGPKvM38DpxV/XDGhGU7kkrNzm+eSxg odW/FQJTWxmB/hf94IeFvgIozj8jP/mfW+cT20oJqgq+iDqFyeXQt3fWomwhtcX7eX+p+Dm7KJ+ wLsW9Y/cWOaOoCRhImXeryfRml0WyhRlpLuHKT2NWM2rIuwZHL1rxUO8QYF27ZVx66G79celJOU tpSrVVnjbRj0QZJUS/AAP68RXd0NwWy6RZGovSzdmMOXe3TTZ+X2loJPGhzd32iRiFgIl0SHTW6 8wYEHXSeBHx4Jjmrt8OxVV+m5tcZppwk2R/WmJtfPEnBJleMfMzuoJ263FN9KwOM6agtsKvBEj1 M4aMUXae09+3ts9HLJwjFwilU6YaTtVkJb+7WHuzTlKx3oxeB5jeRacfR2MNHOj34tCQZ8+2swm FL0NkGOtpK/DWzC1qYrR6r3AILkeqeuB23qVhBd+VssTMpkQt9dZDSqNxWx1OGNL8chX0gDNvqs B3R7RRMQ/3zhrWg== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Update comment about the number of lanes. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 7840ab3454f6..c5734c4df440 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -306,7 +306,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) ctx->dev =3D dev; ctx->pre_enabled =3D false; =20 - /* TODO: Find out how to get dual-lane mode working */ + /* + * When using DSI clk for pixel clock (only mode supported in the driver), + * the pclk is derived directly from the DSI byteclk via simple divider, + * which is either 2 or 3. + * The required divider can be calculated with bitspp / 8 / nlanes. Thus, + * for RGB888, only nlanes =3D 1 works as nlanes =3D 2 would require divi= der + * of 1.5. + */ dsi->lanes =3D 1; dsi->format =3D MIPI_DSI_FMT_RGB888; dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | --=20 2.43.0 From nobody Fri Jun 12 17:36:49 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F00A47A0C4 for ; Wed, 13 May 2026 13:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677861; cv=none; b=OXtqlXFpSc2ONTOozYzAz0jFNzPZVl/vJzMI+w655fX8L34bEEaKFtQ+nCrjF0YTD5EP6V3539L8Ls66BRNMvg7QVkKvRNv6x/+KvO//hn1FH+7wwgrTnXhciyX38t+FobhTujqtoXisc7kgCk3GuhDCFoA2YCtdTGBVdwdNsiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778677861; c=relaxed/simple; bh=bQoNmKi2Dt5CKjdPIka2IqzxG7UblvKfvHzyil3gmsA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E+cLO7XIRTQUz7knUNfaEHo/gFSjFqvZeJdfqJ40mnwd8jdLNeXDn/jtzpjhNYMeaOxntryrVl8tiBsZlHwpOHM7ne4Y+b6cInCQG0xbFZZ6RcqkezabXqh+BmJrnxYUo1fg8nlPuqrcE52EGbeo/FkgtB7L+z6F07+QMpoeXsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=Djs+uGke; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="Djs+uGke" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 86AF826A5; Wed, 13 May 2026 15:10:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778677840; bh=bQoNmKi2Dt5CKjdPIka2IqzxG7UblvKfvHzyil3gmsA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Djs+uGkeUjZXtT8K15fZX74d0VsSdyWaH/rDAIZNpeE17ulNPH7mTSOU4sshE5TIx kQhbqMSB5Zb9SW0rOxTFJ24emjUFmo80ToxVrCDb6ZsxqtHGiGUTK8b5DDEjUM4JKn 1fl/JkRVHkOLVgAPVX3Qh1MpYWaY6aBM31LbutsY= From: Tomi Valkeinen Date: Wed, 13 May 2026 16:10:17 +0300 Subject: [PATCH v3 08/13] drm/bridge: tc358762: Support VTG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-tc358762-fixes-v3-8-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> In-Reply-To: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3412; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=bQoNmKi2Dt5CKjdPIka2IqzxG7UblvKfvHzyil3gmsA=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBqBHhNpneTpk3IRTZNrN4xFQY9GQs+JRmpIC2Yk FpDN8eZhpyJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCagR4TQAKCRD6PaqMvJYe 9eOnD/90pkIdR+UuTuGyCw39VXJr8u8iIDPEf7WNwBVl1rKJ/DdjhUgDutGAIA1prJM1+UNPVrm oP5vCub6R0HV5FSVRcfSHRGcUH+lkxObhPKkZ6uw0VzWwy20k5Dw/LgUKMTpExMITQ9kQH5tlVk 9devhufeVWXoGKkKxUKZfvripusbsywA8lXADIe10MOYrgWL899N5lPhPTzuTQvBtRRZwHckio8 hUOfiKdaj2LkSboHa9nqh+s8l6Q653coFY5+ktcoZML6a49DASUNFsaxaaYLV9OVuOv0xq8XLPI enL3/yN4kUjXngs7ZA0IWQtnuHwGp29j9EnRfOTCU4McZUjXc4L1roYHBd2BEquMi8CpJ/IHsaf w7fq0IhmIIyuG1qzPiljriHIZ+BbuBfnf8YkMyT2ActqUYZ0yO1Dcu+v1WUcMI1DZuAw/ERzwFa xG2Ce53TWZPyle1hx5Uo5iE9D8i8oseAXvkuOSUn2JzBYdZqvWRFWyXACLgb8AncZ2bYtuOpZpw dUgIWYe3/Wrzo+ftCZ6BWYTRtFvLbV6a6YssNo6C1SVmO8ZtZGoRlGq/2qS/GaN4UDVwrhkW3w0 0u7kA1Chkkm7F5KtPn1/rEYDEwTe0DLqK461AxZ4/Mi+Z/TlgRnN9ogRqdiFZPV1iJSeytgE6Ob iDNSVuMT7JTj/Bg== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 TC358762 can generate the DPI output's timings in two ways, either Video Timings Generator (VTG) on or off: - VTG off: Duplicate the timings coming from the DSI. This requires DSI pulse mode. - VTG on: Sync frame on DSI VSync Start, but the exact output timings are defined in TC358762 registers. This can be used with DSI event/burst mode. We are currently using VTG off in the driver. I observe that the hsync signal, on my HW setup, is not 100% stable with VTG off, and it seems to lengthen by a single clock every now and then. However, it then stabilizes later. To me the DSI input looks solid, but that is more challenging to measure exactly. So I have not found the root cause for this. Turning VTG on removes that instability. As I dont' see any downsides with enabling VTG (and it would allow extending the driver to use event/burst mode in the future), let's always enable the VTG. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index c5734c4df440..2d9491e8e582 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -19,6 +19,7 @@ #include =20 #include