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Wed, 13 May 2026 06:40:56 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368b00d2131sm4317403a91.1.2026.05.13.06.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 06:40:55 -0700 (PDT) From: Imran Shaik Date: Wed, 13 May 2026 19:10:36 +0530 Subject: [PATCH 1/4] dt-bindings: clock: qcom: Add Shikra Display clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-shikra-dispcc-gpucc-v1-1-5fd673146ab2@oss.qualcomm.com> References: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> In-Reply-To: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: Ez0jgg3fAyKD_3W0_aVya9WxHto3UTBS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE0MSBTYWx0ZWRfXxeGT6qFCZmkP Vr8fTXLUFYXDeckMx2ef+cX6Fbv+pXHpBxjgvpNJN9T9hfry5hfMqVP4caZHN0P1R/1HW3UpdsE eRFb3sxk3kfdh1syVFy4WR4Y6j9T/Iqbp8jUeZKNWVMe5KDQ9t2ghD0xqFjU5evJXD4Dg9ZdS83 pO3GVbLyj41W5dUjpbnWF+W2qbfC6sq4NU8aQ/ipqBEN/z1sQiemmPrDNvASTrPX81QbzQ+twEq xZNa7Nt38xVqOLuUyweISXTUewp/xj6A4s+898xtqFlgTIVRywp8hJdQilnvu0AMN+nHR6z6Ntl 4P7WpTq4vgiQ+q7nTpKKKg+icCz/nUUQ0QgqzRWV/eFHHZmolGYuNElbbIIgl4na4M6kcqRZQzX PSTs57BiCtHfLLBRagVa64OdxTiVYea7s6+mICCIQFoYR5/IS749+8rmq+bN/rC3mkAOFbSdZDf GpqoPli0urOiPMXM2ww== X-Proofpoint-GUID: Ez0jgg3fAyKD_3W0_aVya9WxHto3UTBS X-Authority-Analysis: v=2.4 cv=Wukb99fv c=1 sm=1 tr=0 ts=6a047f69 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=MM9pdrEQ6VUtxjYSux8A:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130141 Add device tree bindings for the Display clock controller on the Qualcomm Shikra SoC. Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,shikra-dispcc.yaml | 62 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,shikra-dispcc.h | 39 ++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..38302eda7942ebc2e4dfecae511= b75cba0b09916 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-dispcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Display Clock & Reset Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Display clock control module provides the clocks, resets and power + domains on Qualcomm Shikra SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-dispcc.h + +properties: + compatible: + enum: + - qcom,shikra-dispcc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: GPLL0 DISP DIV clock from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@5f00000 { + compatible =3D "qcom,shikra-dispcc"; + reg =3D <0x05f00000 0x20000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,shikra-dispcc.h b/include/dt-bi= ndings/clock/qcom,shikra-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..088a7c692ad5d2bae38d2799ec1= fc6e8ebbe6c0f --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-dispcc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIKRA_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_ESC0_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 +#define DISP_CC_MDSS_MDP_CLK 9 +#define DISP_CC_MDSS_MDP_CLK_SRC 10 +#define DISP_CC_MDSS_MDP_LUT_CLK 11 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 +#define DISP_CC_MDSS_PCLK0_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 +#define DISP_CC_MDSS_VSYNC_CLK 15 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 16 +#define DISP_CC_SLEEP_CLK 17 +#define DISP_CC_SLEEP_CLK_SRC 18 +#define DISP_CC_XO_CLK 19 +#define DISP_CC_XO_CLK_SRC 20 + +/* DISP_CC power domains */ +#define DISP_CC_MDSS_CORE_GDSC 0 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +#endif --=20 2.34.1 From nobody Fri Jun 12 17:25:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C3D3126C0 for ; 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Wed, 13 May 2026 06:41:01 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368b00d2131sm4317403a91.1.2026.05.13.06.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 06:41:00 -0700 (PDT) From: Imran Shaik Date: Wed, 13 May 2026 19:10:37 +0530 Subject: [PATCH 2/4] dt-bindings: clock: qcom: Add Shikra GPU clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-shikra-dispcc-gpucc-v1-2-5fd673146ab2@oss.qualcomm.com> References: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> In-Reply-To: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE0MSBTYWx0ZWRfX/ZPpxYejU1Mp XpaKv1jymM7ds59oRWDB8goYFdeO9ZcIikmi080NaMoUidBYKLygP5uAo0yK9vRjPxR6Qi3PCQH W65Ovc7sWh5d6tsuOSHLMYdyraHassPGIlZplCrXt0Sh5aBv+eN+/evW6/NRGTj1yCif47+Npkl z0hdUyv3JxnC8u9sBiX7KU6ti+GRSAP23hQRGr1JZNOxRTfFWnLS5+wMe0B49pY8AIk05kdXXxJ 3LKrqK6oEWOzEerzXWhNStQe0Kq1C/BkDWC73DDkT+LwutYujPy98ZezQ5IXyHRv3lLaUyoCGYR SgELPCONjyQ9HYJlysTOEwKncFuiGcdISRAdnuwUzR8nXpI3kYWvKncmAm9qGIT8lkG58PuFnd8 zShLkXED8NTeECrIVcGTZMmLBVlfVWN+NXgXisuDX9uP7HGP/V4nWh2w/vL1CsSdARtLPjn6TpN W5SjqfKvvJkRUSVDtOw== X-Proofpoint-ORIG-GUID: PzwPsp6tFOZ_Exvlhgo1AXJsr0vC7h9Z X-Authority-Analysis: v=2.4 cv=TJZ1jVla c=1 sm=1 tr=0 ts=6a047f6e cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=lM1BZXIhDmX_0k9ByEcA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: PzwPsp6tFOZ_Exvlhgo1AXJsr0vC7h9Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130141 Add device tree bindings for the GPU clock controller on the Qualcomm Shikra SoC. Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 6 +++- include/dt-bindings/clock/qcom,shikra-gpucc.h | 37 ++++++++++++++++++= ++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml index 104ba10ca5737ee1ed94fcb2df5a38bda9c86d14..5f0f94074e43034c2241283241e= 10551ae90ee24 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -7,17 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Graphics Clock & Reset Controller on SM6115 =20 maintainers: + - Imran Shaik - Konrad Dybcio =20 description: | Qualcomm graphics clock control module provides clocks, resets and power domains on Qualcomm SoCs. =20 - See also: include/dt-bindings/clock/qcom,sm6115-gpucc.h + See also: + include/dt-bindings/clock/qcom,shikra-gpucc.h + include/dt-bindings/clock/qcom,sm6115-gpucc.h =20 properties: compatible: enum: + - qcom,shikra-gpucc - qcom,sm6115-gpucc =20 clocks: diff --git a/include/dt-bindings/clock/qcom,shikra-gpucc.h b/include/dt-bin= dings/clock/qcom,shikra-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..60714f6cc6cd2c37a0a4caba447= 3259756bb9d31 --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-gpucc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIKRA_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_AHB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GPU_SMMU_VOTE_CLK 10 +#define GPU_CC_GX_CXO_CLK 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CX_BCR 0 +#define GPU_CC_GFX3D_AON_BCR 1 +#define GPU_CC_GMU_BCR 2 +#define GPU_CC_GX_BCR 3 +#define GPU_CC_XO_BCR 4 + +#endif --=20 2.34.1 From nobody Fri Jun 12 17:25:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE873315793 for ; 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Wed, 13 May 2026 06:41:06 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368b00d2131sm4317403a91.1.2026.05.13.06.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 06:41:05 -0700 (PDT) From: Imran Shaik Date: Wed, 13 May 2026 19:10:38 +0530 Subject: [PATCH 3/4] clk: qcom: Add support for Display Clock Controller on Shikra Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-shikra-dispcc-gpucc-v1-3-5fd673146ab2@oss.qualcomm.com> References: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> In-Reply-To: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-GUID: 44vkVKwG7K-1deFGWt8vXRafkSOe4DKx X-Proofpoint-ORIG-GUID: 44vkVKwG7K-1deFGWt8vXRafkSOe4DKx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE0MSBTYWx0ZWRfX3d70LYx8mL5G OQpUd9jJqd2OnoGDFQnaL+UOXYYQ1tfqPGfodSGNOIr+BcEzYlUzLY1C8mB++v865WWSRV6j9iW BJb7Hlj2SAFgz35gyJdklbS8QE3XRkW0onaf9DeIU+CW9ASXC8G2Qbh/gmS5tPrs/5fn8VP0Eny kTCv2T3GO/4E1mQ7o/5lOOzNGiHO/pxpy5dsSAag1ioOwyLJgXvYOATR+fGLfRahcYpD39mJb/0 wzVmcscZdugmijyaez+AJp/J0nQv3+Walw70pYUK6qwGeqC5ROmpHL6Dd8HgfOHQ2nFDaBsLaUG VKZKg/FjjOrO1JERxw+0tOD9dkY9ybsb+uPCCO5zXHzarbJGCQrUZ9IHIz4j8cuQeiUvOIC7Gt0 7cAhSOSQBgCO4JafvQiRfqBaKZMPV6SiphGowg7JxtEBDptealE9EgH5OsCcRf/TB0+o8zYT9Ga bhZ81KJFYtrG57IJwpA== X-Authority-Analysis: v=2.4 cv=Iu0utr/g c=1 sm=1 tr=0 ts=6a047f74 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=nbHMLpFYyCUxKBpsziUA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130141 Add a driver for the Display clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-shikra.c | 565 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 576 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6e0549fccf3eee358ef747a34e698a6a47a02001..78efe494aaeaeefa9da917c4796= 0cfec18259af7 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -155,6 +155,16 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. =20 +config CLK_SHIKRA_DISPCC + tristate "Shikra Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + default m if ARCH_QCOM + help + Support for the display clock controller on Qualcomm Shikra SoCs. + Say Y if you want to support display devices and functionality such as + splash screen. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 08a2cf68cb9cb81f05a903cfaf2deda8f8cba43e..ec4e79614348a23089454b5a20c= 3dc0abbaa0350 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o +obj-$(CONFIG_CLK_SHIKRA_DISPCC) +=3D dispcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/dispcc-shikra.c b/drivers/clk/qcom/dispcc-shi= kra.c new file mode 100644 index 0000000000000000000000000000000000000000..8fd303ddac0690d3e003057ec6e= d91d104427c9f --- /dev/null +++ b/drivers/clk/qcom/dispcc-shikra.c @@ -0,0 +1,565 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_GPLL0, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 768.0 MHz Configuration */ +static const struct alpha_pll_config disp_cc_pll0_config =3D { + .l =3D 0x28, + .alpha =3D 0x0, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi1_val =3D 0x1, +}; + +static struct clk_alpha_pll disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &disp_cc_pll0_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &disp_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0 }, +}; + +static const struct parent_map disp_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map disp_cc_parent_map_5[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x2154, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_2, + .freq_tbl =3D ftbl_disp_cc_mdss_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x20a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x20c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_0, + .freq_tbl =3D ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x2074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_3, + .freq_tbl =3D ftbl_disp_cc_mdss_mdp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x205c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_4, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_4), + .flags =3D CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x208c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] =3D { + F(32764, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x6050, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_5, + .freq_tbl =3D ftbl_disp_cc_sleep_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x6034, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_parent_map_1, + .freq_tbl =3D ftbl_disp_cc_mdss_esc0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_xo_clk_src", + .parent_data =3D disp_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x20bc, + .shift =3D 0, + .width =3D 2, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x2044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x201c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x2020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x2024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x2008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x2010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x2010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0x4004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x2004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x2018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x3000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_shikra_clocks[] =3D { + [DISP_CC_MDSS_AHB_CLK] =3D &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] =3D &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] =3D &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK] =3D &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] =3D &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] =3D &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] =3D &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] =3D &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] =3D &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_VSYNC_CLK] =3D &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] =3D &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK_SRC] =3D &disp_cc_sleep_clk_src.clkr, + [DISP_CC_XO_CLK_SRC] =3D &disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_shikra_gdscs[] =3D { + [DISP_CC_MDSS_CORE_GDSC] =3D &disp_cc_mdss_core_gdsc, +}; + +static const struct qcom_reset_map disp_cc_shikra_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x2000 }, + [DISP_CC_MDSS_RSCC_BCR] =3D { 0x4000 }, +}; + +static struct clk_alpha_pll *disp_cc_shikra_plls[] =3D { + &disp_cc_pll0, +}; + +static const u32 disp_cc_shikra_critical_cbcrs[] =3D { + 0x6068, /* DISP_CC_SLEEP_CLK */ + 0x604c, /* DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_shikra_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data disp_cc_shikra_driver_data =3D { + .alpha_plls =3D disp_cc_shikra_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_shikra_plls), + .clk_cbcrs =3D disp_cc_shikra_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_shikra_critical_cbcrs), +}; + +static const struct qcom_cc_desc disp_cc_shikra_desc =3D { + .config =3D &disp_cc_shikra_regmap_config, + .clks =3D disp_cc_shikra_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_shikra_clocks), + .resets =3D disp_cc_shikra_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_shikra_resets), + .gdscs =3D disp_cc_shikra_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_shikra_gdscs), + .driver_data =3D &disp_cc_shikra_driver_data, +}; + +static const struct of_device_id disp_cc_shikra_match_table[] =3D { + { .compatible =3D "qcom,shikra-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_shikra_match_table); + +static int disp_cc_shikra_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_shikra_desc); +} + +static struct platform_driver disp_cc_shikra_driver =3D { + .probe =3D disp_cc_shikra_probe, + .driver =3D { + .name =3D "dispcc-shikra", + .of_match_table =3D disp_cc_shikra_match_table, + }, +}; + +module_platform_driver(disp_cc_shikra_driver); + +MODULE_DESCRIPTION("QTI DISPCC Shikra Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Jun 12 17:25:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84D702DECC6 for ; Wed, 13 May 2026 13:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 13 May 2026 06:41:12 -0700 (PDT) X-Received: by 2002:a17:90b:3951:b0:368:6a6e:94dd with SMTP id 98e67ed59e1d1-368f40824a8mr3985799a91.24.1778679671746; Wed, 13 May 2026 06:41:11 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368b00d2131sm4317403a91.1.2026.05.13.06.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 06:41:11 -0700 (PDT) From: Imran Shaik Date: Wed, 13 May 2026 19:10:39 +0530 Subject: [PATCH 4/4] clk: qcom: Add support for GPU Clock Controller on Shikra Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-shikra-dispcc-gpucc-v1-4-5fd673146ab2@oss.qualcomm.com> References: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> In-Reply-To: <20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE0MSBTYWx0ZWRfX6TBC8Qpyy6oG ihJb0LeHYJmdC19/pV0uCDx2cqkWIY2+7g9yQYbm9KuMXxXQ7LgundQ3NWTZUnDtdWY02Bq+NgT UHJbUqCOsD5EJ6cJkmjveY/syALfw/KdBQ3S0nmf4a0gO+rTaC2ThuTETc1o9ijYOZDXrNaRhSk TMF8vSy/dHm8saXTy6xxnwEReOzO6rKxHhBZtx70aLMUY0/PMBpFF/mX0/0ti1FQHZ0zmiRIhcY CX8RLbILUvuxknJZ5YiX3A/nm6FC9YRWESP48+A20ZlRpHN51AAYdugPsAA/8dsC/2/dKFZ2tOS gdzqDSBYgQuCB19/1upVlJgSlfLmW6+xCasgYROUeJ3kL9X8Go9/UAB3Aive2Fi8iakkCNsFADx UmdFwawzR4AQXirz5IQmCmNUxM064m0s5D695luwa9PsUDHsNAG/K51nbLnIEIlaIyYcxyV+nQQ Hb5XoF0t5ptsumJfqRg== X-Authority-Analysis: v=2.4 cv=XqXK/1F9 c=1 sm=1 tr=0 ts=6a047f79 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=Sldbi_rnNfayo5p1r4wA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: IdhQK1s97JOhXm9yf-LAHtclO8s2jobv X-Proofpoint-GUID: IdhQK1s97JOhXm9yf-LAHtclO8s2jobv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130141 Add a driver for the GPU clock controller on Qualcomm Shikra SoC. Signed-off-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-shikra.c | 406 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 417 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 78efe494aaeaeefa9da917c47960cfec18259af7..a12cef1c4540078575e4baa2395= c0d058303a8eb 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -175,6 +175,16 @@ config CLK_SHIKRA_GCC Say Y if you want to use multimedia devices or peripheral devices such as Camera, Video, UART, SPI, I2C, USB, SD/eMMC etc. =20 +config CLK_SHIKRA_GPUCC + tristate "Shikra Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + default m if ARCH_QCOM + help + Support for the graphics clock controller on Qualcomm Shikra SoCs. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ec4e79614348a23089454b5a20c3dc0abbaa0350..12eaa5b02e45c20392d9494a568= 1f45d0deb43dd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o n= wgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_SHIKRA_DISPCC) +=3D dispcc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o +obj-$(CONFIG_CLK_SHIKRA_GPUCC) +=3D gpucc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/gpucc-shikra.c b/drivers/clk/qcom/gpucc-shikr= a.c new file mode 100644 index 0000000000000000000000000000000000000000..1ff61a51cbad10602c3f1a6fa18= ca03acd394e31 --- /dev/null +++ b/drivers/clk/qcom/gpucc-shikra.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_AUX, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco huayra_vco[] =3D { + { 600000000, 3300000000, 0 }, + { 600000000, 2200000000, 1 }, +}; + +/* 710.4 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x0, + .config_ctl_val =3D 0x200d4828, + .config_ctl_hi_val =3D 0x6, + .config_ctl_hi1_val =3D 0x00000000, + .test_ctl_val =3D 0x1c000000, + .test_ctl_hi_val =3D 0x00004000, + .test_ctl_hi1_val =3D 0x00000000, + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D huayra_vco, + .num_vco =3D ARRAY_SIZE(huayra_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL0_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x1120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] =3D { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1142400000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src =3D { + .cmd_rcgr =3D 0x101c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gx_gfx3d_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gfx3d_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x107c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x107c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_crc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk =3D { + .halt_reg =3D 0x10a4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_slv_clk =3D { + .halt_reg =3D 0x10a8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gfx3d_slv_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x1098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x108c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x109c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x5000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x5000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { + .halt_reg =3D 0x1054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gfx3d_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x1090, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x106c, + .gds_hw_ctrl =3D 0x1540, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gpu_cc_gx_gdsc =3D { + .gdscr =3D 0x100c, + .clamp_io_ctrl =3D 0x1508, + .resets =3D (unsigned int []){ GPU_CC_GX_BCR }, + .reset_count =3D 1, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gpu_cc_gx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | SW_RESET | CLAMP_IO | AON_= RESET, +}; + +static struct clk_regmap *gpu_cc_shikra_clocks[] =3D { + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] =3D &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] =3D &gpu_cc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] =3D &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_cc_shikra_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, + [GPU_CC_GX_GDSC] =3D &gpu_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_shikra_resets[] =3D { + [GPU_CC_CX_BCR] =3D { 0x1068 }, + [GPU_CC_GFX3D_AON_BCR] =3D { 0x10a0 }, + [GPU_CC_GMU_BCR] =3D { 0x111c }, + [GPU_CC_GX_BCR] =3D { 0x1008 }, + [GPU_CC_XO_BCR] =3D { 0x1000 }, +}; + +static struct clk_alpha_pll *gpu_cc_shikra_plls[] =3D { + &gpu_cc_pll0, +}; + +static const u32 gpu_cc_shikra_critical_cbcrs[] =3D { + 0x1078, /* GPU_CC_AHB_CLK */ + 0x1004, /* GPU_CC_CXO_AON_CLK */ + 0x1060, /* GPU_CC_GX_CXO_CLK */ +}; + +static const struct regmap_config gpu_cc_shikra_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7008, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data gpu_cc_shikra_driver_data =3D { + .alpha_plls =3D gpu_cc_shikra_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_shikra_plls), + .clk_cbcrs =3D gpu_cc_shikra_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_shikra_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_shikra_desc =3D { + .config =3D &gpu_cc_shikra_regmap_config, + .clks =3D gpu_cc_shikra_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_shikra_clocks), + .resets =3D gpu_cc_shikra_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_shikra_resets), + .gdscs =3D gpu_cc_shikra_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_shikra_gdscs), + .driver_data =3D &gpu_cc_shikra_driver_data, +}; + +static const struct of_device_id gpu_cc_shikra_match_table[] =3D { + { .compatible =3D "qcom,shikra-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_shikra_match_table); + +static int gpu_cc_shikra_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_shikra_desc); +} + +static struct platform_driver gpu_cc_shikra_driver =3D { + .probe =3D gpu_cc_shikra_probe, + .driver =3D { + .name =3D "gpucc-shikra", + .of_match_table =3D gpu_cc_shikra_match_table, + }, +}; + +module_platform_driver(gpu_cc_shikra_driver); + +MODULE_DESCRIPTION("QTI GPUCC Shikra Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1