From nobody Fri Jun 12 17:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E59EB38AC9E; Wed, 13 May 2026 15:29:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778686161; cv=none; b=oB5a+/3AlM0yPEDrmiZziq+HtooD+9IaK8IjhuB06XxU4r6S+qCmBQOqc6D2zszoagJ6mp9Hk2up6/SX5TzgoC9PMEMNY9ZAA8pU9MyCLJCHZLmYeCa3qMdh7GbZOXaVfal+oMVjiSUTARapyN+Hk9MXD9eoLSNLrjJoBL7GUoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778686161; c=relaxed/simple; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WLFZ66s9WuW0GWJaVhnRqaIiAJ1yL5CSzu5KxKb+fEq/VnLgRlQqQi09L6uKPrKu1vNEKJAsV7mpnG27AMz7wJPwc9YUgRBxwg4WWtFMd2HGfkoxA/zeeNT7Mn1alci3yKakrnITuh89NaAkyGQalsXi81tieU5qOkQUQmmlgFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dicXb/O8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dicXb/O8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9F068C2BCB3; Wed, 13 May 2026 15:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778686160; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dicXb/O82yGGS6zbj93Z94FiKpquH7FFlicAUyor0WrW43LaPt3hk94BylNzxPFKC vn8OwJz6UqjggKZkYTU9+0d2t3Php+Sr30aKjB2yo1HNZ/CUd70BNoWP+u2PnXKC90 5DLrWy3IjFHXCjj0yd5XwLO44L7nEep2xh5yzBn1HavC/7aC4NHD3FdGmILlrVsmqY rPnGPbkDIKXeKF5cFf84s4MGzmyCyOQGLDbyKGkJyqB7PcI44EZSeIYmdYn0RP8tAC yuy6IAlxQRCKBNav2YkN073IEgRBbkyBYuDZXaNM2zNGY4bDiGsF6ddnP7t409pGYZ VPjFCLyhzLbrQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E892CD4851; Wed, 13 May 2026 15:29:20 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 13 May 2026 17:29:08 +0200 Subject: [PATCH RESEND v7 1/3] dt-bindings: timer: mips,p8700-gcru Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-riscv-time-mmio-v7-1-f8925ffc226b@htecgroup.com> References: <20260513-riscv-time-mmio-v7-0-f8925ffc226b@htecgroup.com> In-Reply-To: <20260513-riscv-time-mmio-v7-0-f8925ffc226b@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778686158; l=1839; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=qlCmLDBO1Y2Dd5pfYZ/Ggi2QMtMAGxo3h0341eF3VPk=; b=0h3nHTrHH207Q3zMXZYKyjtVJwR0VYMcC2lUhhr8kGDm7/giTXj42PmD5fc4T09AxMkudb15L A1y0fCFJlCPDOeCSi7toDZXw1K2dIA/pK7B0ZdK44onyRLSFgNbHur2 X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add dt-bindings for the GCR.U memory mapped timer device for RISC-V platforms. The GCR.U memory region contains shadow copies of the RISC-V mtime register and the hrtime Global Configuration Register. Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- .../devicetree/bindings/timer/mips,p8700-gcru.yaml | 38 ++++++++++++++++++= ++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml b= /Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3498255762cce6b3f491292d340= d9639bb573e6d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mips,p8700-gcru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GCR.U timer device for the MIPS P8700 platform + +maintainers: + - Aleksa Paunovic + +description: + The GCR.U memory region contains memory mapped shadow copies of + mtime and hrtime Global Configuration Registers, + which software can choose to make accessible from user mode. + +properties: + compatible: + const: mips,p8700-gcru + + reg: + items: + - description: Read-only shadow copy of the RISC-V mtime register. + - description: Read-only shadow copy of the P8700 high resolution ti= mer register. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + timer@1617f000 { + compatible =3D "mips,p8700-gcru"; + reg =3D <0x1617f050 0x8>, + <0x1617f090 0x8>; + }; --=20 2.43.0 From nobody Fri Jun 12 17:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6FB2429831; Wed, 13 May 2026 15:29:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778686161; cv=none; b=qvLUxLI9s2bdumeDHmdKuzsAU32kJWuhppAXnawHdxbJOCs7G5Jh/naP7XcgAkbN5MJCfcbdA25VG3hLDLfx9PkrkpJEV6fJin5Kg17fIrmRj/WlaSBmavTxR5HUxnE+8sV7nbue+U7fo5A9pu5n+zCYPJtVajic5micrOSn05s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778686161; c=relaxed/simple; bh=41IZMqDKuz/6MXeNloPVlflrmSHQD4lgmzdF8Vzr3C4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 13 May 2026 15:29:20 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 13 May 2026 17:29:09 +0200 Subject: [PATCH RESEND v7 2/3] riscv: clocksource: Add readq options to clocksource mmio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-riscv-time-mmio-v7-2-f8925ffc226b@htecgroup.com> References: <20260513-riscv-time-mmio-v7-0-f8925ffc226b@htecgroup.com> In-Reply-To: <20260513-riscv-time-mmio-v7-0-f8925ffc226b@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778686158; l=1888; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=Jv3vpBN1+Uh24vJH4CQZDSOQFXoXTNQJWJ4G2f0Tyms=; b=4kpf+EMPbfGjaxnf9vD+A3laptT18SJFJPnFZcHz0/gp0ClnPrnSu6ztZBVE1qtPrVPDSCWWt HLh7kE+l0TlDLy24QvKcp1en65ukAK/sfikCj/NO6GXMKOD948ksd+w X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add read functions for 64-bit register size to the generic mmio clocksource, covering both up and down counters. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/mmio.c | 14 ++++++++++++++ include/linux/clocksource.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c index 9de75153183124cc8997c6ab61d0c01d9b2637bc..6329d8ce2c0911b5c6de34346b5= ca8de40b93099 100644 --- a/drivers/clocksource/mmio.c +++ b/drivers/clocksource/mmio.c @@ -17,6 +17,20 @@ static inline struct clocksource_mmio *to_mmio_clksrc(st= ruct clocksource *c) return container_of(c, struct clocksource_mmio, clksrc); } =20 +#if defined(readq_relaxed) + +u64 clocksource_mmio_readq_up(struct clocksource *c) +{ + return (u64)readq_relaxed(to_mmio_clksrc(c)->reg); +} + +u64 clocksource_mmio_readq_down(struct clocksource *c) +{ + return ~(u64)readq_relaxed(to_mmio_clksrc(c)->reg) & c->mask; +} + +#endif + u64 clocksource_mmio_readl_up(struct clocksource *c) { return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 65b7c41471c390463770c2da13694e58e83b84ea..df8ea45ec60a28e0276020cb95a= b5328bec89879 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -276,6 +276,10 @@ static inline void clocksource_arch_init(struct clocks= ource *cs) { } =20 extern int timekeeping_notify(struct clocksource *clock); =20 +#if defined(readq_relaxed) +extern u64 clocksource_mmio_readq_up(struct clocksource *c); +extern u64 clocksource_mmio_readq_down(struct clocksource *c); +#endif extern u64 clocksource_mmio_readl_up(struct clocksource *); extern u64 clocksource_mmio_readl_down(struct clocksource *); extern u64 clocksource_mmio_readw_up(struct clocksource *); --=20 2.43.0 From nobody Fri Jun 12 17:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F064279ED; Wed, 13 May 2026 15:29:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778686161; cv=none; b=LcHoS+TIwI18w8T6QVXeoEGLgBMu5L3Qnz9N2ejRxYAPU9i5ktn9qnDPqM27BHhZFDMiKpGK1O1y6sw2jyOIIcosGqo3Tlox1+PwcKVfzmND7nppp65Uyo2MCQ2yhmDBFs3LDav3DrnrNkQK0uBXFQ71Dx42aOACCSVMcYqIt38= ARC-Message-Signature: i=1; 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a=ed25519-sha256; t=1778686158; l=3250; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=6tKjaKViZn8P2amTu2oO3Kpu4d2sX/LUMZ6acjvMpRY=; b=yqFqFT2FlIVTgi2TVjxUCDiuHbeM0zfUfHwtCFK/BVCMLLwbzX6HmPi9VsScWzC1TmZZKh3M1 yIQ6AE1h1zgBSAo5e/Uu/YHaPEOJqniGucbSIFilTsV15hi6KHCnTOm X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a clocksource driver for the P8700 GCRU. Initialization uses helper functions provided by clocksource/mmio.c and timer-of.c. Since the GCRU does not support any kind of interrupts, the default RISC-V clockevent implementation should suffice. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/Kconfig | 9 ++++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-p8700.c | 45 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 55 insertions(+) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ffcd23668763fe7707a4e917bf240caadbb09a8c..861e7b8c93376b345e3a488dabe= 435d06a42f357 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -672,6 +672,15 @@ config CLINT_TIMER This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. =20 +config P8700_TIMER + bool "MIPS P8700 timer driver" + depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI + select CLKSRC_MMIO + select TIMER_PROBE + select TIMER_OF + help + Enables support for MIPS P8700 timer driver. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ec4452ee958f1a814c708aeba6412bea61d24892..fae9a58d6c8663a7c857b9ab7fd= ae05782b3551c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -95,3 +95,4 @@ obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) +=3D timer-loongson1-p= wm.o obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o obj-$(CONFIG_RALINK_TIMER) +=3D timer-ralink.o obj-$(CONFIG_NXP_STM_TIMER) +=3D timer-nxp-stm.o +obj-$(CONFIG_P8700_TIMER) +=3D timer-p8700.o diff --git a/drivers/clocksource/timer-p8700.c b/drivers/clocksource/timer-= p8700.c new file mode 100644 index 0000000000000000000000000000000000000000..220ed8efdfe5544a3f925ad43b8= faf2e0565557b --- /dev/null +++ b/drivers/clocksource/timer-p8700.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +static struct timer_of gcru_of =3D { .flags =3D TIMER_OF_BASE }; +static u64 __iomem *p8700_time_val __ro_after_init; + +static u64 notrace p8700_timer_sched_read(void) +{ + return (u64)readq_relaxed(p8700_time_val); +} + +static int __init p8700_timer_init(struct device_node *node) +{ + int error =3D 0; + + error =3D timer_of_init(node, &gcru_of); + if (error) + return error; + + p8700_time_val =3D timer_of_base(&gcru_of); + /* Now init the mmio timer with the address we got from DT */ + error =3D clocksource_mmio_init(p8700_time_val, "mips,p8700-gcru", + riscv_timebase, 450, 64, + clocksource_mmio_readq_up); + if (error) + return error; + + /* Sched clock */ + sched_clock_register(p8700_timer_sched_read, 64, riscv_timebase); + + return error; +} + +TIMER_OF_DECLARE(p8700_timer, "mips,p8700-gcru", p8700_timer_init); --=20 2.43.0