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Add a check to avoid configuring UBWC during sys init on unsupported platforms. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c b/driv= ers/media/platform/qcom/iris/iris_hfi_gen2_packet.c index 0d05dd2afc07..6e04175eb904 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c @@ -140,6 +140,9 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *co= re, struct iris_hfi_heade &payload, sizeof(u32)); =20 + if (!ubwc->ubwc_enc_version) + return; + payload =3D qcom_ubwc_macrotile_mode(ubwc) ? 8 : 4; iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_MAX_CHANNELS, --=20 2.47.3 From nobody Fri Jun 12 17:16:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54054426688 for ; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-393f5f5f15asm41106841fa.17.2026.05.13.05.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 05:49:11 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 13 May 2026 15:45:36 +0300 Subject: [PATCH v2 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-iris-ar50lt-v2-2-411e5f7bdc4c@oss.qualcomm.com> References: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> In-Reply-To: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4536; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=X3Z4HL3UZoUysuTz1/xwzlwJPOeZfHAr2V3R4DT1iDI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqBHM/rOGpk62mEvyYzTUSmmxa/tsYrrnZZDEdj mwZJD3UNf+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCagRzPwAKCRCLPIo+Aiko 1VbHB/4xgL+o0pFRVbWcQXFvIz4kiCzjS4V8GF2MG7OYQh+tfpdavVF7ltbdflw8Anmibz4W8WC afIDGpQxjQEfObIchp/9AHvFj2yz/OMQqMx6lqX71hMDKCrUoYMXaafljvSP1lGfyhveQcNEYi/ yTTevfEug7tIiUQoQRE22t39rY8FzUxZZzwo6rWqneSxeHsE1MA+LkY7KaFsRMKFvAlyGnhCkM9 XROtUNNR0vZySlB+1U7gVdEQReqQ0dAzig2KqQOya90O2UQlLssTvfDgk/WQNgF1bf0k6VkDBqy gR1ytxMXjY4vO4luIUXpyacIdZqJjQtPP/aCuN27EM7ZVPNm X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDEzMiBTYWx0ZWRfX1f1fuGtgaIWp W5GKG+Hmh1jZKbvPQrTiXerJbBw37uhJXV4jYGyhtUA+ikzAvS0gWfndQPg2vijsQQ4vtTzVp1M zYbY9zAu2QaKHPotQOGQkM9Iffoq79AyYc+4hHqgo2Ukdg0vUm0fTzF1GAe4Js+ySJLEy/NIQdJ eiHXOeTQJ/taIkw1GJs3qtc2lY+CuykTRRFLtPxSlyH7RoztD001zX9PGyQ1KeuACZAsx5cxnFr aiSDGuFfG0MptOw1qogp+8RypBhWBchiAu3/bAcfUZgJERMqPb49+RA2mfeNxkwj6uZYut5FEeQ 5pYMoWKFHk+nqgX++6UIa2bsnh2kS6ZQWo3sTommYmWLgqEyKSJUMbDh8ocxRL/hnezUXJ3uENR 655dJJiY+mQqxocEMt64yJxZFUFUYhzxV6vq4Ki4PPRC/hrc3pCVxe4G81nzIoS1iUKvQ/Nq/LE uqrYZHek1qWWOOGYNzA== X-Proofpoint-ORIG-GUID: mJLTQKN9MRGplWh-YlmvwlotndKJW_s- X-Authority-Analysis: v=2.4 cv=TJZ1jVla c=1 sm=1 tr=0 ts=6a047349 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=HWmRtQhKy1KQUjwlQEkA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: mJLTQKN9MRGplWh-YlmvwlotndKJW_s- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130132 From: Dikshita Agarwal The raw formats supported by Iris were previously advertised unconditionally, assuming UBWC support on all platforms. However, some platforms do not support UBWC which results in incorrect format capability exposure. Use the UBWC configuration provided by the platform to dynamically filter raw formats at runtime. If UBWC is not supported, UBWC-based formats are omitted from the advertised capability list, while linear formats remain available. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_vdec.c | 9 +++++++++ drivers/media/platform/qcom/iris/iris_venc.c | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index ff8d664558af..bd44e6437480 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -3,6 +3,7 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include #include #include =20 @@ -74,6 +75,7 @@ static const u32 iris_vdec_formats_cap[] =3D { =20 static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; unsigned int size, i; const u32 *fmt; =20 @@ -85,6 +87,9 @@ static bool check_format(struct iris_inst *inst, u32 pixf= mt, u32 type) case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: fmt =3D iris_vdec_formats_cap; size =3D ARRAY_SIZE(iris_vdec_formats_cap); + /* Last format is UBWC; drop it if UBWC is unsupported */ + if (!ubwc->ubwc_enc_version) + size--; break; default: return false; @@ -100,6 +105,7 @@ static bool check_format(struct iris_inst *inst, u32 pi= xfmt, u32 type) =20 static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 typ= e) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; unsigned int size; const u32 *fmt; =20 @@ -111,6 +117,9 @@ static u32 find_format_by_index(struct iris_inst *inst,= u32 index, u32 type) case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: fmt =3D iris_vdec_formats_cap; size =3D ARRAY_SIZE(iris_vdec_formats_cap); + /* Last format is UBWC; drop it if UBWC is unsupported */ + if (!ubwc->ubwc_enc_version) + size--; break; default: return 0; diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 2398992d0596..c41f4103ccc3 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -3,6 +3,7 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-393f5f5f15asm41106841fa.17.2026.05.13.05.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 05:49:12 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 13 May 2026 15:45:37 +0300 Subject: [PATCH v2 03/16] media: iris: Introduce set_preset_register as a vpu_op Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-iris-ar50lt-v2-3-411e5f7bdc4c@oss.qualcomm.com> References: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> In-Reply-To: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4447; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=yjv3YSjey6H8VPHigK1PHGPXENr2QgLaW8YDZ/WLE3w=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQxZLscP0l1MVnT4xK1wp0pdlXa59nnfC7acZl0q8c46eZ JJkcwjrZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBE1hpzMEwMfv/eYHtzd+CW Jf3Jzplib7v23XsaIDP19yUZFh+xPLf7pb99GL/rtAsF7pddkrjq7Of4z61rFeM4a+43z/329+u huqhfYayCE1wOetnGXC6rvTU9csbeG3qqIV3b2oIKk91KYq4scpt2q+9bSU2vYFbCnNOTMplUZv M8O2rV0KpySFrzb3ST4V3vA91JnF1uIRwuNU78Wcw8s66mXpJboWO+4DmX8XNtcaYLPyVCP089K 1Cqtf3EnWCTVfqrWn09zouXhkq9fiRXIabefOuqg7Zt/pm9jmVvrnQdENro/urM93fhHg+4q37d eGazls+pdsqWi7wlQfN7vd884kg6YCU6uXqBALNipdVqAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=M/l97Sws c=1 sm=1 tr=0 ts=6a04734b cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=4Uh0hlRDs2lXuULb_e4A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDEzMiBTYWx0ZWRfX9vP2RuSc0ea8 cmGrsK3Mv5YY8PxlyzsvkNCCZZjpXA91f/b0sRzUvFH/Ajdfl5rozUIavPv+lMW1p3UBOJJ+pt+ 8Lb7MjcoFz4wXMIzdvPh6SptBohBrLg183iy0IuIte3OXhDIBgXb4yx4Gy+c7LCBbkRseXx71bK q5gPA/9Ak/Ue9IJyaUuHrxiCOjFPmHAV3yeB4F04kv4hxIc7xcrBxkaKsgWGaTx2rix6u0b8ZEw ohO0s+1tRhb3VWW5L6rBT/maAsb5NQnQVP/R6EPRFsMtaPolQxubAmO/eErLQrP49fVEyq1lptq FK/sl4kyU6taKA3wU1dGVGucl7tG6CNtsQ4ifVnZfNXoKQVyDVMJdANuH/53IpbAuAz09A5M4bz MYUwl4Z5baTkcnwcIBADQfpDZbb/z29U0h0JujIpNm0Y2xZG9ieoN1Uwk11xHgypV86RD4hBMOY 2nOME/Nf8DZHQi/KSOw== X-Proofpoint-ORIG-GUID: 4RwaujtrOEOlo05SVFbfznEhuHNY2bfy X-Proofpoint-GUID: 4RwaujtrOEOlo05SVFbfznEhuHNY2bfy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130132 From: Dikshita Agarwal The set_preset_registers sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move set_preset_register into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++ drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 5 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 01ef40f38957..d61902c9a213 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -45,4 +45,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu2_calc_freq, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 3dad47be78b5..dc02ced1b931 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -261,6 +261,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -270,6 +271,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -280,4 +282,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index 02e100a4045f..f608a297d4a3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -368,4 +368,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu4x_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 7bba3b6209c2..ff0070c85ccf 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -472,7 +472,7 @@ int iris_vpu_power_on(struct iris_core *core) =20 iris_opp_set_rate(core->dev, freq); =20 - iris_vpu_set_preset_registers(core); + core->iris_platform_data->vpu_ops->set_preset_registers(core); =20 iris_vpu_interrupt_init(core); core->intr_status =3D 0; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 09799a375c14..21ed4c9bd5e3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -22,6 +22,7 @@ struct vpu_ops { void (*program_bootup_registers)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); int (*set_hwmode)(struct iris_core *core); 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Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move interrupt_init into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++ drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 5 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index d61902c9a213..d49d22b14753 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -46,4 +46,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .calc_freq =3D iris_vpu2_calc_freq, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index dc02ced1b931..c3b760730c98 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -262,6 +262,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -272,6 +273,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -283,4 +285,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index f608a297d4a3..90ccdc0d2a07 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -369,4 +369,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu4x_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index ff0070c85ccf..59e4d68d042f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -31,7 +31,7 @@ #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) =20 -static void iris_vpu_interrupt_init(struct iris_core *core) +void iris_vpu_interrupt_init(struct iris_core *core) { u32 mask_val; =20 @@ -474,7 +474,7 @@ int iris_vpu_power_on(struct iris_core *core) =20 core->iris_platform_data->vpu_ops->set_preset_registers(core); =20 - iris_vpu_interrupt_init(core); + core->iris_platform_data->vpu_ops->interrupt_init(core); core->intr_status =3D 0; enable_irq(core->irq); =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 21ed4c9bd5e3..9151545065cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -23,6 +23,7 @@ struct vpu_ops { u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); 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In preparation of adding support for AR50LT platforms, add an optional disable_arp callback to the VPU ops and invoke it from core init and resume paths. No functional change for existing platforms. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_core.c | 4 ++++ drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 52bf56e517f9..bd22076f3557 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -45,6 +45,7 @@ static int iris_wait_for_system_response(struct iris_core= *core) =20 int iris_core_init(struct iris_core *core) { + const struct vpu_ops *vpu_ops =3D core->iris_platform_data->vpu_ops; int ret; =20 mutex_lock(&core->lock); @@ -78,6 +79,9 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_unload_fw; =20 + if (vpu_ops->disable_arp) + vpu_ops->disable_arp(core); + core->iris_firmware_data->init_hfi_ops(core); =20 ret =3D iris_hfi_core_init(core); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.c index 8769ec61f117..8f04f3793d9a 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -144,6 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) =20 int iris_hfi_pm_resume(struct iris_core *core) { + const struct vpu_ops *vpu_ops =3D core->iris_platform_data->vpu_ops; const struct iris_hfi_sys_ops *ops =3D core->hfi_sys_ops; int ret; =20 @@ -163,6 +164,9 @@ int iris_hfi_pm_resume(struct iris_core *core) if (ret) goto err_suspend_hw; =20 + if (vpu_ops->disable_arp) + vpu_ops->disable_arp(core); + ret =3D ops->sys_interframe_powercollapse(core); if (ret) goto err_suspend_hw; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 9151545065cd..71d96921ed37 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -24,6 +24,7 @@ struct vpu_ops { int (*set_hwmode)(struct iris_core *core); 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In preparation for adding AR50LT support in subsequent patches, introduce a platform data field, wd_intr_mask, to capture the watchdog interrupt bitmask per platform. Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++ drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 6 ++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++--- drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 - 5 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 7acb073f7197..51d8faf6fd1a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -283,6 +283,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + u32 wd_intr_mask; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index 961dce2e6aa9..eeef453c583f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -16,6 +16,8 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" =20 +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc =3D { .firmware_data =3D &iris_hfi_gen1_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -94,6 +96,7 @@ const struct iris_platform_data sc7280_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 1, .no_aon =3D true, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ @@ -124,6 +127,7 @@ const struct iris_platform_data sm8250_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu2, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 9a76149f37b7..5fbaff5c01ca 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -17,6 +17,8 @@ #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" =20 +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc =3D { .firmware_data =3D &iris_hfi_gen2_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -106,6 +108,7 @@ const struct iris_platform_data qcs8300_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 2, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), @@ -135,6 +138,7 @@ const struct iris_platform_data sm8550_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -172,6 +176,7 @@ const struct iris_platform_data sm8650_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -201,6 +206,7 @@ const struct iris_platform_data sm8750_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 59e4d68d042f..b8300195a43b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core) =20 void iris_vpu_clear_interrupt(struct iris_core *core) { + u32 wd_intr_mask =3D core->iris_platform_data->wd_intr_mask; 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This requirement is due to QSB (Qualcomm System Bus) 128b to QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT which is not needed for other IRIS cores. In preparation of adding support for AR50LT core, introduce platform-configurable IB multiplier and enable IB voting for all SoCs. Existing platforms default to IB =3D=3D AB, while AR50LT requires 2x peak bandwidth. Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 ++ drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 4 ++++ drivers/media/platform/qcom/iris/iris_resources.c | 2 ++ 4 files changed, 9 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 51d8faf6fd1a..e1dc226066c1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -284,6 +284,7 @@ struct iris_platform_data { u32 num_vpp_pipe; bool no_aon; u32 wd_intr_mask; + u32 icc_ib_multiplier; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index eeef453c583f..e2fddc29abc7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -97,6 +97,7 @@ const struct iris_platform_data sc7280_data =3D { .num_vpp_pipe =3D 1, .no_aon =3D true, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ @@ -128,6 +129,7 @@ const struct iris_platform_data sm8250_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 5fbaff5c01ca..8c1c8b19fa99 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -109,6 +109,7 @@ const struct iris_platform_data qcs8300_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 2, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), @@ -139,6 +140,7 @@ const struct iris_platform_data sm8550_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -177,6 +179,7 @@ const struct iris_platform_data sm8650_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -207,6 +210,7 @@ const struct iris_platform_data sm8750_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 773f6548370a..caeaf199cef7 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -18,6 +18,7 @@ =20 int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw) { + u32 icc_ib_multiplier =3D core->iris_platform_data->icc_ib_multiplier; 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Tables for AR50LT won't have corresponding entry in the capability tables. Let iris_set_pipe() silently skip propgramming the property if there is no corresponding capability. Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_ctrls.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index ef7adac3764d..f438dddc19ba 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -450,6 +450,9 @@ int iris_set_pipe(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_id) u32 work_route =3D inst->fw_caps[PIPE].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 + if (!hfi_id) + return 0; + return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, iris_get_port_info(inst, cap_id), --=20 2.47.3 From nobody Fri Jun 12 17:16:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A39247A0A1 for ; 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Add register handling for ar50lt by hooking up vpu op with ar50lt specific implemtation or resue from earlier generation wherever feasible. Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 + drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 156 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 3 +- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 5 files changed, 162 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 48e415cbc439..f1b204b95694 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -26,6 +26,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_vpu2.o \ iris_vpu3x.o \ iris_vpu4x.o \ + iris_vpu_ar50lt.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index e1dc226066c1..4a0895bf5720 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -63,6 +63,7 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_THROTTLE_CLK, }; =20 struct platform_clk_data { @@ -283,6 +284,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + bool no_rpmh; u32 wd_intr_mask; u32 icc_ib_multiplier; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_ar50lt.c new file mode 100644 index 000000000000..1af20b067c03 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" + +#include "iris_vpu_register_defines.h" + +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3) + +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080 + +#define CPU_CS_VCICMD 0xa0020 +#define CPU_CS_VCICMD_ARP_OFF 0x1 + +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT); +} + +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core) +{ + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_= INTR_MASK); +} + +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core) +{ + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD); +} + +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core) +{ + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return 0; +} + +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core) +{ + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); +} + +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_ctrl_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_AHB_CLK); + if (ret) + goto err_disable_axi_clock; + + return 0; + +err_disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +err_disable_ctrl_clock: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return ret; +} + +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + if (ret) + goto err_disable_hw_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK); + if (ret) + goto err_disable_hw_ahb_clock; + + return 0; + +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static u64 iris_vpu_ar50lt_calc_freq(struct iris_inst *inst, size_t data_s= ize) +{ + struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; + struct v4l2_format *inp_f =3D inst->fmt_src; + u32 mbs_per_second, mbpf, height, width; + unsigned long vpp_freq, vsp_freq; + u32 fps =3D DEFAULT_FPS; + + width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); + height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); + + mbpf =3D NUM_MBS_PER_FRAME(height, width); + mbs_per_second =3D mbpf * fps; + + vpp_freq =3D mbs_per_second * caps->mb_cycles_vpp; + + /* 21 / 20 is overhead factor */ + vpp_freq +=3D vpp_freq / 20; + vsp_freq =3D mbs_per_second * caps->mb_cycles_vsp; + + /* 10 / 7 is overhead factor */ + vsp_freq +=3D ((fps * data_size * 8) * 10) / 7; + + return max(vpp_freq, vsp_freq); +} + +const struct vpu_ops iris_vpu_ar50lt_ops =3D { + .power_off_hw =3D iris_vpu_ar50lt_power_off_hw, + .power_on_hw =3D iris_vpu_ar50lt_power_on_hw, + .power_off_controller =3D iris_vpu_ar50lt_power_off_controller, + .power_on_controller =3D iris_vpu_ar50lt_power_on_controller, + .calc_freq =3D iris_vpu_ar50lt_calc_freq, + .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_ar50lt_set_preset_registers, + .interrupt_init =3D iris_vpu_ar50lt_interrupt_init, + .disable_arp =3D iris_vpu_ar50lt_disable_arp, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index b8300195a43b..f3607c0ca847 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core) } =20 writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); - writel(0x0, core->reg_base + CPU_CS_X2RPMH); + if (!core->iris_platform_data->no_rpmh) + writel(0x0, core->reg_base + CPU_CS_X2RPMH); =20 return 0; } diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 71d96921ed37..f00e2de5fa53 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; 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Implement minimal support for querying the properties from the firmware. Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 + .../platform/qcom/iris/iris_hfi_gen1_command.c | 21 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_hfi_gen1_defines.h | 15 +++++++++++++++ .../platform/qcom/iris/iris_hfi_gen1_response.c | 6 ++++++ 4 files changed, 43 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index a27447eb2519..16099f9a25b6 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -121,6 +121,7 @@ struct iris_hfi_session_ops { int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, void *payload, u32 payload_size); + int (*session_get_property)(struct iris_inst *inst, u32 packet_type); int (*session_open)(struct iris_inst *inst); int (*session_start)(struct iris_inst *inst, u32 plane); int (*session_queue_buf)(struct iris_inst *inst, struct iris_buffer *buff= er); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 83373862655f..4e17fa3c602f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1063,10 +1063,31 @@ static int iris_hfi_gen1_session_set_config_params(= struct iris_inst *inst, u32 p return 0; } =20 +static int iris_hfi_gen1_session_get_property(struct iris_inst *inst, u32 = packet_type) +{ + struct hfi_session_get_property_pkt pkt; + int ret; + + pkt.shdr.hdr.size =3D sizeof(pkt); + pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_GET_PROPERTY; + pkt.shdr.session_id =3D inst->session_id; + pkt.num_properties =3D 1; + pkt.data =3D packet_type; + + reinit_completion(&inst->completion); + + ret =3D iris_hfi_queue_cmd_write(inst->core, &pkt, pkt.shdr.hdr.size); + if (ret) + return ret; + + return iris_wait_for_session_response(inst, false); +} + static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops =3D { .session_open =3D iris_hfi_gen1_session_open, .session_set_config_params =3D iris_hfi_gen1_session_set_config_params, .session_set_property =3D iris_hfi_gen1_session_set_property, + .session_get_property =3D iris_hfi_gen1_session_get_property, .session_start =3D iris_hfi_gen1_session_start, .session_queue_buf =3D iris_hfi_gen1_session_queue_buffer, .session_release_buf =3D iris_hfi_gen1_session_unset_buffers, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 42226ccee3d9..1b770e830c58 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -35,6 +35,7 @@ #define HFI_CMD_SESSION_EMPTY_BUFFER 0x211004 #define HFI_CMD_SESSION_FILL_BUFFER 0x211005 #define HFI_CMD_SESSION_FLUSH 0x211008 +#define HFI_CMD_SESSION_GET_PROPERTY 0x211009 #define HFI_CMD_SESSION_RELEASE_BUFFERS 0x21100b #define HFI_CMD_SESSION_RELEASE_RESOURCES 0x21100c #define HFI_CMD_SESSION_CONTINUE 0x21100d @@ -113,6 +114,7 @@ #define HFI_MSG_SESSION_FLUSH 0x221006 #define HFI_MSG_SESSION_EMPTY_BUFFER 0x221007 #define HFI_MSG_SESSION_FILL_BUFFER 0x221008 +#define HFI_MSG_SESSION_PROPERTY_INFO 0x221009 #define HFI_MSG_SESSION_RELEASE_RESOURCES 0x22100a #define HFI_MSG_SESSION_RELEASE_BUFFERS 0x22100c =20 @@ -186,6 +188,12 @@ struct hfi_session_set_property_pkt { u32 data[]; }; =20 +struct hfi_session_get_property_pkt { + struct hfi_session_hdr_pkt shdr; + u32 num_properties; + u32 data; +}; + struct hfi_sys_pc_prep_pkt { struct hfi_pkt_hdr hdr; }; @@ -525,6 +533,13 @@ struct hfi_msg_session_fbd_uncompressed_plane0_pkt { u32 data[]; }; =20 +struct hfi_msg_session_property_info_pkt { + struct hfi_session_hdr_pkt shdr; + u32 num_properties; + u32 property; + u8 data[]; +}; + struct hfi_msg_session_release_buffers_done_pkt { struct hfi_msg_session_hdr_pkt shdr; u32 num_buffers; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index bfd7495bf44f..23fc7194b1e3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -591,6 +591,10 @@ static const struct iris_hfi_gen1_response_pkt_info pk= t_infos[] =3D { .pkt =3D HFI_MSG_SESSION_RELEASE_BUFFERS, .pkt_sz =3D sizeof(struct hfi_msg_session_release_buffers_done_pkt), }, + { + .pkt =3D HFI_MSG_SESSION_PROPERTY_INFO, + .pkt_sz =3D sizeof(struct hfi_msg_session_property_info_pkt), + }, }; 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Implement corresponding functionality updating buffers data. This will be used for upcoming support of AR50Lt platforms with Gen1 firmware. Signed-off-by: Dmitry Baryshkov --- .../platform/qcom/iris/iris_hfi_gen1_response.c | 74 ++++++++++++++++++= +++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 23fc7194b1e3..ee996eb1f41f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -533,6 +533,78 @@ static void iris_hfi_gen1_session_ftb_done(struct iris= _inst *inst, void *packet) dev_err(core->dev, "error in ftb done\n"); } =20 +static enum iris_buffer_type iris_hfi_gen1_buf_type(struct iris_inst *inst= , u32 type) +{ + switch (type) { + case HFI_BUFFER_INPUT: + return BUF_INPUT; + case HFI_BUFFER_OUTPUT: + if (iris_split_mode_enabled(inst)) + return BUF_DPB; + return BUF_OUTPUT; + case HFI_BUFFER_OUTPUT2: + if (iris_split_mode_enabled(inst)) + return BUF_OUTPUT; + return BUF_DPB; + case HFI_BUFFER_INTERNAL_PERSIST_1: + return BUF_PERSIST; + case HFI_BUFFER_INTERNAL_SCRATCH: + return BUF_BIN; + case HFI_BUFFER_INTERNAL_SCRATCH_1: + return BUF_SCRATCH_1; + case HFI_BUFFER_INTERNAL_SCRATCH_2: + return BUF_SCRATCH_2; + case HFI_BUFFER_INTERNAL_PERSIST: + return BUF_ARP; + default: + return -EINVAL; + } +} + +static void iris_hfi_gen1_session_buffer_requirements(struct iris_inst *in= st, + void *data, size_t size) +{ + struct hfi_buffer_requirements *req; + + if (!size || size % sizeof(*req)) + return; + + for (req =3D data; size; size -=3D sizeof(*req), req++) { + enum iris_buffer_type type =3D iris_hfi_gen1_buf_type(inst, req->type); + + if (type =3D=3D -EINVAL) + continue; + + inst->buffers[type].min_count =3D req->hold_count; + inst->buffers[type].size =3D req->size; + + if (type =3D=3D BUF_OUTPUT) + inst->fw_min_count =3D req->count_actual; + } +} + +static void iris_hfi_gen1_session_property_info(struct iris_inst *inst, vo= id *packet) +{ + struct hfi_msg_session_property_info_pkt *pkt =3D packet; + + if (!pkt->num_properties) { + dev_err(inst->core->dev, "error, no properties\n"); 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Unlike more recent cores this generation doesn't have the PIPE property (as it always has only one pipe). Also, unlike newer platforms, buffer sizes are requested from the firmware instead of being calculated by the driver. Co-developed-by: Dikshita Agarwal Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 227 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_common.h | 6 + .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 111 ++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 13 ++ drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 + 7 files changed, 363 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index f1b204b95694..bbd1f724963e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -14,6 +14,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_hfi_queue.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ + iris_platform_vpu_ar50lt.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.c index 60f51a1ba941..39e88d5dd6d5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -284,3 +284,230 @@ const struct iris_firmware_data iris_hfi_gen1_data = =3D { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +static const struct platform_inst_fw_cap iris_inst_fw_cap_gen1_ar50lt_dec[= ] =3D { + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_gen1_ar50lt_enc[] =3D= { + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen1, + }, + { + .cap_id =3D BITRATE, + .min =3D BITRATE_MIN, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D BITRATE_STEP, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen1, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D (1 << 16) - 1, + .step_or_mask =3D 1, + .value =3D 30, + .set =3D iris_set_u32 + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen1, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MAX_QP_HEVC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, +}; + +static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_SCRATCH_1, +}; + +const struct iris_firmware_data iris_hfi_gen1_ar50lt_data =3D { + .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, + + .inst_fw_caps_dec =3D iris_inst_fw_cap_gen1_ar50lt_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(iris_inst_fw_cap_gen1_ar50lt_dec), + .inst_fw_caps_enc =3D inst_fw_cap_gen1_ar50lt_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc), + + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_b= uf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 4a0895bf5720..f9763ea51c53 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -29,6 +29,10 @@ struct iris_inst; #define DEFAULT_QP 20 #define BITRATE_DEFAULT 20000000 =20 +#define BITRATE_MAX_AR50LT 100000000 +#define BITRATE_DEFAULT_AR50LT 20000000 +#define MIN_QP_8BIT_AR50LT 0 + enum stage_type { STAGE_1 =3D 1, STAGE_2 =3D 2, @@ -41,8 +45,10 @@ enum pipe_type { }; =20 extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data; extern const struct iris_firmware_data iris_hfi_gen2_data; =20 +extern const struct iris_platform_data qcm2290_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/= drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c new file mode 100644 index 000000000000..76bebe012bd8 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10 + +const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc =3D { + .firmware_data =3D &iris_hfi_gen1_ar50lt_data, + .get_vpu_buffer_size =3D iris_vpu_ar50lt_gen1_buf_size, + .fwname =3D "qcom/venus-6.0/venus.mbn", +}; + +static const u32 iris_fmts_ar50lt_dec[] =3D { + [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, + [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, + [IRIS_FMT_VP9] =3D V4L2_PIX_FMT_VP9, +}; + +static const struct bw_info iris_bw_table_dec_ar50lt[] =3D { + { ((1920 * 1080) / 256) * 60, 1564000, }, + { ((1920 * 1080) / 256) * 30, 791000, }, + { ((1280 * 720) / 256) * 60, 688000, }, + { ((1280 * 720) / 256) * 30, 347000, }, +}; + +static const struct icc_info iris_icc_info_ar50lt[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 6500000 }, +}; + +static const char * const iris_pmdomain_table_ar50lt[] =3D { "venus", "vco= dec0" }; + +static const char * const iris_opp_pd_table_ar50lt[] =3D { "cx" }; + +static const struct platform_clk_data iris_clk_table_ar50lt[] =3D { + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_HW_AHB_CLK, "vcodec0_bus" }, + {IRIS_THROTTLE_CLK, "throttle" }, +}; + +static const char * const iris_opp_clk_table_ar50lt[] =3D { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_ar50lt[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +static struct platform_inst_caps platform_inst_cap_ar50lt =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 1920, + .min_frame_height =3D 128, + .max_frame_height =3D 1920, + .max_mbpf =3D (1920 * 1088) / 256, + .mb_cycles_vpp =3D 440, + .mb_cycles_fw =3D 733003, + .mb_cycles_fw_vpp =3D 225975, + .num_comv =3D 0, + .max_frame_rate =3D 120, + .max_operating_rate =3D 120, +}; + +const struct iris_platform_data qcm2290_data =3D { + .firmware_desc_gen1 =3D &iris_vpu_ar50lt_p1_gen1_s6_desc, + .vpu_ops =3D &iris_vpu_ar50lt_ops, + .icc_tbl =3D iris_icc_info_ar50lt, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_ar50lt), + .bw_tbl_dec =3D iris_bw_table_dec_ar50lt, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_ar50lt), + .pmdomain_tbl =3D iris_pmdomain_table_ar50lt, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_ar50lt), + .opp_pd_tbl =3D iris_opp_pd_table_ar50lt, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_ar50lt), + .clk_tbl =3D iris_clk_table_ar50lt, + .clk_tbl_size =3D ARRAY_SIZE(iris_clk_table_ar50lt), + .opp_clk_tbl =3D iris_opp_clk_table_ar50lt, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .inst_iris_fmts =3D iris_fmts_ar50lt_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_ar50lt_dec), + .inst_caps =3D &platform_inst_cap_ar50lt, + .tz_cp_config_data =3D tz_cp_config_ar50lt, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_ar50lt), + .num_vpp_pipe =3D 1, + .no_rpmh =3D true, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 2, + .max_session_count =3D 8, + .max_core_mbpf =3D ((1920 * 1088) / 256) * 4, + /* Concurrency: 1080p@30 decode + 1080p@30 encode */ + /* Concurrency: 3 * 1080p@30 decode */ + .max_core_mbps =3D (((1920 * 1088) / 256) * 90), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 7211d520eda3..070e09406d89 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -356,6 +356,10 @@ static const struct dev_pm_ops iris_pm_ops =3D { }; =20 static const struct of_device_id iris_dt_match[] =3D { + { + .compatible =3D "qcom,qcm2290-venus", + .data =3D &qcm2290_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 9270422c1601..125fb2d6960d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -2135,6 +2135,19 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum= iris_buffer_type buffer_typ return size; } =20 +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer= _type buffer_type) +{ + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; + int ret; + + /* return 0 on error to let the driver cope */ + ret =3D hfi_ops->session_get_property(inst, HFI_PROPERTY_CONFIG_BUFFER_RE= QUIREMENTS); + if (ret) + return 0; + + return inst->buffers[buffer_type].size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 8c0d6b7b5de8..1d07137c70cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -288,6 +288,7 @@ static inline u32 size_av1d_qp(u32 frame_width, u32 fra= me_height) u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type); u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer= _type buffer_type); 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-393f5f5f15asm41106841fa.17.2026.05.13.05.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 05:49:32 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 13 May 2026 15:45:47 +0300 Subject: [PATCH v2 13/16] media: iris: Introduce buffer size calculations for AR50LT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-iris-ar50lt-v2-13-411e5f7bdc4c@oss.qualcomm.com> References: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> In-Reply-To: <20260513-iris-ar50lt-v2-0-411e5f7bdc4c@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=27281; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=NZM82+SuvWhwak1o8DyX0RlsZmAkYg93fFcjJxyi1Fo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqBHNBECdB+ZT6+fWwDgnReLLYWTapwdDBmKJmQ f9kX/KhWHOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCagRzQQAKCRCLPIo+Aiko 1Wp9CACArWDWQcCz3CKDDOQHqrm/DiYbqoueU6WjJMKCNLRd9BFRTOUx4PFfgBBWE6DqW/bItWa Od8cOq3lfIazwJKeJk1ZLl/1fG475my7ow95gvlsH4Hm6xBSjh7TMHUtnIM7BebZGqZuGTqonXU u6+4zUegT7XxDTCsnKDcJj77NsUQJKndRbSrnxI7Rs3UwwaGQ9WKzM0nRTgB2kqaPVJ/9h8XAmz TtdIrnDMhPmMgbx/zUoKlHdoiggkOdgJXzJS3Mtj0TFg2oxPHvklxBVEkDvVcDtgd2CpSHBGmp3 /eViLKipzxbuZi04HXyE2scd4YZwGkQYgIhSNvTf+4KsTFx/ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: 6Cm6BNhucBzU1pi2q9NUaIX4gnjfhzkG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDEzMiBTYWx0ZWRfX7jOppZnxNP5W 4k6JiBoQ4YMAuHg6kEiruTIM29qBDWsQ5THnekQ4hquEr0iCuGYL38f8UyS8CveqckM6mD/qTKB 6OeRrAvL7LX/vdfzBoRgtZu/pAjPcV0MpKBfxuIC7pFkUKkcBoGho+Ep5ya742WAqU8xoY6Dcro 0BkSQucM0iYpSdTAgV5jlMDyE4u4nKmLbOIUFr/ZZqTnu6GFs4e43fPmfYy9zcilLF+D0Qfq/SV 9rPR0OLqpSZaE+KvJSAY/Ew5q5DBkzMw7N8dl23ENgz5U2JfKsKsg774F1WnTElr3xfGNKj1wgs G72wCf/J73ttmepcQptrVFcnOiCkDnFJTeKgm0CfMoym+iaudQ+12ujsAny/tX0vYqo3hxKjls6 d81sv45U5Z98NrCMQjN0j87gj8fNPK84zo1MPSjZz8ty6bVNOFotofMB8H/XHXEbo7TloDYIZsZ aa8M8LLwy9xwICyD1YA== X-Proofpoint-GUID: 6Cm6BNhucBzU1pi2q9NUaIX4gnjfhzkG X-Authority-Analysis: v=2.4 cv=Wukb99fv c=1 sm=1 tr=0 ts=6a047360 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=iravrUNok-SDL5gDNRIA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130132 From: Dikshita Agarwal Introduces AR50LT buffer size calculation for both encoder and decoder. Reuse the buffer size calculation which are common, while adding the AR50LT specific ones separately. Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 401 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 37 ++ 2 files changed, 438 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 125fb2d6960d..e75684d6d97d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -50,6 +50,32 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 fra= me_height, u32 num_vpp_p return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 size_h264d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_heig= ht, u32 num_vpp_pipes) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((frame_width * frame_height * 3) >> 1); + if (size_yuv <=3D 1920 * 1088 * 3 / 2) { + size_bin_hdr =3D size_yuv * H264_CABAC_HDR_RATIO_SM_TOT; + size_bin_res =3D size_yuv * H264_CABAC_RES_RATIO_SM_TOT; + } else { + size_bin_hdr =3D (size_yuv * 3) / 5; + size_bin_res =3D (size_yuv * 3) / 2; + } + size_bin_hdr =3D ALIGN(size_bin_hdr, DMA_ALIGNMENT); + size_bin_res =3D ALIGN(size_bin_res, DMA_ALIGNMENT); + + return size_bin_hdr + size_bin_res; +} + +static u32 hfi_buffer_bin_h264d_ar50lt(u32 frame_width, u32 frame_height, = u32 num_vpp_pipes) +{ + u32 n_aligned_h =3D ALIGN(frame_height, 16); + u32 n_aligned_w =3D ALIGN(frame_width, 16); + + return size_h264d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_= pipes); +} + static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 = num_vpp_pipes) { u32 size_yuv, size_bin_hdr, size_bin_res; @@ -103,6 +129,21 @@ static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 fr= ame_height, u32 num_vpp_pi return _size * num_vpp_pipes; } =20 +static u32 hfi_buffer_bin_vp9d_ar50lt(u32 frame_width, u32 frame_height, u= 32 num_vpp_pipes) +{ + u32 size_yuv, size; + + size_yuv =3D ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2; + size_yuv =3D ALIGN(size_yuv, DMA_ALIGNMENT); + + size =3D ALIGN(((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 6)= / 5) / + num_vpp_pipes), DMA_ALIGNMENT) + + ALIGN((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 4) / num_vp= p_pipes), + DMA_ALIGNMENT); + + return size * num_vpp_pipes; +} + static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num= _vpp_pipes) { u32 n_aligned_w =3D ALIGN(frame_width, 16); @@ -111,6 +152,32 @@ static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 f= rame_height, u32 num_vpp_p return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 size_h265d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_heig= ht, u32 num_vpp_pipes) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((frame_width * frame_height * 3) >> 1); + if (size_yuv <=3D ((BIN_BUFFER_THRESHOLD * 3) >> 1)) { + size_bin_hdr =3D size_yuv * H265_CABAC_HDR_RATIO_SM_TOT; + size_bin_res =3D size_yuv * H265_CABAC_RES_RATIO_SM_TOT; + } else { + size_bin_hdr =3D (size_yuv * 41) / 50; + size_bin_res =3D (size_yuv * 59) / 50; + } + size_bin_hdr =3D ALIGN(size_bin_hdr, DMA_ALIGNMENT); + size_bin_res =3D ALIGN(size_bin_res, DMA_ALIGNMENT); + + return size_bin_hdr + size_bin_res; +} + +static u32 hfi_buffer_bin_h265d_ar50lt(u32 frame_width, u32 frame_height, = u32 num_vpp_pipes) +{ + u32 n_aligned_w =3D ALIGN(frame_width, 16); + u32 n_aligned_h =3D ALIGN(frame_height, 16); + + return size_h265d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_= pipes); +} + static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _c= omv_bufcount) { u32 frame_height_in_mbs =3D DIV_ROUND_UP(frame_height, 16); @@ -174,6 +241,14 @@ static u32 size_h264d_bse_cmd_buf(u32 frame_height) SIZE_H264D_BSE_CMD_PER_BUF; } =20 +static u32 size_h264d_bse_cmd_buf_ar50lt(u32 frame_height) +{ + u32 height =3D ALIGN(frame_height, 32); + + return min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) * + SIZE_H264D_BSE_CMD_PER_BUF; +} + static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height) { u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * @@ -185,6 +260,18 @@ static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32= frame_height) return _size; } =20 +static u32 size_h265d_bse_cmd_buf_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + + _size =3D min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1); + _size =3D 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF; + + return _size; +} + static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) { return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + @@ -195,6 +282,13 @@ static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_h265d_ar50lt(void) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + + H265_NUM_TILE * sizeof(u32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA), + DMA_ALIGNMENT); +} + static inline u32 hfi_iris3_vp9d_comv_size(void) { @@ -212,6 +306,13 @@ static u32 hfi_buffer_persist_vp9d(void) HDR10_HIST_EXTRADATA_SIZE; } =20 +static u32 hfi_buffer_persist_vp9d_ar50lt(void) +{ + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALI= GNMENT) + + ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT); +} + static u32 size_h264d_vpp_cmd_buf(u32 frame_height) { u32 size, height =3D ALIGN(frame_height, 32); @@ -222,6 +323,16 @@ static u32 size_h264d_vpp_cmd_buf(u32 frame_height) return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; } =20 +static u32 size_h264d_vpp_cmd_buf_ar50lt(u32 frame_height) +{ + u32 size, height =3D ALIGN(frame_height, 32); + + size =3D min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) * + SIZE_H264D_VPP_CMD_PER_BUF; + + return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; +} + static u32 hfi_buffer_persist_h264d(void) { return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + @@ -230,6 +341,11 @@ static u32 hfi_buffer_persist_h264d(void) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_h264d_ar50lt(void) +{ + return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264), DMA_ALIGNMENT); +} + static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 tota= l_ref_count) { u32 comv_size, size; @@ -255,6 +371,17 @@ static u32 hfi_buffer_non_comv_h264d(u32 frame_width, = u32 frame_height, u32 num_ return ALIGN(size, DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_non_comv_h264d_ar50lt(u32 frame_width, u32 frame_hei= ght, u32 num_vpp_pipes) +{ + u32 size_bse =3D size_h264d_bse_cmd_buf_ar50lt(frame_height); + u32 size_vpp =3D size_h264d_vpp_cmd_buf_ar50lt(frame_height); + u32 size =3D ALIGN(size_bse, DMA_ALIGNMENT) + + ALIGN(size_vpp, DMA_ALIGNMENT) + + ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height) { u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * @@ -269,6 +396,20 @@ static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32= frame_height) return _size; } =20 +static u32 size_h265d_vpp_cmd_buf_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + _size =3D min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1); + _size =3D ALIGN(_size, 4); + _size =3D 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF_AR50LT; + if (_size > VPP_CMD_MAX_SIZE) + _size =3D VPP_CMD_MAX_SIZE; + + return _size; +} + static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) { u32 _size_bse =3D size_h265d_bse_cmd_buf(frame_width, frame_height); @@ -285,6 +426,20 @@ static u32 hfi_buffer_non_comv_h265d(u32 frame_width, = u32 frame_height, u32 num_ return ALIGN(_size, DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_non_comv_h265d_ar50lt(u32 frame_width, u32 frame_hei= ght, u32 num_vpp_pipes) +{ + u32 _size_bse =3D size_h265d_bse_cmd_buf_ar50lt(frame_width, frame_height= ); + u32 _size_vpp =3D size_h265d_vpp_cmd_buf_ar50lt(frame_width, frame_height= ); + u32 _size =3D ALIGN(_size_bse, DMA_ALIGNMENT) + + ALIGN(_size_vpp, DMA_ALIGNMENT) + + ALIGN(2 * sizeof(u16) * + (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNM= ENT) + + ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT); + + return ALIGN(_size, DMA_ALIGNMENT); +} + static u32 size_vpss_lb(u32 frame_width, u32 frame_height) { u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; @@ -317,6 +472,13 @@ u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 fra= me_height) (ALIGN(frame_width, 64) + 8) * 2; } =20 +static inline +u32 size_h265d_lb_fe_top_data_ar50lt(u32 frame_width, u32 frame_height) +{ + return ALIGN(MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * + (ALIGN(frame_width, 64) + 8), DMA_ALIGNMENT) * 2; +} + static inline u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) { @@ -348,6 +510,17 @@ u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 fr= ame_height) MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); } =20 +static inline +u32 size_h265d_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 16 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT, + max_t(u32, ((frame_height + 32 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT, + ((frame_height + 64 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT)); +} + static inline u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height) { @@ -355,6 +528,13 @@ u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 fra= me_height) (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); } =20 +static inline +u32 size_h265d_lb_pe_top_data_ar50lt(u32 frame_width, u32 frame_height) +{ + return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT * + (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); +} + static inline u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height) { @@ -404,6 +584,29 @@ u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_h= eight, bool is_opb, u32 nu return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static inline +u32 hfi_buffer_line_h265d_ar50lt(u32 frame_width, u32 frame_height, bool i= s_opb, u32 num_vpp_pipes) +{ + u32 size; + + size =3D ALIGN(size_h265d_lb_fe_top_data_ar50lt(frame_width, frame_height= ), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_se_left_ctrl_ar50lt(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_pe_top_data_ar50lt(frame_width, frame_height), DMA_A= LIGNMENT) + + ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height), + DMA_ALIGNMENT) * 4 + + ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static inline u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) { @@ -438,6 +641,17 @@ u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 fra= me_height) MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); } =20 +static inline +u32 size_vpxd_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 15) >> 4) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT, + max_t(u32, ((frame_height + 31) >> 5) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT, + ((frame_height + 63) >> 6) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT)); +} + static inline u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) { @@ -492,6 +706,19 @@ u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_= height, u32 num_vpp_pipes) ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); } =20 +static inline +u32 hfi_ar50lt_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp= _pipes) +{ + return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_AL= IGNMENT) * + num_vpp_pipes + + ALIGN(size_vpxd_lb_se_left_ctrl_ar50lt(frame_width, frame_height), DMA_A= LIGNMENT) * + num_vpp_pipes + + ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ); +} + static inline u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufco= unt_min, bool is_opb, u32 num_vpp_pipes) @@ -507,6 +734,13 @@ u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_he= ight, u32 _yuv_bufcount_mi return _lb_size + vpss_lb_size + 4096; } =20 +static inline +u32 hfi_buffer_line_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 _yu= v_bufcount_min, + bool is_opb, u32 num_vpp_pipes) +{ + return hfi_ar50lt_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes); +} + static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes) { @@ -529,6 +763,25 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32 = frame_height, return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_line_h264d_ar50lt(u32 frame_width, u32 frame_height, + bool is_opb, u32 num_vpp_pipes) +{ + u32 size; + + size =3D ALIGN(size_h264d_lb_fe_top_data_ar50lt(frame_width), DMA_ALIGNME= NT) + + ALIGN(size_h264d_lb_fe_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp= _pipes + + ALIGN(size_h264d_lb_se_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_se_left_ctrl_ar50lt(frame_height), DMA_ALIGNMENT) * + num_vpp_pipes + + ALIGN(size_h264d_lb_pe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) = * 2 + + ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_heigh= t) { u32 size, y_width, y_width_a =3D 128; @@ -724,6 +977,23 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *ins= t) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_bin_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_bin_h264d_ar50lt(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_bin_h265d_ar50lt(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_bin_vp9d_ar50lt(width, height, num_vpp_pipes); + + return 0; +} + static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) { u32 num_comv =3D VIDEO_MAX_FRAME; @@ -767,6 +1037,18 @@ static u32 iris_vpu_dec_persist_size(struct iris_inst= *inst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_persist_size(struct iris_inst *inst) +{ + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_persist_h264d_ar50lt(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_persist_h265d_ar50lt(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_persist_vp9d_ar50lt(); + + return 0; +} + static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst) { if (iris_split_mode_enabled(inst)) @@ -790,6 +1072,21 @@ static u32 iris_vpu_dec_non_comv_size(struct iris_ins= t *inst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_non_comv_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_non_comv_h264d_ar50lt(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_non_comv_h265d_ar50lt(width, height, num_vpp_pipes); + + return 0; +} + static u32 iris_vpu_dec_line_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -815,6 +1112,29 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *i= nst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + bool is_opb =3D false; + u32 out_min_count =3D inst->buffers[BUF_OUTPUT].min_count; + + if (iris_split_mode_enabled(inst)) + is_opb =3D true; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_line_h264d_ar50lt(width, height, is_opb, num_vpp_pipes= ); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_line_h265d_ar50lt(width, height, is_opb, num_vpp_pipes= ); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_line_vp9d_ar50lt(width, height, out_min_count, is_opb, + num_vpp_pipes); + + return 0; +} + static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst) { return iris_vpu_dec_comv_size(inst) + @@ -822,6 +1142,13 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_ins= t *inst) iris_vpu_dec_line_size(inst); } =20 +static u32 iris_vpu_ar50lt_dec_scratch1_size(struct iris_inst *inst) +{ + return iris_vpu_dec_comv_size(inst) + + iris_vpu_ar50lt_dec_non_comv_size(inst) + + iris_vpu_ar50lt_dec_line_size(inst); +} + static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst) { if (is_rotation_90_or_270(inst)) @@ -1410,6 +1737,15 @@ u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_he= ight, bool is_ten_bit) return size; } =20 +static inline +u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_t= en_bit) +{ + if (!is_ten_bit) + return size_enc_ref_buffer(frame_width, frame_height); + else + return size_enc_ten_bit_ref_buffer(frame_width, frame_height); +} + static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) { return HFI_BUFFER_ARP_ENC; @@ -1434,6 +1770,16 @@ u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, b= ool ds_enable, return 0; } =20 +static inline +u32 hfi_buffer_vpss_enc_ar50lt(u32 dswidth, u32 dsheight, bool ds_enable, + u32 blur, bool is_ten_bit) +{ + if (ds_enable || blur) + return hfi_buffer_dpb_enc_ar50lt(dswidth, dsheight, is_ten_bit); + + return 0; +} + static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_heigh= t, u32 lcu_size, u32 num_ref, bool ten_bit, u32 num_vpp_pipes, @@ -1693,6 +2039,16 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *= inst) return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); } =20 +static u32 iris_vpu_ar50lt_enc_vpss_size(struct iris_inst *inst) +{ + u32 ds_enable =3D is_scaling_enabled(inst); + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_buffer_vpss_enc_ar50lt(width, height, ds_enable, 0, 0); +} + static inline u32 size_dpb_opb(u32 height, u32 lcu_size) { u32 max_tile_height =3D ((height + lcu_size - 1) / lcu_size) * lcu_size += 8; @@ -2148,6 +2504,51 @@ u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *= inst, enum iris_buffer_type return inst->buffers[buffer_type].size; } =20 +u32 iris_vpu_ar50lt_gen2_buf_size(struct iris_inst *inst, enum iris_buffer= _type buffer_type) +{ + const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; + u32 size =3D 0, buf_type_handle_size =3D 0, i; + + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_ar50lt_dec_bin_size }, + {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_NON_COMV, iris_vpu_ar50lt_dec_non_comv_size }, + {BUF_LINE, iris_vpu_ar50lt_dec_line_size }, + {BUF_PERSIST, iris_vpu_ar50lt_dec_persist_size }, + {BUF_DPB, iris_vpu_dec_dpb_size }, + {BUF_SCRATCH_1, iris_vpu_ar50lt_dec_scratch1_size }, + {BUF_PARTIAL, iris_vpu_dec_partial_size }, + }; + + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_ar50lt_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) { + buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); + buf_type_handle_arr =3D dec_internal_buf_type_handle; + } else if (inst->domain =3D=3D ENCODER) { + buf_type_handle_size =3D ARRAY_SIZE(enc_internal_buf_type_handle); + buf_type_handle_arr =3D enc_internal_buf_type_handle; + } + + for (i =3D 0; i < buf_type_handle_size; i++) { + if (buf_type_handle_arr[i].type =3D=3D buffer_type) { + size =3D buf_type_handle_arr[i].handle(inst); + break; + } + } + + return size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 1d07137c70cd..2085e316a6bd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -61,17 +61,26 @@ struct iris_inst; #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) +#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT (8 / 8) +#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT (16 / 8) +#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT (32 / 8) #define VP9_UDC_HEADER_BUF_SIZE (3 * 128) =20 #define SIZE_SEI_USERDATA 4096 #define SIZE_DOLBY_RPU_METADATA (41 * 1024) #define H264_CABAC_HDR_RATIO_HD_TOT 1 #define H264_CABAC_RES_RATIO_HD_TOT 3 +#define H264_CABAC_HDR_RATIO_SM_TOT 1 +#define H264_CABAC_RES_RATIO_SM_TOT 2 #define H265D_MAX_SLICE 3600 +#define H265D_MAX_SLICE_AR50LT 600 #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T #define H265_CABAC_HDR_RATIO_HD_TOT 2 #define H265_CABAC_RES_RATIO_HD_TOT 2 +#define H265_CABAC_HDR_RATIO_SM_TOT 1 +#define H265_CABAC_RES_RATIO_SM_TOT 6 #define SIZE_H265D_VPP_CMD_PER_BUF (256) +#define SIZE_H265D_VPP_CMD_PER_BUF_AR50LT (192) #define SIZE_THREE_DIMENSION_USERDATA 768 #define SIZE_H265D_ARP 9728 =20 @@ -81,6 +90,7 @@ struct iris_inst; #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 =20 #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) +#define VPX_DECODER_FRAME_BIN_BUFFER_SIZE (1024 * 1024) =20 #define SIZE_H264D_HW_PIC_T (BIT(11)) =20 @@ -99,6 +109,7 @@ struct iris_inst; #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 +#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT 176 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 =20 #define AV1_CABAC_HDR_RATIO_HD_TOT 2 @@ -155,11 +166,21 @@ static inline u32 size_h264d_lb_fe_top_data(u32 frame= _width) return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; } =20 +static inline u32 size_h264d_lb_fe_top_data_ar50lt(u32 frame_width) +{ + return 16 * ALIGN(frame_width, 16) * 2; +} + static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width) { return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_fe_top_ctrl_ar50lt(u32 frame_width) +{ + return 16 * DIV_ROUND_UP(frame_width, 16); +} + static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height) { return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height= , 16); @@ -170,16 +191,31 @@ static inline u32 size_h264d_lb_se_top_ctrl(u32 frame= _width) return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_se_top_ctrl_ar50lt(u32 frame_width) +{ + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame= _width, 16); +} + static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height) { return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height= , 16); } =20 +static inline u32 size_h264d_lb_se_left_ctrl_ar50lt(u32 frame_height) +{ + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame= _height, 16); +} + static inline u32 size_h264d_lb_pe_top_data(u32 frame_width) { return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_pe_top_data_ar50lt(u32 frame_width) +{ + return 64 * DIV_ROUND_UP(frame_width, 16); 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Follow the example of the SC7280 platform and extend the driver with supporting both HFI Gen1 and Gen2 firmwares for this platform. Like HFI Gen1 this firmware doesn't have PIPE property (but unlike Gen1 buffer sizes are calculated on the driver side). Signed-off-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_gen2.c | 613 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 11 +- 3 files changed, 623 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen2.c index ce8490d64854..61061d17afe5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -894,3 +894,616 @@ const struct iris_firmware_data iris_hfi_gen2_data = =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; + +static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_dec[] =3D= { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0), + .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D TIER, + .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D POC, + .min =3D 0, + .max =3D 2, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, + }, + { + .cap_id =3D CODED_FRAMES, + .min =3D CODED_FRAMES_PROGRESSIVE, + .max =3D CODED_FRAMES_PROGRESSIVE, + .step_or_mask =3D 0, + .value =3D CODED_FRAMES_PROGRESSIVE, + .hfi_id =3D HFI_PROP_CODED_FRAMES, + }, + { + .cap_id =3D BIT_DEPTH, + .min =3D BIT_DEPTH_8, + .max =3D BIT_DEPTH_8, + .step_or_mask =3D 1, + .value =3D BIT_DEPTH_8, + .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + }, + { + .cap_id =3D RAP_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_enc[] =3D= { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen2, + }, + { + .cap_id =3D PREPEND_SPSPPS_TO_IDR, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + }, + { + .cap_id =3D BITRATE, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_TOTAL_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate, + }, + { + .cap_id =3D BITRATE_PEAK, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_peak_bitrate, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROP_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen2, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 2 * DEFAULT_FPS - 1, + .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_u32, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .hfi_id =3D HFI_PROP_CABAC_SESSION, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen2, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D I_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D I_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D I_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D OUTPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D IR_TYPE, + .min =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .step_or_mask =3D BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RAND= OM), + .value =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D IR_PERIOD, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_ir_period, + }, +}; + +static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_COMV, + BUF_NON_COMV, + BUF_LINE, +}; + +const struct iris_firmware_data iris_hfi_gen2_ar50lt_data =3D { + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, + + .core_arch =3D VIDEO_ARCH_LX, + + .inst_fw_caps_dec =3D inst_fw_cap_gen2_ar50lt_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_dec), + .inst_fw_caps_enc =3D inst_fw_cap_gen2_ar50lt_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_enc), + .dec_input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_output_config_params =3D + sm8550_vdec_output_config_params, + .dec_output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_ip_int_buf_tbl =3D iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_b= uf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f9763ea51c53..e0c18780c045 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -47,6 +47,7 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data; extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_firmware_data iris_hfi_gen2_ar50lt_data; =20 extern const struct iris_platform_data qcm2290_data; extern const struct iris_platform_data qcs8300_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/= drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c index 76bebe012bd8..d2ee3039e35a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -13,12 +13,18 @@ =20 #define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10 =20 -const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc =3D { +const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_desc =3D { .firmware_data =3D &iris_hfi_gen1_ar50lt_data, .get_vpu_buffer_size =3D iris_vpu_ar50lt_gen1_buf_size, .fwname =3D "qcom/venus-6.0/venus.mbn", }; =20 +const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen2_s6_desc =3D { + .firmware_data =3D &iris_hfi_gen2_ar50lt_data, + .get_vpu_buffer_size =3D iris_vpu_ar50lt_gen2_buf_size, + .fwname =3D "qcom/vpu/ar50lt_p1_gen2_s6.mbn", +}; + static const u32 iris_fmts_ar50lt_dec[] =3D { [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, @@ -79,7 +85,8 @@ static struct platform_inst_caps platform_inst_cap_ar50lt= =3D { }; =20 const struct iris_platform_data qcm2290_data =3D { - .firmware_desc_gen1 =3D &iris_vpu_ar50lt_p1_gen1_s6_desc, + .firmware_desc_gen1 =3D &iris_vpu_ar50lt_p1_gen1_desc, + .firmware_desc_gen2 =3D &iris_vpu_ar50lt_p1_gen2_s6_desc, .vpu_ops =3D &iris_vpu_ar50lt_ops, .icc_tbl =3D iris_icc_info_ar50lt, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_ar50lt), --=20 2.47.3 From nobody Fri Jun 12 17:16:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher 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Follow the approach used by other platforms and skip QCM2290 in the Venus driver if Iris is enabled. Signed-off-by: Dmitry Baryshkov Reviewed-by: Dikshita Agarwal --- drivers/media/platform/qcom/venus/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platf= orm/qcom/venus/core.c index a87e8afb23df..8838fa958571 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -1074,7 +1074,6 @@ static const struct venus_resources sc7280_res =3D { .dec_nodename =3D "video-decoder", .enc_nodename =3D "video-encoder", }; -#endif =20 static const struct bw_tbl qcm2290_bw_table_dec[] =3D { { 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */ @@ -1125,12 +1124,15 @@ static const struct venus_resources qcm2290_res =3D= { .enc_nodename =3D "video-encoder", .min_fw =3D &min_fw, }; +#endif =20 static const struct of_device_id venus_dt_match[] =3D { { .compatible =3D "qcom,msm8916-venus", .data =3D &msm8916_res, }, { .compatible =3D "qcom,msm8996-venus", .data =3D &msm8996_res, }, { .compatible =3D "qcom,msm8998-venus", .data =3D &msm8998_res, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) { .compatible =3D "qcom,qcm2290-venus", .data =3D &qcm2290_res, }, +#endif { .compatible =3D "qcom,sc7180-venus", .data =3D &sc7180_res, }, { .compatible =3D "qcom,sdm660-venus", .data =3D &sdm660_res, }, { .compatible =3D "qcom,sdm845-venus", .data =3D &sdm845_res, }, --=20 2.47.3 From nobody Fri Jun 12 17:16:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3118842315B for ; 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Suggested-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.c index 39e88d5dd6d5..6ec5ecfc7759 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -13,7 +13,7 @@ #define BITRATE_MAX 160000000 #define BITRATE_STEP 100 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, /* .max, .min and .value are set via platform data */ --=20 2.47.3