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Add compatible string for Eliza video clock controller to the existing Milos videocc binding and add the dt-bindings header for Eliza. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,milos-videocc.yaml | 9 ++++-- include/dt-bindings/clock/qcom,eliza-videocc.h | 37 ++++++++++++++++++= ++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yam= l b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml index 14c31efe1308aadbea61eb7be7e56039a923aec5..6e3e4424af78a93f6366378a66f= 2944a3bfdccee 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Video Clock & Reset Controller on Milos =20 maintainers: - Luca Weiss + - Taniya Das =20 description: | Qualcomm video clock control module provides the clocks, resets and power domains on Milos. =20 - See also: include/dt-bindings/clock/qcom,milos-videocc.h + See also: + include/dt-bindings/clock/qcom,eliza-videocc.h + include/dt-bindings/clock/qcom,milos-videocc.h =20 properties: compatible: - const: qcom,milos-videocc + enum: + - qcom,eliza-videocc + - qcom,milos-videocc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,eliza-videocc.h b/include/dt-bi= ndings/clock/qcom,eliza-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..1e922250a7fae77f5c996208d50= ff372b252aa51 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-videocc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_ELIZA_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0C_CLK 6 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS0C_SHIFT_CLK 8 +#define VIDEO_CC_PLL0 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_CLK_ARES 1 +#define VIDEO_CC_MVS0_BCR 2 +#define VIDEO_CC_MVS0C_CLK_ARES 3 +#define VIDEO_CC_MVS0C_BCR 4 +#define VIDEO_CC_XO_CLK_ARES 5 + +#endif --=20 2.34.1 From nobody Fri Jun 12 17:19:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68A3947ECC1 for ; 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Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 ++ include/dt-bindings/clock/qcom,eliza-gpucc.h | 52 ++++++++++++++++++= ++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index fdbdf605ee695637512ce4f98c9b6fcfacb9154f..734bab762a30800bda94c726f48= 013679f9ec542 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,6 +15,7 @@ description: | domains on Qualcomm SoCs. =20 See also: + include/dt-bindings/clock/qcom,eliza-gpucc.h include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h @@ -30,6 +31,7 @@ description: | properties: compatible: enum: + - qcom,eliza-gpucc - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc @@ -71,6 +73,7 @@ allOf: compatible: contains: enum: + - qcom,eliza-gpucc - qcom,sm8750-gpucc then: required: diff --git a/include/dt-bindings/clock/qcom,eliza-gpucc.h b/include/dt-bind= ings/clock/qcom,eliza-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..706e1c93240a8234dd8017ee181= d19e58091fd6d --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gpucc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DEMET_DIV_CLK_SRC 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GPU_SMMU_VOTE_CLK 12 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 13 +#define GPU_CC_HUB_AON_CLK 14 +#define GPU_CC_HUB_CLK_SRC 15 +#define GPU_CC_HUB_CX_INT_CLK 16 +#define GPU_CC_MEMNOC_GFX_CLK 17 +#define GPU_CC_MND1X_0_GFX3D_CLK 18 +#define GPU_CC_MND1X_1_GFX3D_CLK 19 +#define GPU_CC_PLL0 20 +#define GPU_CC_PLL1 21 +#define GPU_CC_SLEEP_CLK 22 +#define GPU_CC_XO_CLK_SRC 23 +#define GPU_CC_XO_DIV_CLK_SRC 24 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_FF_BCR 4 +#define GPU_CC_GFX3D_AON_BCR 5 +#define GPU_CC_GMU_BCR 6 +#define GPU_CC_GX_BCR 7 +#define GPU_CC_RBCPR_BCR 8 +#define GPU_CC_XO_BCR 9 + +#endif --=20 2.34.1 From nobody Fri Jun 12 17:19:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08A8647B406 for ; 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Wed, 13 May 2026 08:28:07 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1eafa62sm185042375ad.74.2026.05.13.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 08:28:07 -0700 (PDT) From: Taniya Das Date: Wed, 13 May 2026 20:57:38 +0530 Subject: [PATCH v4 3/7] dt-bindings: clock: qcom: Add support for CAMCC for Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-eliza_mm_cc_v2-v4-3-e61b5434e8d9@oss.qualcomm.com> References: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> In-Reply-To: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue , Luca Weiss Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=X4di7mTe c=1 sm=1 tr=0 ts=6a04988d cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=6H0WHjuAAAAA:8 a=YEWKzK2yvWZE8rxvnj4A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-GUID: MlxZ1zfxQiqPIZf15JDXlhjVPyAzEeCy X-Proofpoint-ORIG-GUID: MlxZ1zfxQiqPIZf15JDXlhjVPyAzEeCy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE1OCBTYWx0ZWRfX4lG1O6I1cuUH nAd1PgH5aimyUzPWCXlBHVTfyHneU5fEYqqpkgR5T0B7LM9ZjFTkSWRnTkBzYIwx8t9+kBgaZAa OyPheUBrOyyeuVLKroWLYlVVGcv1Y2hn2OcbeKpHDfzx9rEol8BgMTKpoRPIOQl8glgcE6pb/vS PmpXwuzZXTp0bddOa1cK4PerAkHOPaIrKwvukDGT5PfST39J5f6aTg89nphwEfnSIsw3g46+o02 vC/+Mh7oL1FVUAPjCOn5BmCdWo5K2o1AuPT8SDwq7G7AESFIyrwHXd7uGNdoj2kIPylsLr5TRnx filr3TRKkfm5r+P4j48EubVPDSnMEUyQpW4UTq95xFMalTch6tp5b7roLRjiLYrj53g//5R8rfW aVl44DrRWg6wM8inG9slIGgBV1V1EhO/xcX24eK+BXJTTvxVjJfM4YOrcaIy++uHt77rOB+g1Hm U8RnUfUl4HlEzvydwpg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130158 Eliza camera clock controller is on CX and MX rails similar to Milos. Add compatible string for Eliza camera and camera BIST clock controller to the existing Milos camcc binding and add the dt-bindings header for Eliza. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,milos-camcc.yaml | 11 +- .../dt-bindings/clock/qcom,eliza-cambistmclkcc.h | 32 +++++ include/dt-bindings/clock/qcom,eliza-camcc.h | 151 +++++++++++++++++= ++++ 3 files changed, 192 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml index f63149ecf3e1b98e60dba27093737ec84b66a899..fe94dbeb80c603b64e67b3fe328= 9db1a81f8991a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml @@ -8,16 +8,23 @@ title: Qualcomm Camera Clock & Reset Controller on Milos =20 maintainers: - Luca Weiss + - Taniya Das =20 description: | Qualcomm camera clock control module provides the clocks, resets and pow= er domains on Milos. =20 - See also: include/dt-bindings/clock/qcom,milos-camcc.h + See also: + include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h + include/dt-bindings/clock/qcom,eliza-camcc.h + include/dt-bindings/clock/qcom,milos-camcc.h =20 properties: compatible: - const: qcom,milos-camcc + enum: + - qcom,eliza-cambistmclkcc + - qcom,eliza-camcc + - qcom,milos-camcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h b/include= /dt-bindings/clock/qcom,eliza-cambistmclkcc.h new file mode 100644 index 0000000000000000000000000000000000000000..7b8b285f18d2714393885149fc9= 7c715b3fbb042 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-cambistmclkcc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_ELIZA_H + +/* CAM_BIST_MCLK_CC clocks */ +#define CAM_BIST_MCLK_CC_MCLK0_CLK 0 +#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 1 +#define CAM_BIST_MCLK_CC_MCLK1_CLK 2 +#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 3 +#define CAM_BIST_MCLK_CC_MCLK2_CLK 4 +#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 5 +#define CAM_BIST_MCLK_CC_MCLK3_CLK 6 +#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 7 +#define CAM_BIST_MCLK_CC_MCLK4_CLK 8 +#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 9 +#define CAM_BIST_MCLK_CC_MCLK5_CLK 10 +#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 11 +#define CAM_BIST_MCLK_CC_MCLK6_CLK 12 +#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 13 +#define CAM_BIST_MCLK_CC_MCLK7_CLK 14 +#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 15 +#define CAM_BIST_MCLK_CC_PLL0 16 +#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 17 +#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 18 +#define CAM_BIST_MCLK_CC_SLEEP_CLK 19 +#define CAM_BIST_MCLK_CC_SLEEP_CLK_SRC 20 + +#endif diff --git a/include/dt-bindings/clock/qcom,eliza-camcc.h b/include/dt-bind= ings/clock/qcom,eliza-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..d85ef9777d08d12ec349d57f6da= 5e76a305404f8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-camcc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_ELIZA_H + +/* CAM_CC clocks */ +#define CAM_CC_CAM_TOP_AHB_CLK 0 +#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 3 +#define CAM_CC_CAMNOC_NRT_CRE_CLK 4 +#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5 +#define CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK 6 +#define CAM_CC_CAMNOC_NRT_OFE_HDR_CLK 7 +#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 8 +#define CAM_CC_CAMNOC_RT_AXI_CLK 9 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10 +#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11 +#define CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK 12 +#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 13 +#define CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK 14 +#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 15 +#define CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK 16 +#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 17 +#define CAM_CC_CAMNOC_XO_CLK 18 +#define CAM_CC_CCI_0_CLK 19 +#define CAM_CC_CCI_0_CLK_SRC 20 +#define CAM_CC_CCI_1_CLK 21 +#define CAM_CC_CCI_1_CLK_SRC 22 +#define CAM_CC_CCI_2_CLK 23 +#define CAM_CC_CCI_2_CLK_SRC 24 +#define CAM_CC_CORE_AHB_CLK 25 +#define CAM_CC_CPHY_RX_CLK_SRC 26 +#define CAM_CC_CRE_AHB_CLK 27 +#define CAM_CC_CRE_CLK 28 +#define CAM_CC_CRE_CLK_SRC 29 +#define CAM_CC_CSI0PHYTIMER_CLK 30 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI1PHYTIMER_CLK 32 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI2PHYTIMER_CLK 34 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI3PHYTIMER_CLK 36 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI4PHYTIMER_CLK 38 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI5PHYTIMER_CLK 40 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSID_CLK 42 +#define CAM_CC_CSID_CLK_SRC 43 +#define CAM_CC_CSID_CSIPHY_RX_CLK 44 +#define CAM_CC_CSIPHY0_CLK 45 +#define CAM_CC_CSIPHY1_CLK 46 +#define CAM_CC_CSIPHY2_CLK 47 +#define CAM_CC_CSIPHY3_CLK 48 +#define CAM_CC_CSIPHY4_CLK 49 +#define CAM_CC_CSIPHY5_CLK 50 +#define CAM_CC_DRV_AHB_CLK 51 +#define CAM_CC_DRV_XO_CLK 52 +#define CAM_CC_FAST_AHB_CLK_SRC 53 +#define CAM_CC_GDSC_CLK 54 +#define CAM_CC_ICP_0_AHB_CLK 55 +#define CAM_CC_ICP_0_CLK 56 +#define CAM_CC_ICP_0_CLK_SRC 57 +#define CAM_CC_ICP_1_AHB_CLK 58 +#define CAM_CC_ICP_1_CLK 59 +#define CAM_CC_ICP_1_CLK_SRC 60 +#define CAM_CC_IFE_LITE_AHB_CLK 61 +#define CAM_CC_IFE_LITE_CLK 62 +#define CAM_CC_IFE_LITE_CLK_SRC 63 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 64 +#define CAM_CC_IFE_LITE_CSID_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 66 +#define CAM_CC_IPE_NPS_AHB_CLK 67 +#define CAM_CC_IPE_NPS_CLK 68 +#define CAM_CC_IPE_NPS_CLK_SRC 69 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 70 +#define CAM_CC_IPE_PPS_CLK 71 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 72 +#define CAM_CC_JPEG_0_CLK 73 +#define CAM_CC_JPEG_1_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_OFE_AHB_CLK 76 +#define CAM_CC_OFE_ANCHOR_CLK 77 +#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 78 +#define CAM_CC_OFE_CLK_SRC 79 +#define CAM_CC_OFE_HDR_CLK 80 +#define CAM_CC_OFE_HDR_FAST_AHB_CLK 81 +#define CAM_CC_OFE_MAIN_CLK 82 +#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 83 +#define CAM_CC_PLL0 84 +#define CAM_CC_PLL0_OUT_EVEN 85 +#define CAM_CC_PLL0_OUT_ODD 86 +#define CAM_CC_PLL1 87 +#define CAM_CC_PLL1_OUT_EVEN 88 +#define CAM_CC_PLL2 89 +#define CAM_CC_PLL2_OUT_EVEN 90 +#define CAM_CC_PLL3 91 +#define CAM_CC_PLL3_OUT_EVEN 92 +#define CAM_CC_PLL4 93 +#define CAM_CC_PLL4_OUT_EVEN 94 +#define CAM_CC_PLL5 95 +#define CAM_CC_PLL5_OUT_EVEN 96 +#define CAM_CC_PLL6 97 +#define CAM_CC_PLL6_OUT_EVEN 98 +#define CAM_CC_PLL6_OUT_ODD 99 +#define CAM_CC_QDSS_DEBUG_CLK 100 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 101 +#define CAM_CC_QDSS_DEBUG_XO_CLK 102 +#define CAM_CC_SLEEP_CLK 103 +#define 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d9443c01a7336-2baf1eafa62sm185042375ad.74.2026.05.13.08.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 08:28:18 -0700 (PDT) From: Taniya Das Date: Wed, 13 May 2026 20:57:39 +0530 Subject: [PATCH v4 4/7] clk: qcom: videocc: Add video clock controller driver for Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-eliza_mm_cc_v2-v4-4-e61b5434e8d9@oss.qualcomm.com> References: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> In-Reply-To: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue , Luca Weiss Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE1OCBTYWx0ZWRfXwXDz0fAPKYai kO80bdpNODTLb8eCV3LC4Y7ZeO9g0nPKDJefsScW60OI4eJK41GZpr5tSGIv982fXo3NzaQt14J bGuFWD9GciiD4i9GKwO1sfO2aemF9bl4xjxSabdEnESXzf0e0UK/kjhEups6Ii04oMy/JnRlLJw dXlrGzXM8wXOeFPDGY4VrpLhQmubvdfjLbyYFjD7F1df3LSREML6pGjMneAdVyj9R68/hc1gAWE 0Hdkq3h0+jWSrO7i6zVGA/KCG8W4iDl1zbJD9tKwkHfbyoFmD8m30l7HwxjJOMw8bwJZQc4imLW ua9M+idqJ4CjD4j1o1W1I1AxmDcD4FxwoVXoDir7pcQTroqGrgtXMrce43V1407Em+3EjUFdPOX PxDBsP1mPs+JGUCK6rtGA02f8QltIssCRqeCn6kMaACKIn7ecBLSsWZ+iRhmprXYMV0/C+Fxg/M h/DiTEAaQy4gnM6gO3Q== X-Proofpoint-ORIG-GUID: CI7ur6bkxrY9I6P-3t7GkWuAacQ-WR8e X-Authority-Analysis: v=2.4 cv=TJZ1jVla c=1 sm=1 tr=0 ts=6a049893 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=fDr36jkL0Xr7p1dDRlIA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: CI7ur6bkxrY9I6P-3t7GkWuAacQ-WR8e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130158 Add support for the video clock controller for video clients to be able to request for videocc clocks on Eliza platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-eliza.c | 404 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 415 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 22eb80be60ad3bde897f2c507ac9897951fbb8fe..0cddeb4cb78ac2de9e8ea29af05= 0c7285f5e43ec 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -45,6 +45,16 @@ config CLK_ELIZA_TCSRCC Support for the TCSR clock controller on Eliza devices. Say Y if you want to use peripheral devices such as USB/PCIe/UFS. =20 +config CLK_ELIZA_VIDEOCC + tristate "Eliza Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_ELIZA_GCC + default m if ARCH_QCOM + help + Support for the video clock controller on Eliza devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config CLK_GLYMUR_DISPCC tristate "Glymur Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b818fd5af8bfb85a51ee90fdc3baa93af30dc39a..e7e239c5a0d088b2e78354bf421= d871a4e4e6d9d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) +=3D mmcc-apq8084.o obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o +obj-$(CONFIG_CLK_ELIZA_VIDEOCC) +=3D videocc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o diff --git a/drivers/clk/qcom/videocc-eliza.c b/drivers/clk/qcom/videocc-el= iza.c new file mode 100644 index 0000000000000000000000000000000000000000..36af35e070299718106f1b8e8db= c23f20279ea85 --- /dev/null +++ b/drivers/clk/qcom/videocc-eliza.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 576.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x1e, + .alpha =3D 0x0, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(633000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1113000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x8110, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x80f4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0x80ac, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x8058, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80a0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x8144, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8144, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x8148, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8148, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x8034, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x808c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, +}; + +static struct clk_regmap *video_cc_eliza_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_eliza_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_eliza_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x80d8 }, + [VIDEO_CC_MVS0_CLK_ARES] =3D { 0x80a0, 2 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x8088 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x804c, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8030 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x810c, 2 }, +}; + +static struct clk_alpha_pll *video_cc_eliza_plls[] =3D { + &video_cc_pll0, +}; + +static u32 video_cc_eliza_critical_cbcrs[] =3D { + 0x80dc, /* VIDEO_CC_AHB_CLK */ + 0x8128, /* VIDEO_CC_SLEEP_CLK */ + 0x810c, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_eliza_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f50, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data video_cc_eliza_driver_data =3D { + .alpha_plls =3D video_cc_eliza_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_eliza_plls), + .clk_cbcrs =3D video_cc_eliza_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_eliza_critical_cbcrs), +}; + +static const struct qcom_cc_desc video_cc_eliza_desc =3D { + .config =3D &video_cc_eliza_regmap_config, + .clks =3D video_cc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_eliza_clocks), + .resets =3D video_cc_eliza_resets, + .num_resets =3D ARRAY_SIZE(video_cc_eliza_resets), + .gdscs =3D video_cc_eliza_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_eliza_gdscs), + .driver_data =3D &video_cc_eliza_driver_data, +}; + +static const struct of_device_id video_cc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_eliza_match_table); + +static int video_cc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_eliza_desc); +} + +static struct platform_driver video_cc_eliza_driver =3D { + .probe =3D video_cc_eliza_probe, + .driver =3D { + .name =3D "videocc-eliza", + .of_match_table =3D video_cc_eliza_match_table, + }, +}; + +module_platform_driver(video_cc_eliza_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC Eliza Driver"); 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Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-eliza.c | 621 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 632 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0cddeb4cb78ac2de9e8ea29af050c7285f5e43ec..084af4c72250edfb41a9bef1b63= 9ed5d144f6d1a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -37,6 +37,16 @@ config CLK_ELIZA_GCC Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. =20 +config CLK_ELIZA_GPUCC + tristate "Eliza Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_ELIZA_GCC + default m if ARCH_QCOM + help + Support for the graphics clock controller on Eliza devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_ELIZA_TCSRCC tristate "Eliza TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e7e239c5a0d088b2e78354bf421d871a4e4e6d9d..1c34797eb385963110614ba43eb= 9bbc9653699fb 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_GCC_8084) +=3D gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) +=3D mmcc-apq8084.o obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o +obj-$(CONFIG_CLK_ELIZA_GPUCC) +=3D gpucc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_ELIZA_VIDEOCC) +=3D videocc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o diff --git a/drivers/clk/qcom/gpucc-eliza.c b/drivers/clk/qcom/gpucc-eliza.c new file mode 100644 index 0000000000000000000000000000000000000000..85ae0ab1184053ce03809176a64= f5d47d3a411b9 --- /dev/null +++ b/drivers/clk/qcom/gpucc-eliza.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 518.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x1a, + .alpha =3D 0xfaaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 440.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x16, + .alpha =3D 0xeaaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &gpu_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src =3D { + .cmd_rcgr =3D 0x94b8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ff_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x935c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x9430, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_2, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x9010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_3, + .freq_tbl =3D ftbl_gpu_cc_xo_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_xo_clk_src", + .parent_data =3D gpu_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_xo_div_clk_src =3D { + .reg =3D 0x9050, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_xo_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x914c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x914c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x9150, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x9480, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9480, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk =3D { + .halt_reg =3D 0x9184, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9184, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_ff_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x916c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x916c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x917c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x917c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x9008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_xo_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x942c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x942c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x9180, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9180, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x9188, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9188, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk =3D { + .halt_reg =3D 0x92cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x92cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_mnd1x_0_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk =3D { + .halt_reg =3D 0x92d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x92d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_mnd1x_1_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x9164, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9110, + .gds_hw_ctrl =3D 0x9124, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_cc_gx_gdsc =3D { + .gdscr =3D 0x905c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_cc_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_eliza_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] =3D &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] =3D &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] =3D &gpu_cc_xo_clk_src.clkr, + [GPU_CC_XO_DIV_CLK_SRC] =3D &gpu_cc_xo_div_clk_src.clkr, +}; + +static struct gdsc *gpu_cc_eliza_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, + [GPU_CC_GX_GDSC] =3D &gpu_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_eliza_resets[] =3D { + [GPU_CC_ACD_BCR] =3D { 0x939c }, + [GPU_CC_CB_BCR] =3D { 0x93e4 }, + [GPU_CC_CX_BCR] =3D { 0x910c }, + [GPU_CC_FAST_HUB_BCR] =3D { 0x9428 }, + [GPU_CC_FF_BCR] =3D { 0x94b4 }, + [GPU_CC_GFX3D_AON_BCR] =3D { 0x91dc }, + [GPU_CC_GMU_BCR] =3D { 0x9358 }, + [GPU_CC_GX_BCR] =3D { 0x9058 }, + [GPU_CC_RBCPR_BCR] =3D { 0x9224 }, + [GPU_CC_XO_BCR] =3D { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_cc_eliza_plls[] =3D { + &gpu_cc_pll0, + &gpu_cc_pll1, +}; + +static u32 gpu_cc_eliza_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_CXO_AON_CLK */ + 0x900c, /* GPU_CC_DEMET_CLK */ +}; + +static const struct regmap_config gpu_cc_eliza_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9988, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data gpu_cc_eliza_driver_data =3D { + .alpha_plls =3D gpu_cc_eliza_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_eliza_plls), + .clk_cbcrs =3D gpu_cc_eliza_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_eliza_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_eliza_desc =3D { + .config =3D &gpu_cc_eliza_regmap_config, + .clks =3D gpu_cc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_eliza_clocks), + .resets =3D gpu_cc_eliza_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_eliza_resets), + .gdscs =3D gpu_cc_eliza_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_eliza_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_eliza_driver_data, +}; + +static const struct of_device_id gpu_cc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_eliza_match_table); + +static int gpu_cc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_eliza_desc); +} + +static struct platform_driver gpu_cc_eliza_driver =3D { + .probe =3D gpu_cc_eliza_probe, + .driver =3D { + .name =3D "gpucc-eliza", + .of_match_table =3D gpu_cc_eliza_match_table, + }, +}; + +module_platform_driver(gpu_cc_eliza_driver); + +MODULE_DESCRIPTION("QTI GPUCC Eliza Driver"); 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Wed, 13 May 2026 08:28:31 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1eafa62sm185042375ad.74.2026.05.13.08.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 08:28:31 -0700 (PDT) From: Taniya Das Date: Wed, 13 May 2026 20:57:41 +0530 Subject: [PATCH v4 6/7] clk: qcom: camcc: Add support for camera clock controller for Eliza Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-eliza_mm_cc_v2-v4-6-e61b5434e8d9@oss.qualcomm.com> References: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> In-Reply-To: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue , Luca Weiss Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE1OCBTYWx0ZWRfX18Wm5xlyLF4b KydjhAS45GfBW0e1ru16r2+/G/+npFehZ9vyKIxlnt9f3axKoQKmlzBUpeOP/QgD1FsOvDNX7IB 0YR4NsPIXKOMkk4MRcoRcxSfpyhsjZWIv5Hg9drbtkjlWyRHwF4q9rmhNVT4CTZqMDOyNGupTVZ oNT+GPin41SuaWRW0YPHhiWf28ws6FtvTodSBvFp4wx4gvgdh5tKNXxUtnCwzAqs6hQvLg9LpdH /YL7tV0hQVhUZBzAIkYdLkFigrRBD8Toh7esucwEj+zH1J9fibB65kH9U8/LnDHtJTx54uTcXSn G2kVB5gaLK6kvpn+RJ5wnj0zeZqVGrHgTaDhKcbvv0UpYAOCqcYG3hCy4rcpWXoac1k6L19hDk/ T3MFX2rOBLg+YS2BGFIpbHZyePc7FehnOIZi8PS1WtS2bMFJzBxuwvd8n9UMs3kmh3joLQDxEbD qCv7ak0fGveOAJb6hYQ== X-Proofpoint-ORIG-GUID: hawA5wI_ZVq6g2PCmtM6rhWn2XQ2opC_ X-Authority-Analysis: v=2.4 cv=TJZ1jVla c=1 sm=1 tr=0 ts=6a0498a3 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=X1llO5yGiJ2-4Hw6Iw4A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: hawA5wI_ZVq6g2PCmtM6rhWn2XQ2opC_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130158 Add support for the Camera Clock Controller (CAMCC) on the Eliza platform. The CAMCC block on Eliza includes both the primary camera clock controller and the Camera BIST clock controller, which provides the functional MCLK required for camera operations. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/cambistmclkcc-eliza.c | 465 ++++++ drivers/clk/qcom/camcc-eliza.c | 2803 ++++++++++++++++++++++++++++= ++++ 4 files changed, 3280 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 084af4c72250edfb41a9bef1b639ed5d144f6d1a..712d1224c8b959f187ede159e08= 4440738326382 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -19,6 +19,17 @@ menuconfig COMMON_CLK_QCOM =20 if COMMON_CLK_QCOM =20 +config CLK_ELIZA_CAMCC + tristate "Eliza Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_ELIZA_GCC + default m if ARCH_QCOM + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Eliza devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_ELIZA_DISPCC tristate "Eliza Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1c34797eb385963110614ba43eb9bbc9653699fb..12574157b7c8a82c890996502f7= 9da03f25cfaa2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) +=3D gdsc.o # Keep alphabetically sorted by config obj-$(CONFIG_APQ_GCC_8084) +=3D gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) +=3D mmcc-apq8084.o +obj-$(CONFIG_CLK_ELIZA_CAMCC) +=3D cambistmclkcc-eliza.o camcc-eliza.o obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GPUCC) +=3D gpucc-eliza.o diff --git a/drivers/clk/qcom/cambistmclkcc-eliza.c b/drivers/clk/qcom/camb= istmclkcc-eliza.c new file mode 100644 index 0000000000000000000000000000000000000000..b65e224a1be907701899a598764= 4ad8f1af23b88 --- /dev/null +++ b/drivers/clk/qcom/cambistmclkcc-eliza.c @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, + P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco rivian_ole_vco[] =3D { + { 777000000, 1285000000, 0 }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config =3D { + .l =3D 0x32, + .cal_l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x10000030, + .config_ctl_hi_val =3D 0x80890263, + .config_ctl_hi1_val =3D 0x00000217, + .user_ctl_val =3D 0x00000001, + .user_ctl_hi_val =3D 0x00000000, +}; + +static struct clk_alpha_pll cam_bist_mclk_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_bist_mclk_cc_pll0_config, + .vco_table =3D rivian_ole_vco, + .num_vco =3D ARRAY_SIZE(rivian_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct parent_map cam_bist_mclk_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 }, + { P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_bist_mclk_cc_pll0.clkr.hw }, + { .hw =3D &cam_bist_mclk_cc_pll0.clkr.hw }, +}; + +static const struct parent_map cam_bist_mclk_cc_parent_map_1[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_bist_mclk_cc_parent_data_1[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4), + F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x4000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk0_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src =3D { + .cmd_rcgr =3D 0x401c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk1_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src =3D { + .cmd_rcgr =3D 0x4038, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk2_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src =3D { + .cmd_rcgr =3D 0x4054, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk3_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src =3D { + .cmd_rcgr =3D 0x4070, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk4_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src =3D { + .cmd_rcgr =3D 0x408c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk5_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src =3D { + .cmd_rcgr =3D 0x40a8, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk6_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src =3D { + .cmd_rcgr =3D 0x40c4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_mclk0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk7_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_bist_mclk_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_bist_mclk_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x40e0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_bist_mclk_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_bist_mclk_cc_sleep_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_sleep_clk_src", + .parent_data =3D cam_bist_mclk_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_bist_mclk_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk0_clk =3D { + .halt_reg =3D 0x4018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk1_clk =3D { + .halt_reg =3D 0x4034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk2_clk =3D { + .halt_reg =3D 0x4050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk3_clk =3D { + .halt_reg =3D 0x406c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x406c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk4_clk =3D { + .halt_reg =3D 0x4088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk5_clk =3D { + .halt_reg =3D 0x40a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk6_clk =3D { + .halt_reg =3D 0x40c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_bist_mclk_cc_mclk7_clk =3D { + .halt_reg =3D 0x40dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x40dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_bist_mclk_cc_mclk7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_bist_mclk_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *cam_bist_mclk_cc_eliza_clocks[] =3D { + [CAM_BIST_MCLK_CC_MCLK0_CLK] =3D &cam_bist_mclk_cc_mclk0_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] =3D &cam_bist_mclk_cc_mclk0_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK1_CLK] =3D &cam_bist_mclk_cc_mclk1_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] =3D &cam_bist_mclk_cc_mclk1_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK2_CLK] =3D &cam_bist_mclk_cc_mclk2_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] =3D &cam_bist_mclk_cc_mclk2_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK3_CLK] =3D &cam_bist_mclk_cc_mclk3_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] =3D &cam_bist_mclk_cc_mclk3_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK4_CLK] =3D &cam_bist_mclk_cc_mclk4_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] =3D &cam_bist_mclk_cc_mclk4_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK5_CLK] =3D &cam_bist_mclk_cc_mclk5_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] =3D &cam_bist_mclk_cc_mclk5_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK6_CLK] =3D &cam_bist_mclk_cc_mclk6_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] =3D &cam_bist_mclk_cc_mclk6_clk_src.clkr, + [CAM_BIST_MCLK_CC_MCLK7_CLK] =3D &cam_bist_mclk_cc_mclk7_clk.clkr, + [CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] =3D &cam_bist_mclk_cc_mclk7_clk_src.clkr, + [CAM_BIST_MCLK_CC_PLL0] =3D &cam_bist_mclk_cc_pll0.clkr, + [CAM_BIST_MCLK_CC_SLEEP_CLK_SRC] =3D &cam_bist_mclk_cc_sleep_clk_src.clkr, +}; + +static struct clk_alpha_pll *cam_bist_mclk_cc_eliza_plls[] =3D { + &cam_bist_mclk_cc_pll0, +}; + +static u32 cam_bist_mclk_cc_eliza_critical_cbcrs[] =3D { + 0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_bist_mclk_cc_eliza_regmap_config =3D= { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5010, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data cam_bist_mclk_cc_eliza_driver_data =3D { + .alpha_plls =3D cam_bist_mclk_cc_eliza_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_bist_mclk_cc_eliza_plls), + .clk_cbcrs =3D cam_bist_mclk_cc_eliza_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_bist_mclk_cc_eliza_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_bist_mclk_cc_eliza_desc =3D { + .config =3D &cam_bist_mclk_cc_eliza_regmap_config, + .clks =3D cam_bist_mclk_cc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(cam_bist_mclk_cc_eliza_clocks), + .use_rpm =3D true, + .driver_data =3D &cam_bist_mclk_cc_eliza_driver_data, +}; + +static const struct of_device_id cam_bist_mclk_cc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-cambistmclkcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_eliza_match_table); + +static int cam_bist_mclk_cc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_bist_mclk_cc_eliza_desc); +} + +static struct platform_driver cam_bist_mclk_cc_eliza_driver =3D { + .probe =3D cam_bist_mclk_cc_eliza_probe, + .driver =3D { + .name =3D "cambistmclkcc-eliza", + .of_match_table =3D cam_bist_mclk_cc_eliza_match_table, + }, +}; + +module_platform_driver(cam_bist_mclk_cc_eliza_driver); + +MODULE_DESCRIPTION("QTI CAMBISTMCLKCC Eliza Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/camcc-eliza.c b/drivers/clk/qcom/camcc-eliza.c new file mode 100644 index 0000000000000000000000000000000000000000..b96a2a58b32a78c50836410fc23= b58e6892196f0 --- /dev/null +++ b/drivers/clk/qcom/camcc-eliza.c @@ -0,0 +1,2803 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL6_OUT_ODD, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x3e, + .cal_l =3D 0x44, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd =3D { + .offset =3D 0x0, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll0_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 900.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll1_config =3D { + .l =3D 0x2e, + .cal_l =3D 0x44, + .alpha =3D 0xe000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even =3D { + .offset =3D 0x1000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll1_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll1_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 872.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x2d, + .cal_l =3D 0x44, + .alpha =3D 0x6aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll2_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 890.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x2e, + .cal_l =3D 0x44, + .alpha =3D 0x5aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even =3D { + .offset =3D 0x3000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll3_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 890.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config =3D { + .l =3D 0x2e, + .cal_l =3D 0x44, + .alpha =3D 0x5aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll4 =3D { + .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 890.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config =3D { + .l =3D 0x2e, + .cal_l =3D 0x44, + .alpha =3D 0x5aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll5 =3D { + .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even =3D { + .offset =3D 0x5000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll5_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +/* 960.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config =3D { + .l =3D 0x32, + .cal_l =3D 0x44, + .alpha =3D 0x0, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll6 =3D { + .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even =3D { + .offset =3D 0x6000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll6_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd =3D { + .offset =3D 0x6000, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll6_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL6_OUT_ODD, 4 }, + { P_CAM_CC_PLL6_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_odd.clkr.hw }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src =3D { + .cmd_rcgr =3D 0x112e8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_camnoc_rt_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src =3D { + .cmd_rcgr =3D 0x1126c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src =3D { + .cmd_rcgr =3D 0x11288, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src =3D { + .cmd_rcgr =3D 0x112a4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x11068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src =3D { + .cmd_rcgr =3D 0x111ac, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10024, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src =3D { + .cmd_rcgr =3D 0x100a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csid_clk_src =3D { + .cmd_rcgr =3D 0x112c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x100dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_0_clk_src =3D { + .cmd_rcgr =3D 0x11214, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_1_clk_src =3D { + .cmd_rcgr =3D 0x1123c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0x11150, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0x1117c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] =3D { + F(450000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src =3D { + .cmd_rcgr =3D 0x10190, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_ipe_nps_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src =3D { + .cmd_rcgr =3D 0x111d0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cre_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] =3D { + F(436000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(570000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(757000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ofe_clk_src =3D { + .cmd_rcgr =3D 0x1011c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ofe_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] =3D { + F(60000000, P_CAM_CC_PLL6_OUT_EVEN, 8, 0, 0), + F(120000000, P_CAM_CC_PLL0_OUT_EVEN, 5, 0, 0), + F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src =3D { + .cmd_rcgr =3D 0x1132c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x11380, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sleep_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x10100, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] =3D { + F(445000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(567000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(644000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_0_clk_src =3D { + .cmd_rcgr =3D 0x11018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_tfe_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] =3D { + F(445000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(567000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(644000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_1_clk_src =3D { + .cmd_rcgr =3D 0x11098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6, + .freq_tbl =3D ftbl_cam_cc_tfe_1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_clk_src", + .parent_data =3D cam_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] =3D { + F(445000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(567000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(644000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_tfe_2_clk_src =3D { + .cmd_rcgr =3D 0x11100, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_7, + .freq_tbl =3D ftbl_cam_cc_tfe_2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_clk_src", + .parent_data =3D cam_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x11364, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_8, + .freq_tbl =3D ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_xo_clk_src", + .parent_data =3D cam_cc_parent_data_8, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_cam_top_ahb_clk =3D { + .halt_reg =3D 0x113ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x113ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cam_top_fast_ahb_clk =3D { + .halt_reg =3D 0x1139c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1139c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cam_top_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk =3D { + .halt_reg =3D 0x11320, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11320, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_dcd_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_axi_clk =3D { + .halt_reg =3D 0x11310, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x11310, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x11310, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_cre_clk =3D { + .halt_reg =3D 0x111c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ipe_nps_clk =3D { + .halt_reg =3D 0x101b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ofe_anchor_clk =3D { + .halt_reg =3D 0x10158, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10158, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ofe_anchor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ofe_hdr_clk =3D { + .halt_reg =3D 0x1016c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1016c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ofe_hdr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_ofe_main_clk =3D { + .halt_reg =3D 0x10144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_axi_clk =3D { + .halt_reg =3D 0x11300, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11300, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_ife_lite_clk =3D { + .halt_reg =3D 0x11178, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11178, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_0_bayer_clk =3D { + .halt_reg =3D 0x11054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_0_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_0_main_clk =3D { + .halt_reg =3D 0x11040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_1_bayer_clk =3D { + .halt_reg =3D 0x110d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_1_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_1_main_clk =3D { + .halt_reg =3D 0x110c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_2_bayer_clk =3D { + .halt_reg =3D 0x1113c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1113c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_2_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_tfe_2_main_clk =3D { + .halt_reg =3D 0x11128, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11128, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk =3D { + .halt_reg =3D 0x11324, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11324, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk =3D { + .halt_reg =3D 0x11284, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11284, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk =3D { + .halt_reg =3D 0x112a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x112a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk =3D { + .halt_reg =3D 0x112bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x112bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk =3D { + .halt_reg =3D 0x11360, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x11360, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_core_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk =3D { + .halt_reg =3D 0x111cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk =3D { + .halt_reg =3D 0x111c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cre_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x10018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x1003c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1003c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x1005c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1005c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk =3D { + .halt_reg =3D 0x1007c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1007c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk =3D { + .halt_reg =3D 0x1009c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1009c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk =3D { + .halt_reg =3D 0x100bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi5phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk =3D { + .halt_reg =3D 0x112d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x112d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk =3D { + .halt_reg =3D 0x10020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x1001c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1001c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x10040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x10060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk =3D { + .halt_reg =3D 0x10080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk =3D { + .halt_reg =3D 0x100a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk =3D { + .halt_reg =3D 0x100c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_drv_ahb_clk =3D { + .halt_reg =3D 0x113c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x113c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_drv_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch cam_cc_drv_xo_clk =3D { + .halt_reg =3D 0x113c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x113c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_drv_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_ahb_clk =3D { + .halt_reg =3D 0x11264, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11264, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_clk =3D { + .halt_reg =3D 0x1122c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1122c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_ahb_clk =3D { + .halt_reg =3D 0x11268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_clk =3D { + .halt_reg =3D 0x11254, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11254, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk =3D { + .halt_reg =3D 0x111a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0x11168, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11168, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0x111a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0x11194, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11194, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk =3D { + .halt_reg =3D 0x101d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk =3D { + .halt_reg =3D 0x101a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk =3D { + .halt_reg =3D 0x101d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk =3D { + .halt_reg =3D 0x101bc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk =3D { + .halt_reg =3D 0x101dc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x101dc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_0_clk =3D { + .halt_reg =3D 0x111e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_1_clk =3D { + .halt_reg =3D 0x111f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x111f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_jpeg_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_ahb_clk =3D { + .halt_reg =3D 0x10118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_clk =3D { + .halt_reg =3D 0x10148, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_anchor_fast_ahb_clk =3D { + .halt_reg =3D 0x100f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_anchor_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_clk =3D { + .halt_reg =3D 0x1015c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1015c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_hdr_fast_ahb_clk =3D { + .halt_reg =3D 0x100fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_hdr_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_clk =3D { + .halt_reg =3D 0x10134, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ofe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ofe_main_fast_ahb_clk =3D { + .halt_reg =3D 0x100f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ofe_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk =3D { + .halt_reg =3D 0x11344, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11344, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x11348, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11348, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_clk =3D { + .halt_reg =3D 0x11044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x11064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_clk =3D { + .halt_reg =3D 0x11030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_0_main_fast_ahb_clk =3D { + .halt_reg =3D 0x11060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_0_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_clk =3D { + .halt_reg =3D 0x110c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x110e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_clk =3D { + .halt_reg =3D 0x110b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_1_main_fast_ahb_clk =3D { + .halt_reg =3D 0x110e0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_1_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_clk =3D { + .halt_reg =3D 0x1112c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1112c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_bayer_fast_ahb_clk =3D { + .halt_reg =3D 0x1114c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1114c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_bayer_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_clk =3D { + .halt_reg =3D 0x11118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_tfe_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tfe_2_main_fast_ahb_clk =3D { + .halt_reg =3D 0x11148, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tfe_2_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc =3D { + .gdscr =3D 0x1134c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc =3D { + .gdscr =3D 0x1017c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ipe_0_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ofe_gdsc =3D { + .gdscr =3D 0x100c8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ofe_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_tfe_0_gdsc =3D { + .gdscr =3D 0x11004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_0_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_tfe_1_gdsc =3D { + .gdscr =3D 0x11084, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_1_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_tfe_2_gdsc =3D { + .gdscr =3D 0x110ec, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_tfe_2_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_eliza_clocks[] =3D { + [CAM_CC_CAM_TOP_AHB_CLK] =3D &cam_cc_cam_top_ahb_clk.clkr, + [CAM_CC_CAM_TOP_FAST_AHB_CLK] =3D &cam_cc_cam_top_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] =3D &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_NRT_AXI_CLK] =3D &cam_cc_camnoc_nrt_axi_clk.clkr, + [CAM_CC_CAMNOC_NRT_CRE_CLK] =3D &cam_cc_camnoc_nrt_cre_clk.clkr, + [CAM_CC_CAMNOC_NRT_IPE_NPS_CLK] =3D &cam_cc_camnoc_nrt_ipe_nps_clk.clkr, + [CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK] =3D &cam_cc_camnoc_nrt_ofe_anchor_clk.= clkr, + [CAM_CC_CAMNOC_NRT_OFE_HDR_CLK] =3D &cam_cc_camnoc_nrt_ofe_hdr_clk.clkr, + [CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK] =3D &cam_cc_camnoc_nrt_ofe_main_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK] =3D &cam_cc_camnoc_rt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] =3D &cam_cc_camnoc_rt_axi_clk_src.clkr, + [CAM_CC_CAMNOC_RT_IFE_LITE_CLK] =3D &cam_cc_camnoc_rt_ife_lite_clk.clkr, + [CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK] =3D &cam_cc_camnoc_rt_tfe_0_bayer_clk.= clkr, + [CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_0_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK] =3D &cam_cc_camnoc_rt_tfe_1_bayer_clk.= clkr, + [CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_1_main_clk.cl= kr, + [CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK] =3D &cam_cc_camnoc_rt_tfe_2_bayer_clk.= clkr, + [CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK] =3D &cam_cc_camnoc_rt_tfe_2_main_clk.cl= kr, + [CAM_CC_CAMNOC_XO_CLK] =3D &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] =3D &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] =3D &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] =3D &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] =3D &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] =3D &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] =3D &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] =3D &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] =3D &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] =3D &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] =3D &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] =3D &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] =3D &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] =3D &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] =3D &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] =3D &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] =3D &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] =3D &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] =3D &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] =3D &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] =3D &cam_cc_csiphy5_clk.clkr, + [CAM_CC_DRV_AHB_CLK] =3D &cam_cc_drv_ahb_clk.clkr, + [CAM_CC_DRV_XO_CLK] =3D &cam_cc_drv_xo_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_0_AHB_CLK] =3D &cam_cc_icp_0_ahb_clk.clkr, + [CAM_CC_ICP_0_CLK] =3D &cam_cc_icp_0_clk.clkr, + [CAM_CC_ICP_0_CLK_SRC] =3D &cam_cc_icp_0_clk_src.clkr, + [CAM_CC_ICP_1_AHB_CLK] =3D &cam_cc_icp_1_ahb_clk.clkr, + [CAM_CC_ICP_1_CLK] =3D &cam_cc_icp_1_clk.clkr, + [CAM_CC_ICP_1_CLK_SRC] =3D &cam_cc_icp_1_clk_src.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] =3D &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] =3D &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] =3D &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] =3D &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] =3D &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] =3D &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] =3D &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_JPEG_0_CLK] =3D &cam_cc_jpeg_0_clk.clkr, + [CAM_CC_JPEG_1_CLK] =3D &cam_cc_jpeg_1_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] =3D &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_OFE_AHB_CLK] =3D &cam_cc_ofe_ahb_clk.clkr, + [CAM_CC_OFE_ANCHOR_CLK] =3D &cam_cc_ofe_anchor_clk.clkr, + [CAM_CC_OFE_ANCHOR_FAST_AHB_CLK] =3D &cam_cc_ofe_anchor_fast_ahb_clk.clkr, + [CAM_CC_OFE_CLK_SRC] =3D &cam_cc_ofe_clk_src.clkr, + [CAM_CC_OFE_HDR_CLK] =3D &cam_cc_ofe_hdr_clk.clkr, + [CAM_CC_OFE_HDR_FAST_AHB_CLK] =3D &cam_cc_ofe_hdr_fast_ahb_clk.clkr, + [CAM_CC_OFE_MAIN_CLK] =3D &cam_cc_ofe_main_clk.clkr, + [CAM_CC_OFE_MAIN_FAST_AHB_CLK] =3D &cam_cc_ofe_main_fast_ahb_clk.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] =3D &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] =3D &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] =3D &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] =3D &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_EVEN] =3D &cam_cc_pll2_out_even.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] =3D &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] =3D &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] =3D &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] =3D &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] =3D &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] =3D &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] =3D &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL6_OUT_ODD] =3D &cam_cc_pll6_out_odd.clkr, + [CAM_CC_QDSS_DEBUG_CLK] =3D &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] =3D &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_TFE_0_BAYER_CLK] =3D &cam_cc_tfe_0_bayer_clk.clkr, + [CAM_CC_TFE_0_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_0_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_0_CLK_SRC] =3D &cam_cc_tfe_0_clk_src.clkr, + [CAM_CC_TFE_0_MAIN_CLK] =3D &cam_cc_tfe_0_main_clk.clkr, + [CAM_CC_TFE_0_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_0_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_1_BAYER_CLK] =3D &cam_cc_tfe_1_bayer_clk.clkr, + [CAM_CC_TFE_1_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_1_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_1_CLK_SRC] =3D &cam_cc_tfe_1_clk_src.clkr, + [CAM_CC_TFE_1_MAIN_CLK] =3D &cam_cc_tfe_1_main_clk.clkr, + [CAM_CC_TFE_1_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_1_main_fast_ahb_clk.clkr, + [CAM_CC_TFE_2_BAYER_CLK] =3D &cam_cc_tfe_2_bayer_clk.clkr, + [CAM_CC_TFE_2_BAYER_FAST_AHB_CLK] =3D &cam_cc_tfe_2_bayer_fast_ahb_clk.cl= kr, + [CAM_CC_TFE_2_CLK_SRC] =3D &cam_cc_tfe_2_clk_src.clkr, + [CAM_CC_TFE_2_MAIN_CLK] =3D &cam_cc_tfe_2_main_clk.clkr, + [CAM_CC_TFE_2_MAIN_FAST_AHB_CLK] =3D &cam_cc_tfe_2_main_fast_ahb_clk.clkr, + [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_eliza_gdscs[] =3D { + [CAM_CC_IPE_0_GDSC] =3D &cam_cc_ipe_0_gdsc, + [CAM_CC_OFE_GDSC] =3D &cam_cc_ofe_gdsc, + [CAM_CC_TFE_0_GDSC] =3D &cam_cc_tfe_0_gdsc, + [CAM_CC_TFE_1_GDSC] =3D &cam_cc_tfe_1_gdsc, + [CAM_CC_TFE_2_GDSC] =3D &cam_cc_tfe_2_gdsc, + [CAM_CC_TITAN_TOP_GDSC] =3D &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_eliza_resets[] =3D { + [CAM_CC_DRV_BCR] =3D { 0x113bc }, + [CAM_CC_ICP_BCR] =3D { 0x11210 }, + [CAM_CC_IPE_0_BCR] =3D { 0x10178 }, + [CAM_CC_OFE_BCR] =3D { 0x100c4 }, + [CAM_CC_QDSS_DEBUG_BCR] =3D { 0x11328 }, + [CAM_CC_TFE_0_BCR] =3D { 0x11000 }, + [CAM_CC_TFE_1_BCR] =3D { 0x11080 }, + [CAM_CC_TFE_2_BCR] =3D { 0x110e8 }, +}; + +static struct clk_alpha_pll *cam_cc_eliza_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, +}; + +static u32 cam_cc_eliza_critical_cbcrs[] =3D { + 0x1137c, /* CAM_CC_GDSC_CLK */ + 0x11398, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_eliza_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1601c, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data cam_cc_eliza_driver_data =3D { + .alpha_plls =3D cam_cc_eliza_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_eliza_plls), + .clk_cbcrs =3D cam_cc_eliza_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_eliza_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_eliza_desc =3D { + .config =3D &cam_cc_eliza_regmap_config, + .clks =3D cam_cc_eliza_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_eliza_clocks), + .resets =3D cam_cc_eliza_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_eliza_resets), + .gdscs =3D cam_cc_eliza_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_eliza_gdscs), + .driver_data =3D &cam_cc_eliza_driver_data, +}; + +static const struct of_device_id cam_cc_eliza_match_table[] =3D { + { .compatible =3D "qcom,eliza-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_eliza_match_table); + +static int cam_cc_eliza_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_eliza_desc); +} + +static struct platform_driver cam_cc_eliza_driver =3D { + .probe =3D cam_cc_eliza_probe, + .driver =3D { + .name =3D "camcc-eliza", + .of_match_table =3D cam_cc_eliza_match_table, + }, +}; + +module_platform_driver(cam_cc_eliza_driver); + +MODULE_DESCRIPTION("QTI CAMCC Eliza Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Jun 12 17:19:54 2026 Received: from mx0a-0031df01.pphosted.com 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Das Date: Wed, 13 May 2026 20:57:42 +0530 Subject: [PATCH v4 7/7] arm64: dts: qcom: eliza: Add support for MM clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260513-eliza_mm_cc_v2-v4-7-e61b5434e8d9@oss.qualcomm.com> References: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> In-Reply-To: <20260513-eliza_mm_cc_v2-v4-0-e61b5434e8d9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue , Luca Weiss Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 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Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/eliza.dtsi | 59 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi index 4a7a0ac40ce6252a138bed06c7c190ada3ea61a3..1a47eb2a865717dde3fa0ff8266= 5eecc8ffb87e2 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3,8 +3,12 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include #include +#include #include +#include #include #include #include @@ -709,6 +713,18 @@ aggre2_noc: interconnect@1700000 { #interconnect-cells =3D <2>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,eliza-cambistmclkcc"; + reg =3D <0x0 0x01760000 0x0 0x6000>; + + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,eliza-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x7d800>; @@ -862,6 +878,23 @@ tcsr: clock-controller@1fbf000 { #reset-cells =3D <1>; }; =20 + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,eliza-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0xa000>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible =3D "qcom,eliza-lpass-ag-noc"; reg =3D <0x0 0x07e40000 0x0 0xe080>; @@ -883,6 +916,32 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells =3D <2>; }; =20 + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,eliza-videocc"; + reg =3D <0x0 0xaaf0000 0x0 0x10000>; + + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ade0000 { + compatible =3D "qcom,eliza-camcc"; + reg =3D <0x0 0x0ade0000 0x0 0x20000>; + + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,eliza-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x40000>, --=20 2.34.1