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VorgV7GcvFGoC11XqMnt8s+0avuuFUFBPgtut+76mdLFENVyy8fy4JT89VpNxwBs5PfdSZWix 6W4Sqf86y26oTHs7J/7SnrjyrFVMjjObl8B9P5V/Bj5yKjxhRm3/OvNnt/NtAlNIWGVA2vkEI oon+zIRCw0iidLzTIVQ49V715PVUyz74d3v47n7K57cCVb1mLU4pB1X4evAiR1F28AiPHi84/ ct4pANSnG9DBbGQxl2/hrTUeEofHsMsq4nWgc+bSPXRlfD6SGgOxApHrHwH38QaeyHH/qa+pH gc+JIN+uC/hv96VyLh0cwBBst8S5WkILMQnQTBCLTDJQ//ay8WiozBeGeq7KAvwtxgHPYtiGz ga04alxSeipjLVwyfAEaLqYim8g8QywpLoGy+0YqgR/lqRy4DL3YV5FS7VYKfu4b4osRvd8K6 gzcOZLB6FlEL1gQALsYmuZWvtkTTMmb4CHTTMPyLnpFDO4SaZNkp72o7pzLlxySFnQOQHKM/x 7+7PSAtUFR6IK3Cseo9Nrl6lBs3lsztnxoWF4qUskYfKuUYAT4VHFZQ+deaaWeqX2UA2xUvC4 mLnWxolpABA8AFw== Content-Type: text/plain; charset="utf-8" The Realtek IRQ controller has two important registers that are used by the driver in several places - GIMR: global interrupt mask register - IRR: Interrupt routing registers The usage of these registers is very inconsistent. GIMR is addressed directly while IRR has a helper that needs an macro as an input. Harmonize this by providing consistent helpers that improve code readability. Signed-off-by: Markus Stockhausen --- drivers/irqchip/irq-realtek-rtl.c | 48 +++++++++++++++++++------------ 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 942c1f8c363d..7fb8dd4c5670 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -37,10 +37,29 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static void write_irr(void __iomem *irr0, int idx, u32 value) +static inline void enable_gimr(int hw_irq) { - unsigned int offset =3D IRR_OFFSET(idx); - unsigned int shift =3D IRR_SHIFT(idx); + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr |=3D BIT(hw_irq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static inline void disable_gimr(int hwirq) +{ + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr &=3D ~BIT(hwirq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static void write_irr(int hw_irq, u32 value) +{ + void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + unsigned int offset =3D IRR_OFFSET(hw_irq); + unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; =20 irr =3D readl(irr0 + offset) & ~(0xf << shift); @@ -51,28 +70,18 @@ static void write_irr(void __iomem *irr0, int idx, u32 = value) static void realtek_ictl_unmask_irq(struct irq_data *i) { unsigned long flags; - u32 value; =20 raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value |=3D BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - + enable_gimr(i->hwirq); raw_spin_unlock_irqrestore(&irq_lock, flags); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { unsigned long flags; - u32 value; =20 raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value &=3D ~BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - + disable_gimr(i->hwirq); raw_spin_unlock_irqrestore(&irq_lock, flags); } =20 @@ -89,7 +98,7 @@ static int intc_map(struct irq_domain *d, unsigned int ir= q, irq_hw_number_t hw) irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 raw_spin_lock_irqsave(&irq_lock, flags); - write_irr(REG(RTL_ICTL_IRR0), hw, 1); + write_irr(hw, 1); raw_spin_unlock_irqrestore(&irq_lock, flags); =20 return 0; @@ -135,9 +144,10 @@ static int __init realtek_rtl_of_init(struct device_no= de *node, struct device_no return -ENXIO; =20 /* Disable all cascaded interrupts and clear routing */ - writel(0, REG(RTL_ICTL_GIMR)); - for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) - write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); + for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { + disable_gimr(soc_irq); + write_irr(soc_irq, 0); + } =20 if (WARN_ON(!of_irq_count(node))) { /* --=20 2.54.0 From nobody Fri Jun 12 20:23:29 2026 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate 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tj3E8KFzdC8Tcl60UsaR65q8w38Zd5ZuUNl+6SmxNqQUfobE7XDTl1a7EtYJZYfCXWNNBTQhK pCh83q2pbqe7sAwOUWBwKAst2SVX9qfqPY2ro1fsZzxnZxR7VB5waEZRvh75rKE2jZwi6+67p fmQjLDq9Bq/6eaOsrfWyRcU6MVJs6d8UvzQnRerJmK60lYDYEQKJUjC04XrUnx4Y1rUzp9QK+ 6R2S7xRlplollJaOyHx2UXI+W6KLc4na692wllrS2KVxp6LPUepFt9pm+cxLy2OTuYz4/smnr O5OKETK/fLm/7JaxzWGJ5HG8OBNWPKEiqDcf9Q4hc2onjeFadKKboxgdue6JTmd27Zx+j3ta2 55ferg== Content-Type: text/plain; charset="utf-8" The Realtek IRQ driver currently supports only single core systems. So the higher end devices like RTL839x and RTL930x with dual VPEs must be driven with NR_CPU=3D1. Enhance the driver to support multicore (dual VPE) systems. For this: - Extend the register map for multiple cores - Search for multiple CPU cores in the devicetree - Improve the register helpers to support multiple cores - Add an affinity setter - Enhance the IRQ handler for multiple cores Signed-off-by: Markus Stockhausen --- drivers/irqchip/irq-realtek-rtl.c | 91 +++++++++++++++++++++++-------- 1 file changed, 69 insertions(+), 22 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 7fb8dd4c5670..e0e07074bf6f 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -23,10 +23,11 @@ =20 #define RTL_ICTL_NUM_INPUTS 32 =20 -#define REG(x) (realtek_ictl_base + x) +#define REG(cpu, x) (realtek_ictl_base[cpu] + x) =20 static DEFINE_RAW_SPINLOCK(irq_lock); -static void __iomem *realtek_ictl_base; +static void __iomem *realtek_ictl_base[NR_CPUS]; +static cpumask_t realtek_ictl_cpu_configurable; =20 /* * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numberi= ng, @@ -37,27 +38,27 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static inline void enable_gimr(int hw_irq) +static inline void enable_gimr(int cpu, int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr |=3D BIT(hw_irq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static inline void disable_gimr(int hwirq) +static inline void disable_gimr(int cpu, int hwirq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr &=3D ~BIT(hwirq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static void write_irr(int hw_irq, u32 value) +static void write_irr(int cpu, int hw_irq, u32 value) { - void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + void __iomem *irr0 =3D REG(cpu, RTL_ICTL_IRR0); unsigned int offset =3D IRR_OFFSET(hw_irq); unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; @@ -70,35 +71,73 @@ static void write_irr(int hw_irq, u32 value) static void realtek_ictl_unmask_irq(struct irq_data *i) { unsigned long flags; + cpumask_t cpus; + int cpu; + + cpumask_and(&cpus, &realtek_ictl_cpu_configurable, + irq_data_get_effective_affinity_mask(i)); =20 raw_spin_lock_irqsave(&irq_lock, flags); - enable_gimr(i->hwirq); + for_each_cpu(cpu, &cpus) + enable_gimr(cpu, i->hwirq); raw_spin_unlock_irqrestore(&irq_lock, flags); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { unsigned long flags; + int cpu; =20 raw_spin_lock_irqsave(&irq_lock, flags); - disable_gimr(i->hwirq); + for_each_cpu(cpu, &realtek_ictl_cpu_configurable) + disable_gimr(cpu, i->hwirq); raw_spin_unlock_irqrestore(&irq_lock, flags); } =20 +static int realtek_ictl_irq_affinity(struct irq_data *i, + const struct cpumask *dest, + bool force) +{ + cpumask_t cpu_configure; + cpumask_t cpu_disable; + cpumask_t cpu_enable; + unsigned long flags; + int cpu; + + cpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configura= ble); + cpumask_and(&cpu_enable, &cpu_configure, dest); + cpumask_andnot(&cpu_disable, &cpu_configure, dest); + + raw_spin_lock_irqsave(&irq_lock, flags); + for_each_cpu(cpu, &cpu_disable) + disable_gimr(cpu, i->hwirq); + for_each_cpu(cpu, &cpu_enable) + if (!irqd_irq_masked(i)) + enable_gimr(cpu, i->hwirq); + raw_spin_unlock_irqrestore(&irq_lock, flags); + + irq_data_update_effective_affinity(i, &cpu_enable); + + return IRQ_SET_MASK_OK; +} + static struct irq_chip realtek_ictl_irq =3D { .name =3D "realtek-rtl-intc", .irq_mask =3D realtek_ictl_mask_irq, .irq_unmask =3D realtek_ictl_unmask_irq, + .irq_set_affinity =3D realtek_ictl_irq_affinity, }; =20 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { unsigned long flags; + int cpu; =20 irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 raw_spin_lock_irqsave(&irq_lock, flags); - write_irr(hw, 1); + for_each_cpu(cpu, &realtek_ictl_cpu_configurable) + write_irr(cpu, hw, 1); raw_spin_unlock_irqrestore(&irq_lock, flags); =20 return 0; @@ -112,12 +151,13 @@ static const struct irq_domain_ops irq_domain_ops =3D= { static void realtek_irq_dispatch(struct irq_desc *desc) { struct irq_chip *chip =3D irq_desc_get_chip(desc); + int cpu =3D smp_processor_id(); struct irq_domain *domain; unsigned long pending; unsigned int soc_int; =20 chained_irq_enter(chip, desc); - pending =3D readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); + pending =3D readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR= )); =20 if (unlikely(!pending)) { spurious_interrupt(); @@ -139,16 +179,23 @@ static int __init realtek_rtl_of_init(struct device_n= ode *node, struct device_no unsigned int soc_irq; int parent_irq; =20 - realtek_ictl_base =3D of_iomap(node, 0); - if (!realtek_ictl_base) - return -ENXIO; - - /* Disable all cascaded interrupts and clear routing */ - for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { - disable_gimr(soc_irq); - write_irr(soc_irq, 0); + cpumask_clear(&realtek_ictl_cpu_configurable); + + for (int cpu =3D 0; cpu < NR_CPUS; cpu++) { + realtek_ictl_base[cpu] =3D of_iomap(node, cpu); + if (realtek_ictl_base[cpu]) { + cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable); + /* Disable all cascaded interrupts and clear routing */ + for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { + disable_gimr(cpu, soc_irq); + write_irr(cpu, soc_irq, 0); + } + } } =20 + if (cpumask_empty(&realtek_ictl_cpu_configurable)) + return -ENXIO; + if (WARN_ON(!of_irq_count(node))) { /* * If DT contains no parent interrupts, assume MIPS CPU IRQ 2 --=20 2.54.0