From nobody Fri Jun 12 21:12:48 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07E2E3C37BD for ; Tue, 12 May 2026 15:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600459; cv=none; b=VlQVn7HczwfQKGtOt2eLtRM2EyJiKKmrGcSdF9OFg66yoj8KExp9gOo3tg2wSTX5vZrgHMUREn4R57QD+mrqbtOBYgQ9XkZVR485gFPwFpesVOOrbO3P3NtkjLRHZIxYXLb/7juXkBcOwqeUByNaj7Ozd+PiH/HKkcawhAThEig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600459; c=relaxed/simple; bh=6q4AW2ZPhngm1iHgc2CJnuk6/CZOBqwKCTS34cok4Es=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Vmt03n+IQxDaEcNLgB7n+/eQ3GIy+6BbOFhAEdh5ZoDhbQbCKJ8N4whrZPnKufXdBEQmEKvDQ7rkM9f/0MxNb1ndDvcQizj6OKQebImBrFcnk7/t+iNPXE8sNsh55fsZXo7WVGKS7dbKJZ35QXaCAj/cKg6yFJUtNfdhUVcQiuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TaAlQ9B2; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TaAlQ9B2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778600458; x=1810136458; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6q4AW2ZPhngm1iHgc2CJnuk6/CZOBqwKCTS34cok4Es=; b=TaAlQ9B2h9MZBMLz5fNGCWRwhpMI89zed4NEZ51xTUzgImcqeyIpKfYW VqdIwfQfaoLAuZzS3vSV+3/R8ceUno10KBh9m6SBlLDSGaLGvB0eqEwrE KsmmDu+abZmiwB0r8yKFbreJaYCJQmTtEvFY6HyqH71sA55JriP4MgNg4 t9N4ZxYIJREIQotFiijq8jo0RyHd7JaqHzKsfbMhnOM7fcuSwV9TY0yxy p8Fbwo7tFgFlz2aLAx1Rj/GUq1z+JfnNOEUPB/zE9RZp51x/Dl3zhLKQh Omgo3pksql2Pqndjocd2+RDcBU7OkzWp66FwmYTB8+edWA++12A7FBJOF Q==; X-CSE-ConnectionGUID: LRaPHBckQPOjgLj0q4+OEQ== X-CSE-MsgGUID: pTHZI5dDRYSkA+k7TekVgg== X-IronPort-AV: E=McAfee;i="6800,10657,11784"; a="83366618" X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="83366618" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2026 08:40:57 -0700 X-CSE-ConnectionGUID: 4S9EwR5EQUGjd35MdEJ+4w== X-CSE-MsgGUID: OwRHbSiiQIyRmsgGVzNReQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="233506324" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.22]) by fmviesa010.fm.intel.com with ESMTP; 12 May 2026 08:40:55 -0700 From: Xiaoyao Li To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen Cc: "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH] x86/microcode: Fix comment in microcode_loader_disabled() Date: Tue, 12 May 2026 23:27:54 +0800 Message-ID: <20260512152754.671760-1-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The code in microcode_loader_disabled() actually checks for the bit 31 in CPUID[1]:ECX being set. Update the comment to match the code. No functional change intended. Signed-off-by: Xiaoyao Li --- arch/x86/kernel/cpu/microcode/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 651202e6fefb..68a1a893246c 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -126,7 +126,7 @@ bool __init microcode_loader_disabled(void) } =20 /* - * 2) Bit 31 in CPUID[1]:ECX is clear + * 2) Bit 31 in CPUID[1]:ECX is set * The bit is reserved for hypervisor use. This is still not * completely accurate as XEN PV guests don't see that CPUID bit * set, but that's good enough as they don't land on the BSP base-commit: 5d6919055dec134de3c40167a490f33c74c12581 --=20 2.43.0