From nobody Fri Jun 12 22:48:11 2026 Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E26BA379C28; Tue, 12 May 2026 07:42:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778571729; cv=none; b=CBIwQzXTF5zFJ5unbwcmUhIWA1CPINuf/iIH2HIGs2OpGJCpaCoeGCK1mVaNhrSz//qP9nurkNdoeaxXJpy+3qWKz4rOyJmBOGx6eKZYMKcT9ezSOxyfGCgD/RH4cg0ay355zcMQXjz3MihG4/Yqu4su8j4dM9QQeOK/CqmxWdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778571729; c=relaxed/simple; bh=S1KAa2hsg2t5OftD1qgj3EN+hxREsBlG2ozkwRkJzto=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G7SNfU+uBPOiC80E5/QrwDDndh6EtuS8H6XLRS+Jpoc6I1LQj3aSBmmCwT+Ck8VahUk+QLCtmaqGhs5CduOM+oxL1l5+a95ZqtyAwIeZIAOuurg2lUlxS2/xgGnCqExM8JZRHw/I3fizONSFVW7dgc6zhaKMulg/91FdYg2gtdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=Y9GUNCON; arc=none smtp.client-ip=115.124.30.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="Y9GUNCON" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778571715; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=i04ZuxIi3jt4m8VWianwNO2YFQpZ5BInIfUiKWtaoro=; b=Y9GUNCONnLHKa7y/tKpkzm8dCjA0cu1wlRnPZXcVPeJ2u8VkuFheFi5ZdszceNBovGGOT6r65F7QikU5lf6uoGarlOBp3NW8PcSh3RRah63qoHBfoJBVym/r8FuA0ZaK6+rEQihrMX5mACpbfXcG/rHYv/WNlbxUuVNdNbdXb50= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam011083073210;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=25;SR=0;TI=SMTPD_---0X2puQMt_1778571712; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2puQMt_1778571712 cluster:ay36) by smtp.aliyun-inc.com; Tue, 12 May 2026 15:41:53 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com, nutty.liu@hotmail.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [PATCH v4 1/2] iommu/riscv: Advertise Svpbmt support to generic page table Date: Tue, 12 May 2026 15:41:41 +0800 Message-Id: <20260512074142.16356-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> References: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu The RISC-V IOMMU can optionally support Svpbmt page-based memory types in its page table format. When present,the generic page table code can use this capability to encode memory attributes (e.g. MMIO vs normal memory) in PTEs. Reviewed-by: Jason Gunthorpe Reviewed-by: Anup Patel Reviewed-by: Guo Ren Reviewed-by: Nutty Liu Reviewed-by: Kevin Tian Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 2 ++ include/linux/generic_pt/common.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index a31f50bbad35..6c324f9fdc53 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1268,6 +1268,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_= domain(struct device *dev) cfg.common.features =3D BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_RISCV_SVNAPOT_64K); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) + cfg.common.features |=3D BIT(PT_FEAT_RISCV_SVPBMT); domain->riscvpt.iommu.nid =3D dev_to_node(iommu->dev); domain->domain.ops =3D &riscv_iommu_paging_domain_ops; =20 diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/c= ommon.h index fc5d0b5edadc..2683e5b38998 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -188,6 +188,10 @@ enum { * Support the 64k contiguous page size following the Svnapot extension. */ PT_FEAT_RISCV_SVNAPOT_64K =3D PT_FEAT_FMT_START, + /* + * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs. + */ + PT_FEAT_RISCV_SVPBMT, =20 }; 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Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2puQNT_1778571714 cluster:ay36) by smtp.aliyun-inc.com; Tue, 12 May 2026 15:41:55 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com, nutty.liu@hotmail.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [PATCH v4 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits Date: Tue, 12 May 2026 15:41:42 +0800 Message-Id: <20260512074142.16356-3-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> References: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu When the RISC-V IOMMU page table format support Svpbmt, PBMT provides a way to tag mappings with page-based memory types. Encode memory type via PBMT in RISC-V IOMMU PTEs: - IOMMU_MMIO -> PBMT=3DIO - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=3DNC - otherwise -> PBMT=3DNormal (PBMT=3D0) Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. Reviewed-by: Jason Gunthorpe Reviewed-by: Anup Patel Reviewed-by: Guo Ren Reviewed-by: Nutty Liu Reviewed-by: Kevin Tian Signed-off-by: Fangyu Yu --- drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_p= t/fmt/riscv.h index a7fef6266a36..ae9a76514416 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -64,6 +64,8 @@ enum { RISCVPT_PPN64 =3D GENMASK_ULL(53, 10), RISCVPT_PPN64_64K =3D GENMASK_ULL(53, 14), RISCVPT_PBMT =3D GENMASK_ULL(62, 61), + RISCVPT_NC =3D BIT_ULL(61), + RISCVPT_IO =3D BIT_ULL(62), RISCVPT_N =3D BIT_ULL(63), =20 /* Svnapot encodings for ppn[0] */ @@ -201,7 +203,8 @@ static inline void riscvpt_attr_from_entry(const struct= pt_state *pts, { attrs->descriptor_bits =3D pts->entry & (RISCVPT_R | RISCVPT_W | RISCVPT_X | RISCVPT_U | - RISCVPT_G | RISCVPT_A | RISCVPT_D); + RISCVPT_G | RISCVPT_A | RISCVPT_D | RISCVPT_NC | + RISCVPT_IO); } #define pt_attr_from_entry riscvpt_attr_from_entry =20 @@ -237,6 +240,12 @@ static inline int riscvpt_iommu_set_prot(struct pt_com= mon *common, pte |=3D RISCVPT_R; if (!(iommu_prot & IOMMU_NOEXEC)) pte |=3D RISCVPT_X; + if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { + if (iommu_prot & IOMMU_MMIO) + pte |=3D RISCVPT_IO; + else if (!(iommu_prot & IOMMU_CACHE)) + pte |=3D RISCVPT_NC; + } =20 /* Caller must specify a supported combination of flags */ if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) =3D=3D 0)) --=20 2.50.1