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charset="utf-8" According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the Common Block Signals section selects the reference clock source connected to the PHY pads. Per the specification, any change to this input must be followed by a PHY reset assertion to take effect. Move the REF_USE_PAD configuration before the PHY reset toggle to comply with the required initialization sequence. Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe") Cc: Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 1034ac5c5f5c1..c57f18d9e4ffa 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -137,6 +137,7 @@ struct imx_pcie_drvdata { const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; + int (*init_pre_reset)(struct imx_pcie *pcie); int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); @@ -247,6 +248,24 @@ static unsigned int imx_pcie_grp_offset(const struct i= mx_pcie *imx_pcie) return imx_pcie->controller_id =3D=3D 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } =20 +static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie) +{ + bool ext =3D imx_pcie->enable_ext_refclk; + + /* + * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is + * used to select reference clock connected to a pair of pads. + * + * Any change in this input must be followed by phy_reset assertion. + */ + + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_USE_PAD, + ext ? IMX95_PCIE_REF_USE_PAD : 0); + + return 0; +} + static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { bool ext =3D imx_pcie->enable_ext_refclk; @@ -269,9 +288,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pci= e) IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); =20 - regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL, - IMX95_PCIE_REF_USE_PAD, - ext ? IMX95_PCIE_REF_USE_PAD : 0); regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_REF_CLKEN, ext ? 0 : IMX95_PCIE_REF_CLKEN); @@ -1251,6 +1267,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) pp->bridge->disable_device =3D imx_pcie_disable_device; } =20 + if (imx_pcie->drvdata->init_pre_reset) + imx_pcie->drvdata->init_pre_reset(imx_pcie); + imx_pcie_assert_core_reset(imx_pcie); imx_pcie_assert_perst(imx_pcie, true); =20 @@ -1961,6 +1980,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_mask[0] =3D IMX95_PCIE_DEVICE_TYPE, .core_reset =3D imx95_pcie_core_reset, .init_phy =3D imx95_pcie_init_phy, + .init_pre_reset =3D imx95_pcie_init_pre_reset, .wait_pll_lock =3D imx95_pcie_wait_for_phy_pll_lock, .enable_ref_clk =3D imx95_pcie_enable_ref_clk, .clr_clkreq_override =3D imx95_pcie_clr_clkreq_override, @@ -2016,6 +2036,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .ltssm_mask =3D IMX95_PCIE_LTSSM_EN, .mode_off[0] =3D IMX95_PE0_GEN_CTRL_1, .mode_mask[0] =3D IMX95_PCIE_DEVICE_TYPE, + .init_pre_reset =3D imx95_pcie_init_pre_reset, .init_phy =3D imx95_pcie_init_phy, .core_reset =3D imx95_pcie_core_reset, .wait_pll_lock =3D imx95_pcie_wait_for_phy_pll_lock, base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83 --=20 2.37.1 From nobody Tue May 26 04:51:42 2026 Received: from DUZPR83CU001.outbound.protection.outlook.com (mail-northeuropeazon11012052.outbound.protection.outlook.com [52.101.66.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B989F9D9; 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charset="utf-8" According to the PHY Databook Common Block Signals section, the ref_clk_en signal must remain de-asserted until the reference clock is running at the appropriate frequency. Once the clock is stable, ref_clk_en can be asserted. For lower power states where the reference clock to the PHY is disabled, ref_clk_en should also be de-asserted. Move the ref_clk_en bit manipulation into imx95_pcie_enable_ref_clk() to ensure the reference clock stabilizes before ref_clk_en is asserted and before the PHY reset is de-asserted. This aligns with the timing requirements specified in the PHY documentation. Fixes: d8574ce57d76 ("PCI: imx6: Add external reference clock input mode su= pport") Cc: Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 40 +++++++++++++++++++-------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index c57f18d9e4ffa..c3e623aa18bc2 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -268,8 +268,6 @@ static int imx95_pcie_init_pre_reset(struct imx_pcie *i= mx_pcie) =20 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { - bool ext =3D imx_pcie->enable_ext_refclk; - /* * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready * Through Beacon or PERST# De-assertion @@ -288,10 +286,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pc= ie) IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); =20 - regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, - IMX95_PCIE_REF_CLKEN, - ext ? 0 : IMX95_PCIE_REF_CLKEN); - return 0; } =20 @@ -740,7 +734,29 @@ static void imx95_pcie_clkreq_override(struct imx_pcie= *imx_pcie, bool enable) =20 static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enabl= e) { + bool ext =3D imx_pcie->enable_ext_refclk; + imx95_pcie_clkreq_override(imx_pcie, enable); + /* + * The ref_clk_en signal must remain de-asserted until the + * reference clock is running at appropriate frequency, at which + * point this bit can be asserted. For lower power states where + * the reference clock to the PHY is disabled, it may also be + * de-asserted. + * +------------------- -+--------+----------------+ + * | External clock mode | Enable | PCIE_REF_CLKEN | + * +---------------------+--------+----------------+ + * | TRUE | X | 1b'0 | + * +---------------------+--------+----------------+ + * | FALSE | TRUE | 1b'1 | + * +---------------------+--------+----------------+ + * | FALSE | FALSE | 1b'0 | + * +---------------------+--------+----------------+ + */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, + IMX95_PCIE_REF_CLKEN, + ext || !enable ? 0 : IMX95_PCIE_REF_CLKEN); + return 0; } =20 @@ -1262,6 +1278,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } =20 + ret =3D imx_pcie_clk_enable(imx_pcie); + if (ret) { + dev_err(dev, "unable to enable pcie clocks: %d\n", ret); + goto err_reg_disable; + } + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { pp->bridge->enable_device =3D imx_pcie_enable_device; pp->bridge->disable_device =3D imx_pcie_disable_device; @@ -1278,12 +1300,6 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) =20 imx_pcie_configure_type(imx_pcie); =20 - ret =3D imx_pcie_clk_enable(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clocks: %d\n", ret); - goto err_reg_disable; - } - if (imx_pcie->phy) { ret =3D phy_init(imx_pcie->phy); if (ret) { --=20 2.37.1