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Miller" , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: crypto: qcom,ice: Add sa8255p support Date: Mon, 11 May 2026 20:37:48 -0700 Message-Id: <20260512033750.3393050-2-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> References: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDAzMCBTYWx0ZWRfX3u1fBKRqrQ/2 msEbbyJkau38Vxe0+YtJzb8+/WDq+rsH8f5LWQzW8nC0N6Kn4Vl64scg7Nl8fXbky3CtDGBGQKl O0h2qQPCvT3YA3w379D//hH6AEelDIHo6XWJoRNyRBcfjTASXnJeI2zHibo4WV80nezyTIznLEE rbyJ/ZTb207Dp48+/rSWo/VeHG/qeajxQHCaIxpCQtQsaa67ggrrcQwxn16iwrB3TniauPrG454 /S91ysomF2HjGhPkpnUSBENdP3W3imvZ/SGStaT5DGDfoySPA94KJk4N66bFF6119I8h7oWzSCM UpWZZcfMzvHeiP4ijMFbsZu7/LsSAJvVKP5R2KbrGAiYOizYg8QUBBfWPRbegd8vCkR4sVg+qBA UpbCjlHKYkl8AWXdbZPvqULMfMeeTD6QQ5+2RvX+TUKs9ek4b9NSsZYQxdOd+BBHH5tDH1RMq3Q RicvhugvX/Jw+Huswlw== X-Authority-Analysis: v=2.4 cv=Kvp9H2WN c=1 sm=1 tr=0 ts=6a02a095 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=UuHxjPGgWbCNvu6MkpoA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: 3CLjaOF-N9iV0rEIIdspVI-nAnQ9-Kxp X-Proofpoint-GUID: 3CLjaOF-N9iV0rEIIdspVI-nAnQ9-Kxp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120030 Content-Type: text/plain; charset="utf-8" On sa8255p, resources such as PHY, clocks, regulators, and resets are managed by remote firmware via the SCMI power protocol. As a result, the ICE driver cannot directly access clocks and must instead use power-domains to request resource configuration. Add the qcom,sa8255p-inline-crypto-engine compatible string and make clocks optional for platforms that use power-domains instead. Signed-off-by: Linlin Zhang --- .../crypto/qcom,inline-crypto-engine.yaml | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-en= gine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-eng= ine.yaml index 876bf90ed96e..4e7d9111d0eb 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml @@ -17,6 +17,7 @@ properties: - qcom,kaanapali-inline-crypto-engine - qcom,milos-inline-crypto-engine - qcom,qcs8300-inline-crypto-engine + - qcom,sa8255p-inline-crypto-engine - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine @@ -32,6 +33,9 @@ properties: clocks: maxItems: 1 =20 + power-domains: + maxItems: 1 + operating-points-v2: true =20 opp-table: @@ -40,7 +44,20 @@ properties: required: - compatible - reg - - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8255p-inline-crypto-engine + then: + required: + - power-domains + else: + required: + - clocks =20 additionalProperties: false =20 @@ -75,4 +92,12 @@ examples: }; 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Miller" , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Deepti Jaggi Subject: [PATCH v2 2/3] soc: qcom: ice: Enable PM runtime for ICE driver Date: Mon, 11 May 2026 20:37:49 -0700 Message-Id: <20260512033750.3393050-3-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> References: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDAzMCBTYWx0ZWRfX/idEAYdW5FUP D3c6jT5TaLKiI57iRZZaGPhcRUUYPn+uN9Q5VPBTfcRe0G2B0+Lg0tZlis8AZ/3skLY+Sn4O/Be 51pEIYb/kr5R6yOTaeRcR+7IbaaZIuEd6WpqcZ1GgFbObpzmnKHjc0vPDlgMALOBxOcs9i4b+5g +6P64gNDl7lDqr+4heXdS0YZBERCHNe1eotV1wl0n4s3TaNblHaNEoBRCbWVGmyDfGvxQ8QdM3x BtIlXcTSFfRyjedBPaGJVomDRzj4qY+LgAtJoIjbw0zhMx2kp0Y5XfkegZcukquGbJ2b8TsBuH8 DEQKmfiaN04RszV5RRdqgh0XIyf3evX7BqnYUav047v7FSlnionjBY9lpNoiZ6ltr9sPLxWFUme iVSQ2xG+4KpPrIpY48IyNK6/Bqn5f2GcmBgk6SVfprLVx8XJ0KtiQN11QdkGVe1eR8UidGWU+L0 xWITDheWT5xD5+Wrzgw== X-Authority-Analysis: v=2.4 cv=Kvp9H2WN c=1 sm=1 tr=0 ts=6a02a096 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=7JBRkwD79zxFga_vYKgA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: n4ltsEc8gpSd8Z8nBVUg_Z6XzTbiUR9L X-Proofpoint-GUID: n4ltsEc8gpSd8Z8nBVUg_Z6XzTbiUR9L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120030 Content-Type: text/plain; charset="utf-8" The QCOM ICE driver manages the ICE core clock through direct calls to clk_prepare_enable() and clk_disable_unprepare(), which limits integration with platforms that rely on firmware-managed resources or platform-specific power management mechanisms. Replace direct clock management with runtime PM support by moving clock enable and disable into runtime PM callbacks. Use pm_runtime_resume_and_get() and pm_runtime_put_sync() in qcom_ice_resume() and qcom_ice_suspend() to drive power state transitions, and enable runtime PM in qcom_ice_probe(). Reviewed-by: Neeraj Soni Reviewed-by: Deepti Jaggi Signed-off-by: Linlin Zhang --- drivers/soc/qcom/ice.c | 58 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cad..6f9d679b530c 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -310,8 +311,8 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev =3D ice->dev; int err; =20 - err =3D clk_prepare_enable(ice->core_clk); - if (err) { + err =3D pm_runtime_resume_and_get(dev); + if (err < 0) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; @@ -323,7 +324,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); =20 int qcom_ice_suspend(struct qcom_ice *ice) { - clk_disable_unprepare(ice->core_clk); + pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete =3D false; =20 return 0; @@ -716,24 +717,69 @@ EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get); =20 static int qcom_ice_probe(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; struct qcom_ice *engine; void __iomem *base; + int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) { - dev_warn(&pdev->dev, "ICE registers not found\n"); + dev_warn(dev, "ICE registers not found\n"); return PTR_ERR(base); } =20 - engine =3D qcom_ice_create(&pdev->dev, base); + engine =3D qcom_ice_create(dev, base); if (IS_ERR(engine)) return PTR_ERR(engine); =20 platform_set_drvdata(pdev, engine); =20 + ret =3D devm_pm_runtime_enable(dev); + if (ret) { + dev_warn(dev, "Enable runtime PM failed, ret: %d\n", ret); + return ret; + } + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_warn(dev, "Runtime PM fails to resume, ret: %d\n", ret); + return ret; + } + return 0; } =20 +static void qcom_ice_remove(struct platform_device *pdev) +{ + pm_runtime_put_sync(&pdev->dev); +} + +static int ice_runtime_resume(struct device *dev) +{ + struct qcom_ice *ice =3D dev_get_drvdata(dev); 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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f8859eb4b7sm16730109eec.2.2026.05.11.20.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 20:37:57 -0700 (PDT) From: Linlin Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Herbert Xu , "David S . Miller" , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Deepti Jaggi Subject: [PATCH v2 3/3] soc: qcom: ice: Add SCMI support for sa8255p based targets Date: Mon, 11 May 2026 20:37:50 -0700 Message-Id: <20260512033750.3393050-4-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> References: <20260512033750.3393050-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PN0/P/qC c=1 sm=1 tr=0 ts=6a02a097 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=SaV-z_UyVCyeOftNReQA:9 a=scEy_gLbYbu1JhEsrz4S:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: zH6Mt7734kYArYjRLJNKmuNpIZ7ZDXoC X-Proofpoint-ORIG-GUID: zH6Mt7734kYArYjRLJNKmuNpIZ7ZDXoC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDAzMCBTYWx0ZWRfX1NVj4Wpo0QNW 14CIEHO+d4B/a7Msww43BYsex1W6R/3TKBT1zF0rAcT+JyOvSIMBjT3IDJvg0YO6qPP9q232pPF KTo1hfBSnjcEmwplPD7C7JMq6TnY4MuzG9c07ZZPp7ZlX5YVYFEulS9vY2v7p414XOywyGOgPel ycrsQvKCWBNZ+Z5Ag7R431jw3wRwfhv26DxIrEM+jgxGXrpu8xcDsV7CPsEP4LeA+wFxgmK7qQo gLFceBzVFz0TLOH9DeEfw1JoVDSei93xVy++VTCUToI4drtnY7aoxfUsJRkbKk/RQ6WHUfn3ac/ yU7v4/M1oCiRzCp6MvYba0pFYlYRlTHPihg6XYc3P7PFXV/glCiETNMAeobwg8wJxLk/mfFwwJ8 C9uSOk/LJKMBMI9zcKcUHfOg0e8uMya9ONQTSo6pcLOeslRZMDjTioQuxkXb3tzlms4ntGhy7K4 HW6/KEySzAYWzw1rTTg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120030 Content-Type: text/plain; charset="utf-8" The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages ICE clock, with a power domain set for ICE clock. The driver uses runtime PM framework APIs to request power on/off status of the clock. Reviewed-by: Neeraj Soni Reviewed-by: Deepti Jaggi Signed-off-by: Linlin Zhang --- drivers/soc/qcom/ice.c | 64 ++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 6f9d679b530c..cf185a6e1973 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -68,6 +68,10 @@ union crypto_cfg { }; }; =20 +struct engine_desc { + bool fw_managed; +}; + /* QCOM ICE HWKM (Hardware Key Manager) registers */ =20 #define HWKM_OFFSET 0x8000 @@ -554,6 +558,7 @@ static struct qcom_ice *qcom_ice_create(struct device *= dev, void __iomem *base) { struct qcom_ice *engine; + const struct engine_desc *engine_cfg =3D NULL; =20 if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -570,20 +575,23 @@ static struct qcom_ice *qcom_ice_create(struct device= *dev, engine->dev =3D dev; engine->base =3D base; =20 - /* - * Legacy DT binding uses different clk names for each consumer, - * so lets try those first. If none of those are a match, it means - * the we only have one clock and it is part of the dedicated DT node. - * Also, enable the clock before we check what HW version the driver - * supports. - */ - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice_core_clk"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice"); - if (!engine->core_clk) - engine->core_clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(engine->core_clk)) - return ERR_CAST(engine->core_clk); + engine_cfg =3D device_get_match_data(dev); + if (!engine_cfg || !engine_cfg->fw_managed) { + /* + * Legacy DT binding uses different clk names for each consumer, + * so lets try those first. If none of those are a match, it means + * the we only have one clock and it is part of the dedicated DT node. + * Also, enable the clock before we check what HW version the driver + * supports. + */ + engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice_core_clk"); + if (!engine->core_clk) + engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + } =20 if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -756,13 +764,17 @@ static void qcom_ice_remove(struct platform_device *p= dev) =20 static int ice_runtime_resume(struct device *dev) { - struct qcom_ice *ice =3D dev_get_drvdata(dev); + struct engine_desc *engine_cfg =3D device_get_match_data(dev); int err =3D 0; =20 - err =3D clk_prepare_enable(ice->core_clk); - if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice =3D dev_get_drvdata(dev); + + err =3D clk_prepare_enable(ice->core_clk); + if (err) { + dev_err(dev, "failed to enable core clock (%d)\n", + err); + } } =20 return err; @@ -770,9 +782,14 @@ static int ice_runtime_resume(struct device *dev) =20 static int ice_runtime_suspend(struct device *dev) { - struct qcom_ice *ice =3D dev_get_drvdata(dev); + const struct engine_desc *engine_cfg =3D device_get_match_data(dev); + + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice =3D dev_get_drvdata(dev); + + clk_disable_unprepare(ice->core_clk); + } =20 - clk_disable_unprepare(ice->core_clk); return 0; } =20 @@ -780,8 +797,13 @@ static const struct dev_pm_ops ice_pm_ops =3D { SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL) }; =20 +static const struct engine_desc cfg_fw_managed =3D { + .fw_managed =3D true, +}; + static const struct of_device_id qcom_ice_of_match_table[] =3D { { .compatible =3D "qcom,inline-crypto-engine" }, + { .compatible =3D "qcom,sa8255p-inline-crypto-engine", .data =3D &cfg_fw_= managed }, { }, }; MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); --=20 2.34.1