From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70649191F91; Tue, 12 May 2026 03:34:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; cv=none; b=P7QzVfwt7TEuX0o1LhzSEDIb63I/lg9TioFiYMz3lgcYsLajuAgLjGsMr79u+ZktrCKvmr91loRiIqPQtrQNlEBgU5euLaZ33FNf+HEpXfB8se2EYs+umumUp8BjtUFuvOYFjm47jpsRIJAYX4QA7LwNGMttMRKBfEcAuKdqsTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; c=relaxed/simple; bh=zo3ua4tjSJT16HT8pARi7KfE6Nh31HEVohwZpTphF3E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jfEvNgm9kg73WLfCQTg5VXjW6dcFqZQt+DHvujo5GYZEa7TvbCO27U6lsKbfxZNOHbhk8IPHB7kQ4lWEnFsO/xnl5hZtIqdzmnwDtk0Lp8CTnI1Ab7tVf3na/jqLR7nVl47MqNZDbYXNgbHU8Wuk20o+oA1ezCyoXftQyH3pX3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=o//eQHsx; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="o//eQHsx" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 64C3XIZS03571928, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1778556798; bh=dOwvgZaj8C8d3GPUA8TOM+3UpiD8i749mYQXLwcMoZE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=o//eQHsx/N3X3qO8pXBqvh5gG5QOP2Y5ngNpoV0FOzqeazt/8dUNdJmHNXCL+6tl/ g/W2xbZ2fibWQkDiaPMUse5UzjIgNZNpBEpmqO+IxrZbwUtIk7wTuRWO0eVxy0ckgr w/RjJU9m2e0mfD0peJz8ObItJeEiNkfh70KDRAJ2t56wTGexki12FKLzV86JuGPFkD cxFhyYNRH0xp5HIzuCuUiU8raVEum75EANdA72iWvqmqoTxD1MWupCxuIEbzctKx4w PKnjcKq6nULplHkPqZz70SamIEkP9ANqcrzo+pkWmDg2H/rjcKR61AmY5jh6e6oZrM Wu4XFJxd2G4AQ== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.27/5.94) with ESMTPS id 64C3XIZS03571928 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 12 May 2026 11:33:18 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:18 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:18 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:18 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 1/7] gpio: Replace "default y" with "default ARCH_REALTEK" in Kconfig Date: Tue, 12 May 2026 11:33:11 +0800 Message-ID: <20260512033317.1602537-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace "default y" with "default ARCH_REALTEK" to avoid bloating the build for non-Realtek platforms when COMPILE_TEST is enabled on other platforms. Signed-off-by: Yu-Chun Lin --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 020e51e30317..504b4bdd75d4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -637,7 +637,7 @@ config GPIO_ROCKCHIP config GPIO_RTD tristate "Realtek DHC GPIO support" depends on ARCH_REALTEK || COMPILE_TEST - default y + default ARCH_REALTEK select GPIOLIB_IRQCHIP help This option enables support for GPIOs found on Realtek DHC(Digital --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30CCA274B43; Tue, 12 May 2026 03:34:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; cv=none; b=EQ22gPWcxVp4rkd6NGjpD6K20FxBGEunLNmOq5bvREJ21XnqwSaD+EsjZPPGAkSE2QcIkKsFOY/vi0dkPAMxKvON/rTMKXpfE9PNtBgndpa84tdhmFoezhZg9c8vji+2Qf0hYNOh7kvgrdVGKEdQ1GOIVuA1p0I3IQzfMRq5eNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; c=relaxed/simple; bh=tSv8hEY8sk+mSdC1mMMC8Q63kBRtY+0Goshq44RXMbw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lhINX1QPsBQvUXqrqTTvcJVR0XZclJPxVyXG7RLM+rPjqMpxJzMP5ICmA9GsBO6Isq95NyuDLoVLBJTeZ95Ion/NfzgEZKYwtfvLe/z9QHYXzlPFZsBBC5F4nT5DJD3SwGPF4OrNhbWlvUoBFHafb7gJRScDi+A8QkF/7b80ijY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=YCKBm32C; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="YCKBm32C" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 64C3XIeR43571932, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1778556798; bh=UJl/6Y6d4E6puh3y3cEykQ83pumRgeb1nEF73Wn9I74=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=YCKBm32CPGop+DynySQ5CrtQTVwrpjxzjpPWAZ/hkBe1/hVH6Sh9pZh8cMwPkrsJN u/STXO9gnMlc0Yb1pnN3qOvsebF6+9yJdLSxDt3033ULLKhXId20NdZG1A08Pc5zYf lrchTqSasIbl5wmx/4sVGwJJy51tWFelV05ZVueRPMHM+k3JJXq9alU4RAin2m8O0G 4kBd7QqfNZDwUV25d0uvm+YnvNkQcFARS6uXhmtd6d9eyD37Ur5KhvBfKymbzOyhE6 EbcFn5gUa0alCbmrAJkADc8IDYAx7+yQFUqSZbMAkV7VZUyzP18+kd7Wp2/l8QPjko wIe/n/1NtRNmg== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.27/5.94) with ESMTPS id 64C3XIeR43571932 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 12 May 2026 11:33:18 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:19 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:18 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:18 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 2/7] gpio: regmap: add gpio_regmap_get_gpiochip() accessor Date: Tue, 12 May 2026 11:33:12 +0800 Message-ID: <20260512033317.1602537-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expose an accessor function to retrieve the gpio_chip pointer from a gpio_regmap instance. This is needed by drivers that use gpio_regmap but also manage their own irq_chip, where gpiochip_enable_irq()/gpiochip_disable_irq() must be called with the gpio_chip pointer. Add gpio_regmap_get_gpiochip() to allow drivers with complex custom IRQ implementations. Signed-off-by: Yu-Chun Lin --- drivers/gpio/gpio-regmap.c | 6 ++++++ include/linux/gpio/regmap.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 9ae4a41a2427..deb9eebb58de 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -230,6 +230,12 @@ void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) } EXPORT_SYMBOL_GPL(gpio_regmap_get_drvdata); =20 +struct gpio_chip *gpio_regmap_get_gpiochip(struct gpio_regmap *gpio) +{ + return &gpio->gpio_chip; +} +EXPORT_SYMBOL_GPL(gpio_regmap_get_gpiochip); + /** * gpio_regmap_register() - Register a generic regmap GPIO controller * @config: configuration for gpio_regmap diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 12d154732ca9..e4a95f805a81 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -113,5 +113,6 @@ void gpio_regmap_unregister(struct gpio_regmap *gpio); struct gpio_regmap *devm_gpio_regmap_register(struct device *dev, const struct gpio_regmap_config *config); void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio); +struct gpio_chip *gpio_regmap_get_gpiochip(struct gpio_regmap *gpio); =20 #endif /* _LINUX_GPIO_REGMAP_H */ --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 760ED226D18; Tue, 12 May 2026 03:34:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; cv=none; b=udfmkKmxWfZgap5ITFxXLKKd6UHDoOjz4p5RW0spj0hmufGBvkxwhtpTT5vfemU0GDPRa2MS/5kk/BpYuBc4r6/999kNdfSJLa59/MyrXgsZILCQyYFOeenvj4fH7Twef76V5GIbK+yo/hvplzTFytX026VGX3XnXic5I39J1Gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556881; c=relaxed/simple; bh=STg+/kp/CRwX2rjIcCOFYfha5vMo8nNiCAngZ1D/WxM=; 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Tue, 12 May 2026 11:33:19 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:18 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:18 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , , Linus Walleij Subject: [PATCH v3 3/7] gpio: regmap: Add gpio_regmap_operation and write-enable support Date: Tue, 12 May 2026 11:33:13 +0800 Message-ID: <20260512033317.1602537-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the reg_mask_xlate callback with an operation type parameter (gpio_regmap_operation) to allow drivers to return different register/mask combinations for different GPIO operations. Also add write-enable mechanism for hardware that requires setting a write-enable bit before modifying GPIO control registers. Consequently, update all existing drivers utilizing the gpio-regmap framework (across drivers/gpio, drivers/iio, and drivers/pinctrl) to accommodate the new reg_mask_xlate function signature. Suggested-by: Linus Walleij Signed-off-by: Yu-Chun Lin --- drivers/gpio/gpio-104-idi-48.c | 18 +++++-- drivers/gpio/gpio-i8255.c | 13 ++++- drivers/gpio/gpio-idio-16.c | 16 ++++-- drivers/gpio/gpio-max7360.c | 10 ++++ drivers/gpio/gpio-pcie-idio-24.c | 15 ++++-- drivers/gpio/gpio-regmap.c | 72 ++++++++++++++++++++------- drivers/iio/adc/ad7173.c | 32 +++++++++--- drivers/iio/addac/stx104.c | 17 +++++-- drivers/pinctrl/bcm/pinctrl-bcm63xx.c | 12 ++++- drivers/pinctrl/pinctrl-tps6594.c | 10 ++++ include/linux/gpio/regmap.h | 43 ++++++++++++++-- 11 files changed, 214 insertions(+), 44 deletions(-) diff --git a/drivers/gpio/gpio-104-idi-48.c b/drivers/gpio/gpio-104-idi-48.c index ba73ee9c0c29..ebd0587f99c5 100644 --- a/drivers/gpio/gpio-104-idi-48.c +++ b/drivers/gpio/gpio-104-idi-48.c @@ -36,9 +36,10 @@ MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line n= umbers"); #define IDI48_IRQ_STATUS 0x7 #define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS =20 -static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int ba= se, - unsigned int offset, unsigned int *reg, - unsigned int *mask) +static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) { const unsigned int line =3D offset % 8; const unsigned int stride =3D offset / 8; @@ -46,7 +47,16 @@ static int idi_48_reg_mask_xlate(struct gpio_regmap *gpi= o, unsigned int base, const unsigned int port_stride =3D stride % 3; =20 *reg =3D base + port + port_stride; - *mask =3D BIT(line); + + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D BIT(line); + break; + } =20 return 0; } diff --git a/drivers/gpio/gpio-i8255.c b/drivers/gpio/gpio-i8255.c index 953018bfa2b1..ec3c3186e2d1 100644 --- a/drivers/gpio/gpio-i8255.c +++ b/drivers/gpio/gpio-i8255.c @@ -67,8 +67,8 @@ static int i8255_ppi_init(struct regmap *const map, const= unsigned int base) return regmap_write(map, base + I8255_PORTC, 0x00); } =20 -static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int bas= e, - unsigned int offset, unsigned int *reg, +static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap= _operation op, + unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { const unsigned int ppi =3D offset / I8255_NGPIO; @@ -76,6 +76,15 @@ static int i8255_reg_mask_xlate(struct gpio_regmap *gpio= , unsigned int base, const unsigned int stride =3D ppi_offset / I8255_NGPIO_PER_REG; const unsigned int line =3D ppi_offset % I8255_NGPIO_PER_REG; =20 + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + return 0; + default: + break; + } + switch (base) { case I8255_REG_DAT_BASE: *reg =3D base + stride + ppi * 4; diff --git a/drivers/gpio/gpio-idio-16.c b/drivers/gpio/gpio-idio-16.c index 4fbae6f6a497..d78a05c22531 100644 --- a/drivers/gpio/gpio-idio-16.c +++ b/drivers/gpio/gpio-idio-16.c @@ -66,9 +66,9 @@ static int idio_16_handle_mask_sync(const int index, cons= t unsigned int mask_buf return 0; } =20 -static int idio_16_reg_mask_xlate(struct gpio_regmap *const gpio, const un= signed int base, - const unsigned int offset, unsigned int *const reg, - unsigned int *const mask) +static int idio_16_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpi= o_regmap_operation op, + const unsigned int base, const unsigned int offset, + unsigned int *const reg, unsigned int *const mask) { unsigned int stride; =20 @@ -81,7 +81,15 @@ static int idio_16_reg_mask_xlate(struct gpio_regmap *co= nst gpio, const unsigned *reg =3D IDIO_16_IN_BASE + stride * IDIO_16_REG_STRIDE; } =20 - *mask =3D BIT(offset % IDIO_16_NGPIO_PER_REG); + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D BIT(offset % IDIO_16_NGPIO_PER_REG); + break; + } =20 return 0; } diff --git a/drivers/gpio/gpio-max7360.c b/drivers/gpio/gpio-max7360.c index db92a43776a9..2a26313d021d 100644 --- a/drivers/gpio/gpio-max7360.c +++ b/drivers/gpio/gpio-max7360.c @@ -94,9 +94,19 @@ static int max7360_set_gpos_count(struct device *dev, st= ruct regmap *regmap) } =20 static int max7360_gpio_reg_mask_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + return 0; + default: + break; + } + if (base =3D=3D MAX7360_REG_PWMBASE) { /* * GPIO output is using PWM duty cycle registers: one register diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio= -24.c index 80c0ba0afa67..dc80f96174c2 100644 --- a/drivers/gpio/gpio-pcie-idio-24.c +++ b/drivers/gpio/gpio-pcie-idio-24.c @@ -225,9 +225,9 @@ static int idio_24_set_type_config(unsigned int **const= buf, const unsigned int return ret; } =20 -static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, const un= signed int base, - const unsigned int offset, unsigned int *const reg, - unsigned int *const mask) +static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpi= o_regmap_operation op, + const unsigned int base, const unsigned int offset, + unsigned int *const reg, unsigned int *const mask) { const unsigned int out_stride =3D offset / IDIO_24_NGPIO_PER_REG; const unsigned int in_stride =3D (offset - 24) / IDIO_24_NGPIO_PER_REG; @@ -235,6 +235,15 @@ static int idio_24_reg_mask_xlate(struct gpio_regmap *= const gpio, const unsigned int err; unsigned int ctrl_reg; =20 + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + return 0; + default: + break; + } + switch (base) { case IDIO_24_OUT_BASE: *mask =3D BIT(offset % IDIO_24_NGPIO_PER_REG); diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index deb9eebb58de..c76eef20e412 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -38,9 +38,10 @@ struct gpio_regmap { struct regmap_irq_chip_data *irq_chip_data; #endif =20 - int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, - unsigned int offset, unsigned int *reg, - unsigned int *mask); + int (*reg_mask_xlate)(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask); =20 void *driver_data; }; @@ -54,6 +55,7 @@ static unsigned int gpio_regmap_addr(unsigned int addr) } =20 static int gpio_regmap_simple_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { @@ -61,7 +63,16 @@ static int gpio_regmap_simple_xlate(struct gpio_regmap *= gpio, unsigned int stride =3D offset / gpio->ngpio_per_reg; =20 *reg =3D base + stride * gpio->reg_stride; - *mask =3D BIT(line); + + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D BIT(line); + break; + } =20 return 0; } @@ -69,7 +80,7 @@ static int gpio_regmap_simple_xlate(struct gpio_regmap *g= pio, static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset) { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); - unsigned int base, val, reg, mask; + unsigned int base, val, reg, mask, dir_mask; int ret; =20 /* we might not have an output register if we are input only */ @@ -78,10 +89,24 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsi= gned int offset) else base =3D gpio_regmap_addr(gpio->reg_set_base); =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_GET_OP, base, offset, ®= , &dir_mask); if (ret) return ret; =20 + ret =3D regmap_read(gpio->regmap, reg, &val); + if (ret) + return ret; + + if (val & dir_mask) { + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_OUT, base, offset, ®, = &mask); + if (ret) + return ret; + } else { + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_IN, base, offset, ®, &= mask); + if (ret) + return ret; + } + /* ensure we don't spoil any register cache with pin input values */ if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) ret =3D regmap_read_bypassed(gpio->regmap, reg, &val); @@ -98,10 +123,14 @@ static int gpio_regmap_set(struct gpio_chip *chip, uns= igned int offset, { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); unsigned int base =3D gpio_regmap_addr(gpio->reg_set_base); - unsigned int reg, mask, mask_val; + unsigned int reg, mask, mask_val, wren_mask; int ret; =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WREN_OP, base, offset,= ®, &wren_mask); + if (ret) + return ret; + + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_OP, base, offset, ®= , &mask); if (ret) return ret; =20 @@ -112,9 +141,9 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsi= gned int offset, =20 /* ignore input values which shadow the old output value */ if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) - ret =3D regmap_write_bits(gpio->regmap, reg, mask, mask_val); + ret =3D regmap_write_bits(gpio->regmap, reg, mask | wren_mask, mask_val = | wren_mask); else - ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask_val); + ret =3D regmap_update_bits(gpio->regmap, reg, mask | wren_mask, mask_val= | wren_mask); =20 return ret; } @@ -123,7 +152,7 @@ static int gpio_regmap_set_with_clear(struct gpio_chip = *chip, unsigned int offset, int val) { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); - unsigned int base, reg, mask; + unsigned int base, reg, mask, wren_mask; int ret; =20 if (val) @@ -131,11 +160,15 @@ static int gpio_regmap_set_with_clear(struct gpio_chi= p *chip, else base =3D gpio_regmap_addr(gpio->reg_clr_base); =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WREN_OP, base, offset,= ®, &wren_mask); if (ret) return ret; =20 - return regmap_write(gpio->regmap, reg, mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WITH_CLEAR_OP, base, o= ffset, ®, &mask); + if (ret) + return ret; + + return regmap_write(gpio->regmap, reg, mask | wren_mask); } =20 static int gpio_regmap_get_direction(struct gpio_chip *chip, @@ -167,7 +200,7 @@ static int gpio_regmap_get_direction(struct gpio_chip *= chip, return -ENOTSUPP; } =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_GET_DIR_OP, base, offset, = ®, &mask); if (ret) return ret; =20 @@ -185,7 +218,7 @@ static int gpio_regmap_set_direction(struct gpio_chip *= chip, unsigned int offset, bool output) { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); - unsigned int base, val, reg, mask; + unsigned int base, val, reg, mask, wren_mask; int invert, ret; =20 if (gpio->reg_dir_out_base) { @@ -198,7 +231,12 @@ static int gpio_regmap_set_direction(struct gpio_chip = *chip, return -ENOTSUPP; } =20 - ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_DIR_OP, base, offset, = ®, &mask); + if (ret) + return ret; + + ret =3D gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_DIR_WREN_OP, base, off= set, ®, + &wren_mask); if (ret) return ret; =20 @@ -207,7 +245,7 @@ static int gpio_regmap_set_direction(struct gpio_chip *= chip, else val =3D output ? mask : 0; =20 - return regmap_update_bits(gpio->regmap, reg, mask, val); + return regmap_update_bits(gpio->regmap, reg, mask | wren_mask, val | wren= _mask); } =20 static int gpio_regmap_direction_input(struct gpio_chip *chip, diff --git a/drivers/iio/adc/ad7173.c b/drivers/iio/adc/ad7173.c index f76a9e08f39e..e8a6921bc443 100644 --- a/drivers/iio/adc/ad7173.c +++ b/drivers/iio/adc/ad7173.c @@ -561,21 +561,41 @@ static int ad4111_openwire_event(struct iio_dev *indi= o_dev, return ret; } =20 -static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, - unsigned int offset, unsigned int *reg, +static int ad7173_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_op= eration op, + unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { - *mask =3D AD7173_GPO_DATA(offset); + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + return 0; + default: + *mask =3D AD7173_GPO_DATA(offset); + break; + } + *reg =3D base; + return 0; } =20 -static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, - unsigned int offset, unsigned int *reg, +static int ad4111_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_op= eration op, + unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { - *mask =3D AD4111_GPO01_DATA(offset); + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D AD4111_GPO01_DATA(offset); + break; + } + *reg =3D base; + return 0; } =20 diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c index 7bdf2cb94176..a4e54ed102a2 100644 --- a/drivers/iio/addac/stx104.c +++ b/drivers/iio/addac/stx104.c @@ -349,16 +349,25 @@ static const struct iio_chan_spec stx104_channels_dif= f[] =3D { STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1) }; =20 -static int stx104_reg_mask_xlate(struct gpio_regmap *const gpio, const uns= igned int base, - unsigned int offset, unsigned int *const reg, - unsigned int *const mask) +static int stx104_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpio= _regmap_operation op, + const unsigned int base, unsigned int offset, + unsigned int *const reg, unsigned int *const mask) { /* Output lines are located at same register bit offsets as input lines */ if (offset >=3D 4) offset -=3D 4; =20 *reg =3D base; - *mask =3D BIT(offset); + + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D BIT(offset); + break; + } =20 return 0; } diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c b/drivers/pinctrl/bcm/pi= nctrl-bcm63xx.c index 59d2ce8462d8..3a868deb7793 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c @@ -20,6 +20,7 @@ #define BCM63XX_DATA_REG 0x0c =20 static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { @@ -27,7 +28,16 @@ static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gp= io, unsigned int stride =3D offset / BCM63XX_BANK_GPIOS; =20 *reg =3D base - stride * BCM63XX_BANK_SIZE; - *mask =3D BIT(line); + + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + break; + default: + *mask =3D BIT(line); + break; + } =20 return 0; } diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tp= s6594.c index 6726853110d1..e30a856712af 100644 --- a/drivers/pinctrl/pinctrl-tps6594.c +++ b/drivers/pinctrl/pinctrl-tps6594.c @@ -347,12 +347,22 @@ static struct tps6594_pinctrl tps6594_template_pinctr= l =3D { }; =20 static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { unsigned int line =3D offset % 8; unsigned int stride =3D offset / 8; =20 + switch (op) { + case GPIO_REGMAP_SET_WREN_OP: + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D 0; + return 0; + default: + break; + } + switch (base) { case TPS6594_REG_GPIOX_CONF(0): *reg =3D TPS6594_REG_GPIOX_CONF(offset); diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index e4a95f805a81..519fc81add8a 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -13,6 +13,43 @@ struct regmap; #define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1)) #define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO) =20 +/** + * enum gpio_regmap_operation - Operation type for reg_mask_xlate callback + * + * This enum is used to distinguish between different types of GPIO operat= ions + * so that the reg_mask_xlate callback can return the appropriate mask for= each + * operation type. + * + * Value operations: + * @GPIO_REGMAP_GET_OP: Mask for reading direction to detect if GPIO is in= put or output. + * Used in gpio_regmap_get() to determine the GPIO di= rection. + * @GPIO_REGMAP_IN: Mask for reading input value. Used when GPIO is config= ured as input. + * @GPIO_REGMAP_OUT: Mask for reading output value. Used when GPIO is conf= igured as output. + * + * Output operations: + * @GPIO_REGMAP_SET_OP: Mask for setting GPIO output value. + * @GPIO_REGMAP_SET_WITH_CLEAR_OP: Mask for setting/clearing GPIO using se= parate registers. + * @GPIO_REGMAP_SET_WREN_OP: Write-enable mask for output operations. May = be used to enable + * writes to protected registers. + * + * Direction operations: + * @GPIO_REGMAP_GET_DIR_OP: Mask for reading GPIO direction (input/output). + * @GPIO_REGMAP_SET_DIR_OP: Mask for setting GPIO direction (input/output). + * @GPIO_REGMAP_SET_DIR_WREN_OP: Write-enable mask for direction operation= s. May be used to + * enable writes to protected direction regi= sters. + */ +enum gpio_regmap_operation { + GPIO_REGMAP_GET_OP, + GPIO_REGMAP_SET_OP, + GPIO_REGMAP_SET_WITH_CLEAR_OP, + GPIO_REGMAP_SET_WREN_OP, + GPIO_REGMAP_GET_DIR_OP, + GPIO_REGMAP_SET_DIR_OP, + GPIO_REGMAP_SET_DIR_WREN_OP, + GPIO_REGMAP_IN, + GPIO_REGMAP_OUT, +}; + /** * struct gpio_regmap_config - Description of a generic regmap gpio_chip. * @parent: The parent device @@ -97,9 +134,9 @@ struct gpio_regmap_config { unsigned long regmap_irq_flags; #endif =20 - int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, - unsigned int offset, unsigned int *reg, - unsigned int *mask); + int (*reg_mask_xlate)(struct gpio_regmap *gpio, enum gpio_regmap_operatio= n, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask); =20 int (*init_valid_mask)(struct gpio_chip *gc, unsigned long *valid_mask, --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9995271471; 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charset="utf-8" Add a new set_config callback to struct gpio_regmap_config to allow drivers to implement hardware-specific configuration such as debounce settings, or other platform-specific GPIO properties. Signed-off-by: Yu-Chun Lin Reviewed-by: Andy Shevchenko --- drivers/gpio/gpio-regmap.c | 2 ++ include/linux/gpio/regmap.h | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index c76eef20e412..490a35fe8768 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -371,6 +371,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config if (!gpio->reg_mask_xlate) gpio->reg_mask_xlate =3D gpio_regmap_simple_xlate; =20 + chip->set_config =3D config->set_config; + ret =3D gpiochip_add_data(chip, gpio); if (ret < 0) goto err_free_bitmap; diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 519fc81add8a..0660fd9be928 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -89,6 +89,9 @@ enum gpio_regmap_operation { * domain will be set accordingly. * @regmap_irq_line: (Optional) The IRQ the device uses to signal interrup= ts. * @regmap_irq_flags: (Optional) The IRQF_ flags to use for the interrupt. + * @set_config: (Optional) Callback for setting GPIO configuration such + * as debounce, drive strength, or other hardware specific + * settings. * * The ->reg_mask_xlate translates a given base address and GPIO offset to * register and mask pair. The base address is one of the given register @@ -142,6 +145,10 @@ struct gpio_regmap_config { unsigned long *valid_mask, unsigned int ngpios); =20 + int (*set_config)(struct gpio_chip *gc, + unsigned int offset, + unsigned long config); + void *drvdata; }; =20 --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E98442F83A2; Tue, 12 May 2026 03:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556899; cv=none; b=UMf1J66PWhfJS0BM7Z7HlAnoNyGGj/DhPdwzKVyf/DhW203v6Ynbf9HQ/2tx8tPO1+xDcjpBaSoWVhQN4Kc0qVG91QrfNEx4kjWQL0rbXB1yZt1hk1RQRtLEcN+lwEuGFQmzpwZsXjn5lCu+l0YxUhWv2pqGbUv68TOiRnPKEHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556899; c=relaxed/simple; bh=ZhdPSsqU1VtoN3zjMNuxTnfCBHFJ8NuxN7BaGty72eo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oX/iepNlY+mWUaJuzKUcBbimm3ypyFNdONJkl94iJOzOglokISO9ff734Pr5js+eKavZSuHeSYmuabh4smmfQ7j+p2LCcbmfyid6LTCp9oQvnViAAW+Ozy0ExXC+X6BumcVSsV5Y/dFUlSvbGD0NE/aMuFMzVh1Dg8whqaskhZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=PH/ibe10; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="PH/ibe10" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 64C3XJoF43571941, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1778556799; bh=LtdXnQEVIb6c5aCwt7NTASRXJz0sr0Gu7xDW8knSUp0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=PH/ibe10a+mefQYnoIHyfTzenlMWsYQCsiyitA/1ih68ubpjh4k6+k9o7bZ0qieRw PaDYkv2kH4AfQH0apvmW2y0R3AmXhvbyZx8kCVGVYAqtdcNTKffIieYTAIfAu73WNc bG74IX0xoiIyGCHxctQB/gfrzLgQWr+UE97QgqCUaAzPbpSBx/DvdXDPjK2hasHQRb xnfYO3PFRt+myy9gaBzM391GhMO4sOeVP0avb7ByxvJD+zwVm9a/LkFGNMi70CBzCT 6SA5VN1OvC6fQGIztGBzOIne5eXDRVhKHC2EbrBGio+kOOLzp6DuJbtlGM69b/zBDt a/ZrCvPRA9YGg== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.27/5.94) with ESMTPS id 64C3XJoF43571941 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 12 May 2026 11:33:19 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:19 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 12 May 2026 11:33:19 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:19 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , , Krzysztof Kozlowski Subject: [PATCH v3 5/7] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio Date: Tue, 12 May 2026 11:33:15 +0800 Message-ID: <20260512033317.1602537-6-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add the device tree bindings for the Realtek DHC (Digital Home Center) RTD1625 GPIO controllers. The RTD1625 GPIO controller features a per-pin register architecture that differs significantly from previous generations. It utilizes separate register blocks for GPIO configuration and interrupt control. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin --- .../bindings/gpio/realtek,rtd1625-gpio.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/realtek,rtd1625-= gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.ya= ml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml new file mode 100644 index 000000000000..f13c910b73c6 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 GPIO controller + +maintainers: + - Tzuyi Chang + +description: | + GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register + architecture that differs significantly from earlier RTD series controll= ers. + Each GPIO has dedicated registers for configuration (direction, input/ou= tput + values, debounce), and interrupt control supporting edge and level detec= tion + modes. + +properties: + compatible: + enum: + - realtek,rtd1625-iso-gpio + - realtek,rtd1625-isom-gpio + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt number of the assert GPIO interrupt, which = is + triggered when there is a rising edge. + - description: Interrupt number of the deassert GPIO interrupt, whic= h is + triggered when there is a falling edge. + - description: Interrupt number of the level-sensitive GPIO interrup= t, + triggered by a configured logic level. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-ranges: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - gpio-ranges + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@89100 { + compatible =3D "realtek,rtd1625-isom-gpio"; + reg =3D <0x89100 0x30>; + interrupt-parent =3D <&iso_m_irq_mux>; + interrupts =3D <0>, <1>, <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&isom_pinctrl 0 0 4>; + gpio-controller; + #gpio-cells =3D <2>; + }; --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FF08274B44; Tue, 12 May 2026 03:34:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556882; cv=none; b=A6JWLk3bARuzYgL7YR2OuqkrZnjYvvu6XVJDQAtgl36cMo05cEjyzK/SxIn3G3ZmvtW97PP5zGGm2bqwo7UFOu2e7ifpDt0YgF65NoJSZb4nztyfuw1U9NpcNRecxOpJxAnT8tJhVb8dGc1V/tDUnHGhYPmf1ESR5up4v1m0GEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 12 May 2026 11:33:19 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:19 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v3 6/7] gpio: realtek: Add driver for Realtek DHC RTD1625 SoC Date: Tue, 12 May 2026 11:33:16 +0800 Message-ID: <20260512033317.1602537-7-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs. Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c), which manages pins via shared bank registers, the RTD1625 introduces a per-pin register architecture. Each GPIO line now has its own dedicated 32-bit control register to manage configuration independently, including direction, output value, input value, interrupt enable, and debounce. Therefore, this distinct hardware design requires a separate driver. The driver leverages the gpio-regmap framework, utilizing the recently introduced write-enable and operation-specific mask translation features. Additionally, because the controller utilizes multiple independent IRQ status registers (assert, de-assert, and level) which cannot be mapped via standard regmap_irq_chip, the driver implements a custom irq_domain. Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- drivers/gpio/Kconfig | 13 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rtd1625.c | 608 ++++++++++++++++++++++++++++++++++++ 3 files changed, 622 insertions(+) create mode 100644 drivers/gpio/gpio-rtd1625.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 504b4bdd75d4..4449b288dfd5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -647,6 +647,19 @@ config GPIO_RTD Say yes here to support GPIO functionality and GPIO interrupt on Realtek DHC SoCs. =20 +config GPIO_RTD1625 + tristate "Realtek DHC RTD1625 GPIO support" + depends on ARCH_REALTEK || COMPILE_TEST + default ARCH_REALTEK + select GPIOLIB_IRQCHIP + select GPIO_REGMAP + help + This option enables support for the GPIO controller on Realtek + DHC (Digital Home Center) RTD1625 SoC. + + Say yes here to support both basic GPIO line functionality + and GPIO interrupt handling capabilities for this platform. + config GPIO_SAMA5D2_PIOBU tristate "SAMA5D2 PIOBU GPIO support" depends on OF diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b267598b517d..d837061d2df7 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -158,6 +158,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO) +=3D gpio-realtek-otto= .o obj-$(CONFIG_GPIO_REG) +=3D gpio-reg.o obj-$(CONFIG_GPIO_ROCKCHIP) +=3D gpio-rockchip.o obj-$(CONFIG_GPIO_RTD) +=3D gpio-rtd.o +obj-$(CONFIG_GPIO_RTD1625) +=3D gpio-rtd1625.o obj-$(CONFIG_ARCH_SA1100) +=3D gpio-sa1100.o obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) +=3D gpio-sama5d2-piobu.o obj-$(CONFIG_GPIO_SCH311X) +=3D gpio-sch311x.o diff --git a/drivers/gpio/gpio-rtd1625.c b/drivers/gpio/gpio-rtd1625.c new file mode 100644 index 000000000000..0eae4bb5577d --- /dev/null +++ b/drivers/gpio/gpio-rtd1625.c @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC RTD1625 gpio driver + * + * Copyright (c) 2023-2026 Realtek Semiconductor Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTD1625_GPIO_DIR BIT(0) +#define RTD1625_GPIO_OUT BIT(2) +#define RTD1625_GPIO_IN BIT(4) +#define RTD1625_GPIO_EDGE_INT_DP BIT(6) +#define RTD1625_GPIO_EDGE_INT_EN BIT(8) +#define RTD1625_GPIO_LEVEL_INT_EN BIT(16) +#define RTD1625_GPIO_LEVEL_INT_DP BIT(18) +#define RTD1625_GPIO_DEBOUNCE GENMASK(30, 28) +#define RTD1625_GPIO_DEBOUNCE_WREN BIT(31) + +#define RTD1625_GPIO_WREN(x) ((x) << 1) + +/* Write-enable masks for all GPIO configs and reserved hardware bits */ +#define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a +#define RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a + +#define RTD1625_GPIO_DEBOUNCE_1US 0 +#define RTD1625_GPIO_DEBOUNCE_10US 1 +#define RTD1625_GPIO_DEBOUNCE_100US 2 +#define RTD1625_GPIO_DEBOUNCE_1MS 3 +#define RTD1625_GPIO_DEBOUNCE_10MS 4 +#define RTD1625_GPIO_DEBOUNCE_20MS 5 +#define RTD1625_GPIO_DEBOUNCE_30MS 6 +#define RTD1625_GPIO_DEBOUNCE_50MS 7 + +#define GPIO_CONTROL(gpio) ((gpio) * 4) + +/** + * struct rtd1625_gpio_info - Specific GPIO register information + * @num_gpios: The number of GPIOs + * @irq_type_support: Supported IRQ types + * @gpa_offset: Offset for GPIO assert interrupt status registers + * @gpda_offset: Offset for GPIO deassert interrupt status registers + * @level_offset: Offset of level interrupt status register + * @write_en_all: Write-enable mask for all configurable bits + */ +struct rtd1625_gpio_info { + unsigned int num_gpios; + unsigned int irq_type_support; + unsigned int base_offset; + unsigned int gpa_offset; + unsigned int gpda_offset; + unsigned int level_offset; + unsigned int write_en_all; +}; + +struct rtd1625_gpio { + struct gpio_chip *gpio_chip; + const struct rtd1625_gpio_info *info; + void __iomem *base; + struct regmap *regmap; + unsigned int irqs[3]; + raw_spinlock_t lock; + struct irq_domain *domain; + unsigned int *save_regs; +}; + +static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio *data, uns= igned int offset) +{ + return data->info->gpa_offset + ((offset / 32) * 4); +} + +static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio *data, un= signed int offset) +{ + return data->info->gpda_offset + ((offset / 32) * 4); +} + +static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio *data, u= nsigned int offset) +{ + return data->info->level_offset + ((offset / 32) * 4); +} + +static int rtd1625_reg_mask_xlate(struct gpio_regmap *gpio, enum gpio_regm= ap_operation op, + unsigned int base, unsigned int offset, unsigned int *reg, + unsigned int *mask) +{ + /* Each GPIO has its own dedicated 32-bit register */ + *reg =3D base + offset * 4; + + switch (op) { + case GPIO_REGMAP_IN: + *mask =3D RTD1625_GPIO_IN; + break; + case GPIO_REGMAP_OUT: + *mask =3D RTD1625_GPIO_OUT; + break; + case GPIO_REGMAP_SET_WREN_OP: + *mask =3D RTD1625_GPIO_WREN(RTD1625_GPIO_OUT); + break; + case GPIO_REGMAP_SET_WITH_CLEAR_OP: + case GPIO_REGMAP_SET_OP: + *mask =3D RTD1625_GPIO_OUT; + break; + case GPIO_REGMAP_SET_DIR_WREN_OP: + *mask =3D RTD1625_GPIO_WREN(RTD1625_GPIO_DIR); + break; + case GPIO_REGMAP_GET_OP: + case GPIO_REGMAP_GET_DIR_OP: + *mask =3D RTD1625_GPIO_DIR; + break; + default: + *mask =3D 0; + break; + } + + return 0; +} + +static unsigned int rtd1625_gpio_set_debounce(struct gpio_chip *chip, unsi= gned int offset, + unsigned int debounce) +{ + struct rtd1625_gpio *data =3D gpiochip_get_data(chip); + u8 deb_val; + u32 val; + + switch (debounce) { + case 1: + deb_val =3D RTD1625_GPIO_DEBOUNCE_1US; + break; + case 10: + deb_val =3D RTD1625_GPIO_DEBOUNCE_10US; + break; + case 100: + deb_val =3D RTD1625_GPIO_DEBOUNCE_100US; + break; + case 1000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_1MS; + break; + case 10000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_10MS; + break; + case 20000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_20MS; + break; + case 30000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_30MS; + break; + case 50000: + deb_val =3D RTD1625_GPIO_DEBOUNCE_50MS; + break; + default: + return -ENOTSUPP; + } + + val =3D FIELD_PREP(RTD1625_GPIO_DEBOUNCE, deb_val) | RTD1625_GPIO_DEBOUNC= E_WREN; + regmap_write(data->regmap, GPIO_CONTROL(offset), val); + + return 0; +} + +static int rtd1625_gpio_set_config(struct gpio_chip *chip, unsigned int of= fset, + unsigned long config) +{ + int debounce; + + if (pinconf_to_config_param(config) =3D=3D PIN_CONFIG_INPUT_DEBOUNCE) { + debounce =3D pinconf_to_config_argument(config); + return rtd1625_gpio_set_debounce(chip, offset, debounce); + } + + return gpiochip_generic_config(chip, offset, config); +} + +static void rtd1625_gpio_irq_handle(struct irq_desc *desc) +{ + unsigned int (*get_reg_offset)(struct rtd1625_gpio *gpio, unsigned int of= fset); + struct rtd1625_gpio *data =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int irq =3D irq_desc_get_irq(desc); + struct irq_domain *domain =3D data->domain; + unsigned int reg_offset, i, j, val; + irq_hw_number_t hwirq; + unsigned long status; + unsigned int girq; + u32 irq_type; + + if (irq =3D=3D data->irqs[0]) + get_reg_offset =3D &rtd1625_gpio_gpa_offset; + else if (irq =3D=3D data->irqs[1]) + get_reg_offset =3D &rtd1625_gpio_gpda_offset; + else if (irq =3D=3D data->irqs[2]) + get_reg_offset =3D &rtd1625_gpio_level_offset; + else + return; + + chained_irq_enter(chip, desc); + + for (i =3D 0; i < data->info->num_gpios; i +=3D 32) { + reg_offset =3D get_reg_offset(data, i); + regmap_read(data->regmap, reg_offset, &val); + + status =3D val; + + /* Clear edge interrupts; level interrupts are cleared in ->irq_ack() */ + if (irq !=3D data->irqs[2]) + regmap_write(data->regmap, reg_offset, status); + + for_each_set_bit(j, &status, 32) { + hwirq =3D i + j; + girq =3D irq_find_mapping(domain, hwirq); + irq_type =3D irq_get_trigger_type(girq); + + if (irq =3D=3D data->irqs[1] && irq_type !=3D IRQ_TYPE_EDGE_BOTH) + continue; + + generic_handle_domain_irq(domain, hwirq); + } + } + + chained_irq_exit(chip, desc); +} + +static void rtd1625_gpio_ack_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + u32 bit_mask =3D BIT(hwirq % 32); + struct rtd1625_gpio *data; + struct gpio_regmap *gpio; + int reg_offset; + + gpio =3D gpiochip_get_data(gc); + data =3D gpio_regmap_get_drvdata(gpio); + + if (irq_type & IRQ_TYPE_LEVEL_MASK) { + reg_offset =3D rtd1625_gpio_level_offset(data, hwirq); + regmap_write(data->regmap, reg_offset, bit_mask); + } +} + +static void rtd1625_gpio_enable_edge_irq(struct rtd1625_gpio *data, irq_hw= _number_t hwirq) +{ + int gpda_reg_offset =3D rtd1625_gpio_gpda_offset(data, hwirq); + int gpa_reg_offset =3D rtd1625_gpio_gpa_offset(data, hwirq); + u32 clr_mask =3D BIT(hwirq % 32); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + regmap_write(data->regmap, gpa_reg_offset, clr_mask); + regmap_write(data->regmap, gpda_reg_offset, clr_mask); + val =3D RTD1625_GPIO_EDGE_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_IN= T_EN); + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq),= val); +} + +static void rtd1625_gpio_disable_edge_irq(struct rtd1625_gpio *data, irq_h= w_number_t hwirq) +{ + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN); + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq),= val); +} + +static void rtd1625_gpio_enable_level_irq(struct rtd1625_gpio *data, irq_h= w_number_t hwirq) +{ + int level_reg_offset =3D rtd1625_gpio_level_offset(data, hwirq); + u32 clr_mask =3D BIT(hwirq % 32); + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + regmap_write(data->regmap, level_reg_offset, clr_mask); + val =3D RTD1625_GPIO_LEVEL_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_= INT_EN); + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq),= val); +} + +static void rtd1625_gpio_disable_level_irq(struct rtd1625_gpio *data, irq_= hw_number_t hwirq) +{ + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN); + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq),= val); +} + +static void rtd1625_gpio_enable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + struct rtd1625_gpio *data; + struct gpio_regmap *gpio; + + gpio =3D gpiochip_get_data(gc); + data =3D gpio_regmap_get_drvdata(gpio); + + gpiochip_enable_irq(gc, hwirq); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) + rtd1625_gpio_enable_edge_irq(data, hwirq); + else if (irq_type & IRQ_TYPE_LEVEL_MASK) + rtd1625_gpio_enable_level_irq(data, hwirq); +} + +static void rtd1625_gpio_disable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 irq_type =3D irqd_get_trigger_type(d); + struct rtd1625_gpio *data; + struct gpio_regmap *gpio; + + gpio =3D gpiochip_get_data(gc); + data =3D gpio_regmap_get_drvdata(gpio); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) + rtd1625_gpio_disable_edge_irq(data, hwirq); + else if (irq_type & IRQ_TYPE_LEVEL_MASK) + rtd1625_gpio_disable_level_irq(data, hwirq); + + gpiochip_disable_irq(gc, hwirq); +} + +static int rtd1625_gpio_irq_set_level_type(struct irq_data *d, bool level) +{ + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_DP); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + struct rtd1625_gpio *data; + struct gpio_regmap *gpio; + + gpio =3D gpiochip_get_data(gc); + data =3D gpio_regmap_get_drvdata(gpio); + if (!(data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK)) + return -EINVAL; + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + if (level) + val |=3D RTD1625_GPIO_LEVEL_INT_DP; + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq)= , val); + } + + irq_set_handler_locked(d, handle_level_irq); + + return 0; +} + +static int rtd1625_gpio_irq_set_edge_type(struct irq_data *d, bool polarit= y) +{ + u32 val =3D RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_DP); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + struct rtd1625_gpio *data; + struct gpio_regmap *gpio; + + gpio =3D gpiochip_get_data(gc); + data =3D gpio_regmap_get_drvdata(gpio); + if (!(data->info->irq_type_support & IRQ_TYPE_EDGE_BOTH)) + return -EINVAL; + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + if (polarity) + val |=3D RTD1625_GPIO_EDGE_INT_DP; + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(hwirq)= , val); + } + + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static int rtd1625_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + int ret; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 1); + break; + case IRQ_TYPE_EDGE_FALLING: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 0); + break; + case IRQ_TYPE_EDGE_BOTH: + ret =3D rtd1625_gpio_irq_set_edge_type(d, 1); + break; + case IRQ_TYPE_LEVEL_HIGH: + ret =3D rtd1625_gpio_irq_set_level_type(d, 0); + break; + case IRQ_TYPE_LEVEL_LOW: + ret =3D rtd1625_gpio_irq_set_level_type(d, 1); + break; + default: + ret =3D -EINVAL; + } + + return ret; +} + +static struct irq_chip rtd1625_iso_gpio_irq_chip =3D { + .name =3D "rtd1625-gpio", + .irq_ack =3D rtd1625_gpio_ack_irq, + .irq_mask =3D rtd1625_gpio_disable_irq, + .irq_unmask =3D rtd1625_gpio_enable_irq, + .irq_set_type =3D rtd1625_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int rtd1625_gpio_setup_irq(struct platform_device *pdev, struct rtd= 1625_gpio *data) +{ + int num_irqs, irq, i; + + irq =3D platform_get_irq_optional(pdev, 0); + if (irq =3D=3D -ENXIO) + return 0; + if (irq < 0) + return irq; + + num_irqs =3D (data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK) ? 3 : 2; + + for (i =3D 0; i < num_irqs; i++) { + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + data->irqs[i] =3D irq; + irq_set_chained_handler_and_data(data->irqs[i], rtd1625_gpio_irq_handle,= data); + } + + return 0; +} + +static int rtd1625_gpio_irq_map(struct irq_domain *domain, unsigned int ir= q, + irq_hw_number_t hwirq) +{ + struct rtd1625_gpio *data =3D domain->host_data; + + irq_set_chip_data(irq, data->gpio_chip); + + irq_set_chip_and_handler(irq, &rtd1625_iso_gpio_irq_chip, handle_bad_irq); + + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops rtd1625_gpio_irq_domain_ops =3D { + .map =3D rtd1625_gpio_irq_map, + .xlate =3D irq_domain_xlate_twocell, +}; + +static const struct regmap_config rtd1625_gpio_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .disable_locking =3D true, +}; + +static int rtd1625_gpio_probe(struct platform_device *pdev) +{ + struct gpio_regmap_config config =3D {0}; + struct device *dev =3D &pdev->dev; + struct gpio_regmap *gpio_reg; + struct rtd1625_gpio *data; + void __iomem *irq_base; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->info =3D device_get_match_data(dev); + if (!data->info) + return -EINVAL; + + irq_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(irq_base)) + return PTR_ERR(irq_base); + + data->regmap =3D devm_regmap_init_mmio(dev, irq_base, + &rtd1625_gpio_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + data->save_regs =3D devm_kzalloc(dev, data->info->num_gpios * + sizeof(*data->save_regs), GFP_KERNEL); + if (!data->save_regs) + return -ENOMEM; + + config.parent =3D dev; + config.regmap =3D data->regmap; + config.ngpio =3D data->info->num_gpios; + config.reg_dat_base =3D data->info->base_offset; + config.reg_set_base =3D data->info->base_offset; + config.reg_mask_xlate =3D rtd1625_reg_mask_xlate; + config.set_config =3D rtd1625_gpio_set_config; + config.reg_dir_out_base =3D data->info->base_offset; + + data->domain =3D irq_domain_add_linear(dev->of_node, + data->info->num_gpios, + &rtd1625_gpio_irq_domain_ops, + data); + if (!data->domain) + return -ENOMEM; + + ret =3D rtd1625_gpio_setup_irq(pdev, data); + if (ret) { + irq_domain_remove(data->domain); + return ret; + } + + config.irq_domain =3D data->domain; + config.drvdata =3D data; + platform_set_drvdata(pdev, data); + + gpio_reg =3D devm_gpio_regmap_register(dev, &config); + if (IS_ERR(gpio_reg)) { + irq_domain_remove(data->domain); + return PTR_ERR(gpio_reg); + } + + data->gpio_chip =3D gpio_regmap_get_gpiochip(gpio_reg); + + return 0; +} + +static const struct rtd1625_gpio_info rtd1625_iso_gpio_info =3D { + .num_gpios =3D 166, + .irq_type_support =3D IRQ_TYPE_EDGE_BOTH, + .base_offset =3D 0x100, + .gpa_offset =3D 0x0, + .gpda_offset =3D 0x20, + .write_en_all =3D RTD1625_ISO_GPIO_WREN_ALL, +}; + +static const struct rtd1625_gpio_info rtd1625_isom_gpio_info =3D { + .num_gpios =3D 4, + .irq_type_support =3D IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_LOW | + IRQ_TYPE_LEVEL_HIGH, + .base_offset =3D 0x20, + .gpa_offset =3D 0x0, + .gpda_offset =3D 0x4, + .level_offset =3D 0x18, + .write_en_all =3D RTD1625_ISOM_GPIO_WREN_ALL, +}; + +static const struct of_device_id rtd1625_gpio_of_matches[] =3D { + { .compatible =3D "realtek,rtd1625-iso-gpio", .data =3D &rtd1625_iso_gpio= _info }, + { .compatible =3D "realtek,rtd1625-isom-gpio", .data =3D &rtd1625_isom_gp= io_info }, + { } +}; +MODULE_DEVICE_TABLE(of, rtd1625_gpio_of_matches); + +static int rtd1625_gpio_suspend(struct device *dev) +{ + struct rtd1625_gpio *data =3D dev_get_drvdata(dev); + const struct rtd1625_gpio_info *info =3D data->info; + int i; + + for (i =3D 0; i < info->num_gpios; i++) + regmap_read(data->regmap, data->info->base_offset + GPIO_CONTROL(i), + &data->save_regs[i]); + + return 0; +} + +static int rtd1625_gpio_resume(struct device *dev) +{ + struct rtd1625_gpio *data =3D dev_get_drvdata(dev); + const struct rtd1625_gpio_info *info =3D data->info; + int i; + + for (i =3D 0; i < info->num_gpios; i++) + regmap_write(data->regmap, data->info->base_offset + GPIO_CONTROL(i), + data->save_regs[i] | info->write_en_all); + + return 0; +} + +DEFINE_NOIRQ_DEV_PM_OPS(rtd1625_gpio_pm_ops, rtd1625_gpio_suspend, rtd1625= _gpio_resume); + +static struct platform_driver rtd1625_gpio_platform_driver =3D { + .driver =3D { + .name =3D "gpio-rtd1625", + .of_match_table =3D rtd1625_gpio_of_matches, + .pm =3D pm_sleep_ptr(&rtd1625_gpio_pm_ops), + }, + .probe =3D rtd1625_gpio_probe, +}; +module_platform_driver(rtd1625_gpio_platform_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 gpio driver"); --=20 2.34.1 From nobody Fri Jun 12 22:50:34 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1306336882; Tue, 12 May 2026 03:34:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778556885; cv=none; b=YNlpDEmz5bn84FB8gQcLlw99IfuAlGu9VQpODpRUXFnJVJh7rhg7aWXZY5NqRlCLfIdbcrVbODitfpP67Fit4gpDQvGGSXQZnx34+gqD/ypUDsoTWEIpeuKYvHTCZOC6sjNdTtc4KuSnKaFUmhgaD6Dlfr11rz+4Zzh1fYfl8VU= ARC-Message-Signature: i=1; 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Tue, 12 May 2026 11:33:20 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 12 May 2026 11:33:19 +0800 From: Yu-Chun Lin To: , , , , , , , , , , , , , , , CC: , , , , , , , , , , Bartosz Golaszewski Subject: [PATCH v3 7/7] arm64: dts: realtek: Add GPIO support for RTD1625 Date: Tue, 12 May 2026 11:33:17 +0800 Message-ID: <20260512033317.1602537-8-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com> References: <20260512033317.1602537-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the GPIO node for the Realtek RTD1625 SoC. Reviewed-by: Bartosz Golaszewski Signed-off-by: Yu-Chun Lin --- The changes are based on commit 856540ac9b441a8c0e39f1f1787277edc4097c9b, which was merged into the soc/for-next branch. --- arch/arm64/boot/dts/realtek/kent.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index 8d4293cd4c03..228b82dfdb7a 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -151,6 +151,37 @@ uart0: serial@7800 { status =3D "disabled"; }; =20 + gpio: gpio@31000 { + compatible =3D "realtek,rtd1625-iso-gpio"; + reg =3D <0x31000 0x398>; + gpio-controller; + gpio-ranges =3D <&isom_pinctrl 0 0 2>, + <&ve4_pinctrl 2 0 6>, + <&iso_pinctrl 8 0 4>, + <&ve4_pinctrl 12 6 2>, + <&main2_pinctrl 14 0 2>, + <&ve4_pinctrl 16 8 4>, + <&main2_pinctrl 20 2 3>, + <&ve4_pinctrl 23 12 3>, + <&iso_pinctrl 26 4 2>, + <&isom_pinctrl 28 2 2>, + <&ve4_pinctrl 30 15 6>, + <&main2_pinctrl 36 5 6>, + <&ve4_pinctrl 42 21 3>, + <&iso_pinctrl 45 6 6>, + <&ve4_pinctrl 51 24 1>, + <&iso_pinctrl 52 12 1>, + <&ve4_pinctrl 53 25 11>, + <&main2_pinctrl 64 11 28>, + <&ve4_pinctrl 92 36 2>, + <&iso_pinctrl 94 13 19>, + <&iso_pinctrl 128 32 4>, + <&ve4_pinctrl 132 38 13>, + <&iso_pinctrl 145 36 19>, + <&ve4_pinctrl 164 51 2>; + #gpio-cells =3D <2>; + }; + iso_pinctrl: pinctrl@4e000 { compatible =3D "realtek,rtd1625-iso-pinctrl"; reg =3D <0x4e000 0x1a4>; @@ -161,6 +192,14 @@ main2_pinctrl: pinctrl@4f200 { reg =3D <0x4f200 0x50>; }; =20 + iso_m_gpio: gpio@89100 { + compatible =3D "realtek,rtd1625-isom-gpio"; + reg =3D <0x89100 0x30>; + gpio-controller; + gpio-ranges =3D <&isom_pinctrl 0 0 4>; + #gpio-cells =3D <2>; + }; + isom_pinctrl: pinctrl@146200 { compatible =3D "realtek,rtd1625-isom-pinctrl"; reg =3D <0x146200 0x34>; --=20 2.34.1