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Mayer Date: Tue, 12 May 2026 15:00:05 +0200 Subject: [PATCH v3 1/4] dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260512-rzg2-sr-boards-v3-1-f033fc96c906@solid-run.com> References: <20260512-rzg2-sr-boards-v3-0-f033fc96c906@solid-run.com> In-Reply-To: <20260512-rzg2-sr-boards-v3-0-f033fc96c906@solid-run.com> To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jon Nettleton , Mikhail Anikin , Yazan Shhady , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Josua Mayer X-Mailer: b4 0.14.3 X-ClientProxiedBy: FR3P281CA0170.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a0::18) To GVXPR04MB12057.eurprd04.prod.outlook.com (2603:10a6:150:313::24) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: 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5e4c7257-8643-416c-2b15-08deb026724d X-MS-Exchange-CrossTenant-Id: a4a8aaf3-fd27-4e27-add2-604707ce5b82 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=a4a8aaf3-fd27-4e27-add2-604707ce5b82;Ip=[52.17.62.50];Helo=[eu-dlp.cloud-sec-av.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000041.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR04MB10707 Add bindings for various SolidRun boards and System on Module built around Renesas RZ/G2 family of SoCs: - RZ/G2L SoM [1] - RZ/V2L SoM [2] (shares PCB with G2L and has very similar programming model) - RZ/G2LC SoM [3] - RZ/G2UL SoM [4] (shares PCB with G2LC but programming model differs largely) - HummingBoard IIoT [5] (RZ/G2L, RZ/V2L, RZ/G2LC) - HummingBoard Pro [6] (RZ/G2L, RZ/V2L) - HummingBoard Base (Ripple) [7] (RZ/G2L, RZ/V2L, RZ/G2LC, RZ/G2UL) [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= g2l-som/ [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= v2l-som/ [3] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= g2lc-som/ [4] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= g2ul-som/ [5] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/ [6] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2l-sbc/ [7] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2lc-base/ Signed-off-by: Josua Mayer Acked-by: Conor Dooley --- .../devicetree/bindings/soc/renesas/renesas.yaml | 37 ++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index 5c22c51b1533d..889d4c5e8cd1b 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -502,6 +502,14 @@ properties: - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 =20 + - description: SolidRun RZ/G2UL based boards + items: + - enum: + - solidrun,rzg2ul-hummingboard-ripple # SolidRun RZ/G2UL Hum= mingBoard Ripple + - const: solidrun,rzg2ul-sr-som + - const: renesas,r9a07g043u12 # RZ/G2UL Type-2 + - const: renesas,r9a07g043 + - description: RZ/G2{L,LC} (R9A07G044) items: - enum: @@ -513,6 +521,25 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 =20 + - description: SolidRun RZ/G2L based boards + items: + - enum: + - solidrun,rzg2l-hummingboard-iiot # SolidRun RZ/G2L Hummi= ngBoard IIoT + - solidrun,rzg2l-hummingboard-pro # SolidRun RZ/G2L Hummi= ngBoard Pro + - solidrun,rzg2l-hummingboard-ripple # SolidRun RZ/G2L Hummi= ngBoard Ripple + - const: solidrun,rzg2l-sr-som + - const: renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L + - const: renesas,r9a07g044 + + - description: SolidRun RZ/G2LC based boards + items: + - enum: + - solidrun,rzg2lc-hummingboard-iiot # SolidRun RZ/G2LC Hum= mingBoard IIoT + - solidrun,rzg2lc-hummingboard-ripple # SolidRun RZ/G2LC Hum= mingBoard Ripple + - const: solidrun,rzg2lc-sr-som + - const: renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC + - const: renesas,r9a07g044 + - items: - enum: # MYIR Remi Pi SBC (MYB-YG2LX-REMI) @@ -529,6 +556,16 @@ properties: - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L - const: renesas,r9a07g054 =20 + - description: SolidRun RZ/V2L based boards + items: + - enum: + - solidrun,rzv2l-hummingboard-iiot # SolidRun RZ/V2L Hummi= ngBoard IIoT + - solidrun,rzv2l-hummingboard-pro # SolidRun RZ/V2L Hummi= ngBoard Pro + - solidrun,rzv2l-hummingboard-ripple # SolidRun RZ/V2L Hummi= ngBoard Ripple + - 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Mayer Date: Tue, 12 May 2026 15:00:06 +0200 Subject: [PATCH v3 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260512-rzg2-sr-boards-v3-2-f033fc96c906@solid-run.com> References: <20260512-rzg2-sr-boards-v3-0-f033fc96c906@solid-run.com> In-Reply-To: <20260512-rzg2-sr-boards-v3-0-f033fc96c906@solid-run.com> To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jon Nettleton , Mikhail Anikin , Yazan Shhady , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Josua Mayer X-Mailer: b4 0.14.3 X-ClientProxiedBy: FR3P281CA0170.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a0::18) To GVXPR04MB12057.eurprd04.prod.outlook.com (2603:10a6:150:313::24) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 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a09d2d10-04fa-4425-b79a-08deb026799e X-MS-Exchange-CrossTenant-Id: a4a8aaf3-fd27-4e27-add2-604707ce5b82 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=a4a8aaf3-fd27-4e27-add2-604707ce5b82;Ip=[52.17.62.50];Helo=[eu-dlp.cloud-sec-av.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009BA2.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA6PR04MB11945 Add support for the SolidRun RZ/G2L SoM [1] on Hummingboard IIoT [2]. The SoM features: - 2x 1Gbps Ethernet with PHY - eMMC - 1/2GB DDR - WiFi + Bluetooth - SDHI Mux switching between eMMC and Carrier Board The HummingBoard IIoT features: - 3x USB-2.0 Type A connector - 2x 1Gbps RJ45 Ethernet - USB Type-C Console Port - microSD connector - RTC with backup battery - RGB Status LED - 1x M.2 B-Key connector with USB-2.0 + SIM card holder - 1x DSI Display Connector - GPIO header - 2x RS232/RS485 ports (configurable) - 2x CAN Descriptions for eMMC, microSD and RS485 are provided as overlays due to their dependency on configurable mux states. [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= g2l-som/ [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/ Signed-off-by: Josua Mayer --- arch/arm64/boot/dts/renesas/Makefile | 13 + .../dts/renesas/r9a07g044l2-hummingboard-iiot.dts | 16 + .../renesas/rzg2l-hummingboard-iiot-common.dtsi | 572 +++++++++++++++++= ++++ .../renesas/rzg2l-hummingboard-iiot-microsd.dtso | 26 + .../renesas/rzg2l-hummingboard-iiot-rs485-a.dtso | 17 + .../renesas/rzg2l-hummingboard-iiot-rs485-b.dtso | 17 + .../boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi | 49 ++ arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso | 44 ++ arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi | 421 +++++++++++++++ 9 files changed, 1175 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index ca45d2857ea7f..38163ce845e7a 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -169,6 +169,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc-cr= u-csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g044c2-smarc.dtb r9a07g044= c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc-cru-csi-ov5645.dtb =20 +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-hummingboard-iiot.dtb +dtb-$(CONFIG_ARCH_R9A07G044) +=3D rzg2l-sr-som-emmc.dtbo +r9a07g044l2-hummingboard-iiot-emmc-dtbs :=3D r9a07g044l2-hummingboard-iiot= .dtb rzg2l-sr-som-emmc.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-hummingboard-iiot-emmc.dtb +dtb-$(CONFIG_ARCH_R9A07G044) +=3D rzg2l-hummingboard-iiot-microsd.dtbo +r9a07g044l2-hummingboard-iiot-microsd-dtbs :=3D r9a07g044l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-microsd.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-hummingboard-iiot-microsd.dtb +dtb-$(CONFIG_ARCH_R9A07G044) +=3D rzg2l-hummingboard-iiot-rs485-a.dtbo +r9a07g044l2-hummingboard-iiot-rs485-a-dtbs :=3D r9a07g044l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-hummingboard-iiot-rs485-a.dtb +dtb-$(CONFIG_ARCH_R9A07G044) +=3D rzg2l-hummingboard-iiot-rs485-b.dtbo +r9a07g044l2-hummingboard-iiot-rs485-b-dtbs :=3D r9a07g044l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-hummingboard-iiot-rs485-b.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-remi-pi.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts = b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts new file mode 100644 index 0000000000000..eba4f423c8f05 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include "r9a07g044l2.dtsi" +#include "rzg2l-sr-som.dtsi" +#include "rzg2l-hummingboard-iiot.dtsi" + +/ { + compatible =3D "solidrun,rzg2l-hummingboard-iiot", "solidrun,rzg2l-sr-som= ", + "renesas,r9a07g044l2", "renesas,r9a07g044"; + model =3D "SolidRun RZ/G2L HummingBoard IIoT"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dts= i b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi new file mode 100644 index 0000000000000..fbf2e7c393bf3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + */ + +#include +#include +/ { + /* power for M.2 B-Key connector (J6) */ + regulator-m2-b { + compatible =3D "regulator-fixed"; + regulator-name =3D "m2-b"; + gpios =3D <&tca6416_u20 5 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + enable-active-high; + }; + + /* power for M.2 M-Key connector (J4) */ + regulator-m2-m { + compatible =3D "regulator-fixed"; + regulator-name =3D "m2-m"; + gpios =3D <&tca6416_u20 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 3 */ + regulator-vbus-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus2"; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&tca6416_u20 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 4 */ + regulator-vbus-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus3"; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&tca6416_u20 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + aliases { + gpio1 =3D &tca6408_u48; + gpio2 =3D &tca6408_u37; + gpio3 =3D &tca6416_u20; + gpio4 =3D &tca6416_u21; + i2c3 =3D &i2c_exp; + i2c4 =3D &i2c_csi; + i2c5 =3D &i2c_dsi; + i2c6 =3D &i2c_lvds; + rtc0 =3D &carrier_rtc; + rtc1 =3D &pmic; + serial3 =3D &scif3; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + wakeup-event { + interrupts-extended =3D <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>; + label =3D "m2-m-wakeup"; + wakeup-source; + linux,code =3D ; + }; + }; + + can_mux: mux-controller-1 { + compatible =3D "gpio-mux"; + /* default J9-55/57/59/61 to on-board transceivers */ + idle-state =3D <0>; + #mux-control-cells =3D <0>; + /* + * Mux routes CAN bus signals between SoM connector pins, + * expansion connector (J22) and on-board transceivers using + * two GPIO: + * - IO3: 0 =3D on-board transceivers, 1 =3D expansion connector + * - IO4: 0 =3D J9-55/57/59/61, 1 =3D J7-12/16 & J9-54/56 + */ + mux-gpios =3D <&tca6416_u20 3 GPIO_ACTIVE_HIGH>, + <&tca6416_u20 4 GPIO_ACTIVE_HIGH>; + }; + + spi_mux: mux-controller-2 { + compatible =3D "gpio-mux"; + /* default on-board */ + idle-state =3D <0>; + /* + * Mux switches spi bus between on-board tpm + * and expansion connector (J22). + */ + mux-gpios =3D <&tca6416_u21 0 GPIO_ACTIVE_HIGH>; + #mux-control-cells =3D <0>; + }; + + scif1_scif3_b2b_mux: mux-controller-3 { + compatible =3D "gpio-mux"; + /* default on-board */ + idle-state =3D <0>; + #mux-control-cells =3D <0>; + /* + * Mux switches both scif1 and scif3 tx/rx between expansion + * connector (J22) and on-board rs232/rs485 transceivers + * using one GPIO: 0 =3D on-board, 1 =3D connector. + */ + mux-gpios =3D <&tca6416_u20 0 GPIO_ACTIVE_HIGH>; + }; + + scif1_rs_232_485_mux: mux-controller-4 { + compatible =3D "gpio-mux"; + /* default rs232 */ + idle-state =3D <0>; + #mux-control-cells =3D <0>; + /* + * Mux switches scif1 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 =3D rs232, 1 =3D rs485. + */ + mux-gpios =3D <&tca6416_u20 1 GPIO_ACTIVE_HIGH>; + }; + + scif3_rs_232_485_mux: mux-controller-5 { + compatible =3D "gpio-mux"; + /* default rs232 */ + idle-state =3D <0>; + #mux-control-cells =3D <0>; + /* + * Mux switches scif3 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 =3D rs232, 1 =3D rs485. + */ + mux-gpios =3D <&tca6416_u20 2 GPIO_ACTIVE_HIGH>; + }; + + v_1_2: regulator-1-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v2"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + v_3_3: regulator-3-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_dsi_panel: regulator-dsi-panel { + compatible =3D "regulator-fixed"; + regulator-name =3D "dsi-panel"; + gpios =3D <&tca6416_u20 15 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <11200000>; + regulator-min-microvolt =3D <11200000>; + enable-active-high; + }; + + vmmc: regulator-mmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vmmc"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + startup-delay-us =3D <250>; + vin-supply =3D <&v_3_3>; + gpio =3D <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J5003 */ + vbus1: regulator-vbus-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus1"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&tca6416_u20 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill-m2-b-gnss { + compatible =3D "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios =3D <&tca6416_u20 10 GPIO_ACTIVE_LOW>; + label =3D "m2-b gnss"; + radio-type =3D "gps"; + }; + + rfkill-m2-b-wwan { + compatible =3D "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios =3D <&tca6416_u20 9 GPIO_ACTIVE_HIGH>; + label =3D "m2-b radio"; + radio-type =3D "wwan"; + }; +}; + +&ehci1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hub_2_0: hub@1 { + compatible =3D "usb4b4,6502", "usb4b4,6506"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + reset-gpios =3D <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply =3D <&v_3_3>; + vdd-supply =3D <&v_1_2>; + }; + + /* this device is not visible because host supports 2.0 only */ + hub_3_0: hub@2 { + compatible =3D "usb4b4,6500", "usb4b4,6504"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + reset-gpios =3D <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply =3D <&v_3_3>; + vdd-supply =3D <&v_1_2>; + }; +}; + +&i2c0 { + /* highest i2c clock supported by all peripherals is 400kHz */ + + tca6416_u20: gpio@20 { + compatible =3D "ti,tcal6416"; + reg =3D <0x20>; + #gpio-cells =3D <2>; + gpio-controller; + gpio-line-names =3D "TCA_INT/EXT_UART", "TCA_UARTA_232/485", + "TCA_UARTB_232/485", "TCA_INT/EXT_CAN", + "TCA_NXP/REN", "TCA_M.2B_3V3_EN", + "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#", + "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#", + "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#", + "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN", + "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN"; + + m2-b-reset-hog { + gpios =3D <8 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name =3D "m2-b-reset"; + output-low; + }; + + m2-m-reset-hog { + gpios =3D <7 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name =3D "m2-m-reset"; + /* + * M.2 Key-M connector only supports PCI, + * but RZ/G2L(C) has no pci controller. + * Keep any card in reset. + */ + output-high; + }; + }; + + tca6416_u21: gpio@21 { + compatible =3D "ti,tcal6416"; + reg =3D <0x21>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + gpio-line-names =3D "TCA_SPI_TPM/EXT", "TCA_TPM_RST#", + "TCA_I2C_RST", "TCA_RS232_SHTD#", + "TCA_LCD_I2C_RST", "TCA_DIG_OUT1", + "TCA_bDIG_IN1", "TCA_SENS_INT", + "TCA_ALERT#", "TCA_TPM_PIRQ#", + "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN", + "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#", + "", "TCA_POE_AT"; + /* Level triggered irq does not currently work well on RZ/G2L, fall-back= to edge */ + interrupts-extended =3D <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING= >; + + lcd-i2c-reset-hog { + gpios =3D <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + line-name =3D "lcd-i2c-reset"; + output-low; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + */ + gpio-hog; + }; + + lvds-irq-hog { + gpios =3D <13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>; + gpio-hog; + input; + line-name =3D "lvds-irq"; + }; + + m2-m-clkreq-hog { + gpios =3D <12 GPIO_ACTIVE_LOW>; + gpio-hog; + input; + line-name =3D "m2-m-clkreq"; + }; + + rs232_shutdown: rs232-shutdown-hog { + gpios =3D <3 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name =3D "rs232-shutdown"; + output-low; + }; + + sensor-irq-hog { + gpios =3D <7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>; + gpio-hog; + input; + line-name =3D "sensor-irq"; + }; + + tpm-irq-hog { + gpios =3D <9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>; + gpio-hog; + input; + line-name =3D "tpm-irq"; + }; + }; + + led-controller@30 { + compatible =3D "ti,lp5562"; + reg =3D <0x30>; + #address-cells =3D <1>; + #size-cells =3D <0>; + /* use internal clock, could use external generated by rtc */ + clock-mode =3D /bits/ 8 <1>; + + multi-led@0 { + reg =3D <0x0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + color =3D ; + label =3D "D7"; + + led@0 { + reg =3D <0x0>; + color =3D ; + led-cur =3D /bits/ 8 <0x32>; + max-cur =3D /bits/ 8 <0x64>; + }; + + led@1 { + reg =3D <0x1>; + color =3D ; + led-cur =3D /bits/ 8 <0x19>; + max-cur =3D /bits/ 8 <0x32>; + }; + + led@2 { + reg =3D <0x2>; + color =3D ; + led-cur =3D /bits/ 8 <0x19>; + max-cur =3D /bits/ 8 <0x32>; + }; + }; + + led@3 { + reg =3D <0x3>; + chan-name =3D "D8"; + color =3D ; + label =3D "D8"; + led-cur =3D /bits/ 8 <0x19>; + max-cur =3D /bits/ 8 <0x64>; + }; + }; + + light-sensor@44 { + compatible =3D "isil,isl29023"; + reg =3D <0x44>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J500= 7) */ + interrupts-extended =3D <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + }; + + accelerometer@53 { + compatible =3D "adi,adxl345"; + reg =3D <0x53>; + interrupts-extended =3D <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J500= 7) */ + interrupt-names =3D "INT1"; + }; + + carrier_eeprom: eeprom@57 { + compatible =3D "atmel,24c02"; + reg =3D <0x57>; + pagesize =3D <8>; + }; + + carrier_rtc: rtc@69 { + compatible =3D "abracon,ab1805"; + reg =3D <0x69>; + /* + * AM1805 RTC used on this board has only nTIRQ pins wired, + * which is for countdown timer irqs only. + * Driver does not support this, disable for now. + * + * interrupts-extended =3D <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>; + */ + abracon,tc-diode =3D "schottky"; + abracon,tc-resistor =3D <3>; + }; +}; + +&i2c1 { + /* highest i2c clock supported by all peripherals is 400kHz */ + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + /* + * This reset is open drain with HW 10k pull-up resistor, + * but reset core does not support GPIO_OPEN_DRAIN flag. + * The pull-up and GPIO voltages match, push-pull is safe. + */ + reset-gpios =3D <&tca6416_u21 2 GPIO_ACTIVE_LOW>; + + /* channel 0 routed to expansion connector (J22) */ + i2c_exp: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + /* channel 1 routed to mipi-csi connector (J23) */ + i2c_csi: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + /* channel 2 routed to mipi-dsi connector (J25) */ + i2c_dsi: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tca6408_u48: gpio@21 { + compatible =3D "ti,tca6408"; + reg =3D <0x21>; + #gpio-cells =3D <2>; + gpio-line-names =3D "CAM_RST#", "DSI_RESET", + "DSI_STBYB", "DSI_PWM_BL", + "DSI_L/R", "DSI_U/D", + "DSI_CTP_/RST", "CAM_TRIG"; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios =3D <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + gpio-controller; + }; + }; + + /* channel 2 routed to lvds connector (J24) */ + i2c_lvds: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tca6408_u37: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + #gpio-cells =3D <2>; + gpio-line-names =3D "SELB", "LVDS_RESET", + "LVDS_STBYB", "LVDS_PWM_BL", + "LVDS_L/R", "LVDS_U/D", + "LVDS_CTP_/RST", ""; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios =3D <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + gpio-controller; + }; + }; + }; +}; + +&phy0 { + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* LED_0 pin */ + led@0 { + reg =3D <0>; + color =3D ; + default-state =3D "keep"; + function =3D LED_FUNCTION_LAN; + }; + }; +}; + +&pinctrl { + /* UARTA */ + scif1_pins: scif1 { + pinmux =3D , /* SCIF1_RXD */ + ; /* SCIF1_TXD */ + }; + + /* UARTB */ + scif3_pins: scif3 { + pinmux =3D , /* SCIF3_RXD */ + ; /* SCIF3_TXD */ + }; +}; + +&scif1 { + pinctrl-0 =3D <&scif1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&scif3 { + pinctrl-0 =3D <&scif3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&spi1 { + /* native cs does not support cs persistence required for tpm */ + cs-gpios =3D <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>; + num-cs =3D <1>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + spi1_muxed: spi@0 { + compatible =3D "spi-mux"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + mux-controls =3D <&spi_mux>; + /* mux bandwidth is 2GHz, soc max. spi clock is P0/2 =3D 50MHz */ + spi-max-frequency =3D <50000000>; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + reg =3D <0>; + interrupts-extended =3D <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency =3D <43000000>; + }; + }; +}; + +&usb2_phy0 { + dr_mode =3D "host"; + vbus-supply =3D <&vbus1>; +}; + +&usb2_phy1 { + dr_mode =3D "host"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dt= so b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso new file mode 100644 index 0000000000000..aa85054efa0c4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* +* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM SD +* +* Copyright (C) 2024 SolidRun Ltd. +*/ + +/dts-v1/; +/plugin/; + +#include +#include + +&sdhi0 { + bus-width =3D <4>; + full-pwr-cycle; + mux-states =3D <&sdhi0_mux 1>; + pinctrl-0 =3D <&sdhi0_pins>, <&sdhi0_cd_pins>; + pinctrl-1 =3D <&sdhi0_uhs_pins>, <&sdhi0_cd_pins>; + pinctrl-names =3D "default", "state_uhs"; + sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply =3D <&vmmc>; + vqmmc-supply =3D <®_pmic_ldo1>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dt= so b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso new file mode 100644 index 0000000000000..4bcb22d518f05 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connect= or J5004. + * + * Because Renesas uart driver does not support rs485, + * users must manually toggle P41_1 between RX & TX. + */ + +/dts-v1/; +/plugin/; + +&scif1_rs_232_485_mux { + /* select rs485 */ + idle-state =3D <1>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dt= so b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso new file mode 100644 index 0000000000000..6f460b3e0b256 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connect= or J5004. + * + * Because Renesas uart driver does not support rs485, + * users must manually toggle P41_0 between RX & TX. + */ + +/dts-v1/; +/plugin/; + +&scif3_rs_232_485_mux { + /* select rs485 */ + idle-state =3D <1>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi b/arc= h/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi new file mode 100644 index 0000000000000..22f066079e69a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + */ + +#include "rzg2l-hummingboard-iiot-common.dtsi" + +&canfd { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&can0_pins>, <&can1_pins>; + status =3D "okay"; + + channel0 { + status =3D "okay"; + }; + + channel1 { + status =3D "okay"; + }; +}; + +&phy1 { + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* LED_0 pin */ + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + }; +}; + +&pinctrl { + /* CANA */ + can0_pins: can0 { + pinmux =3D , /* CAN0_TX */ + ; /* CAN0_RX */ + }; + + /* CANB */ + can1_pins: can1 { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso b/arch/arm6= 4/boot/dts/renesas/rzg2l-sr-som-emmc.dtso new file mode 100644 index 0000000000000..c59c7e7e70bfa --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* +* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM eMMC +* +* Copyright (C) 2024 SolidRun Ltd. +*/ + +/dts-v1/; +/plugin/; + +#include +#include + +®_pmic_ldo1 { + /* + * This ldo can switch mmc host controller io voltage between + * 1.8V and 3.3V. The eMMC IO voltage however is supplied from + * reg_pmic_buck3 which is fixed at 1.8V. + * Lower this ldo maximum voltage to 1.8V to prevent setting 3.3V. + */ + regulator-max-microvolt =3D <1800000>; +}; + +&sdhi0 { + /* + * Host controller and eMMC have separate io voltage regulators: + * reg_pmic_ldo1 (1.8V/3.3V); reg_pmic_buck3 (1.8V only). + * Link to the switchable regulator ensuring that it gets configured. + */ + vqmmc-supply =3D <®_pmic_ldo1>; + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mux-states =3D <&sdhi0_mux 0>; + non-removable; + no-sdio; + pinctrl-0 =3D <&sdhi0_uhs_pins>, <&sdhi0_rst_pins>; + pinctrl-1 =3D <&sdhi0_uhs_pins>, <&sdhi0_rst_pins>; + pinctrl-names =3D "default", "state_uhs"; + vmmc-supply =3D <®_pmic_buck4>; + /* emmc io voltage is hard-wired for 1.8V, disable sd modes */ + no-sd; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boo= t/dts/renesas/rzg2l-sr-som.dtsi new file mode 100644 index 0000000000000..297256299e7a8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L Solidrun SoM + * + * Copyright 2023 SolidRun Ltd. + * Copyright 2025 Josua Mayer + */ + +#include +#include +/ { + aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; + gpio0 =3D &pinctrl; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c3; + mmc0 =3D &sdhi0; + mmc1 =3D &sdhi1; + rtc0 =3D &pmic; + serial0 =3D &scif0; + serial1 =3D &scif1; + serial2 =3D &scif2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + sdhi0_mux: mux-controller-0 { + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + #mux-state-cells =3D <1>; + /* + * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between + * on-SoM eMMC and board-to-board connector using one gpio: + * 1 =3D connector, 0 =3D eMMC. + */ + mux-gpios =3D <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_LOW>; + }; + + clk_pmic_32k: pmic-32k-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + + reg_pmic_buck1: regulator-pmic-buck1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + }; + + reg_pmic_buck3: regulator-pmic-buck3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_pmic_buck4: regulator-pmic-buck4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_pmic_ldo1: regulator-pmic-ldo1 { + compatible =3D "regulator-gpio"; + regulator-name =3D "pmic-ldo1"; + gpios =3D <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + states =3D <3300000 1>, <1800000 0>; + }; + + reg_pmic_ldo2: regulator-pmic-ldo2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-ldo2"; + /* + * This ldo can switch mmc host controller io voltage between + * 1.8V and 3.3V by assembly option of pull-up / pull-dow. + * Default assembly is 3.3V. + */ + regulator-min-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + mmp_reserved: linux,multimedia@68000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x68000000 0x0 0x8000000>; + reusable; + }; + + global_cma: linux,cma@58000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x58000000 0x0 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + sdhi1_pwrseq: sdhi1-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>; + }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + + memory@40000000 { + reg =3D <0x0 0x40000000 0x0 0x20000000>; + device_type =3D "memory"; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +ð0 { + phy-handle =3D <&phy0>; + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + /* + * ravb driver does not configure mac internal delays for RZ/G2L(C), + * instead delays are added by the MxL86110 phy driver. + */ + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + interrupts-extended =3D <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ð1 { + phy-handle =3D <&phy1>; + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + /* + * ravb driver does not configure mac internal delays for RZ/G2L(C), + * instead delays are added by the MxL86110 phy driver. + */ + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + phy1: ethernet-phy@4 { + reg =3D <4>; + interrupts-extended =3D <&pinctrl RZG2L_GPIO(42, 4) IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal_clk { + clock-frequency =3D <24000000>; +}; + +&gpu { + mali-supply =3D <®_pmic_buck1>; +}; + +&i2c0 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + eeprom: eeprom@50 { + compatible =3D "atmel,24c01"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pmic: pmic@12 { + compatible =3D "renesas,raa215300"; + reg =3D <0x12>, <0x6f>; + reg-names =3D "main", "rtc"; + clocks =3D <&x2>; + clock-names =3D "xin"; + }; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&ostm1 { + status =3D "okay"; +}; + +&ostm2 { + status =3D "okay"; +}; + +&phyrst { + status =3D "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux =3D , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux =3D , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + + i2c0_pins: i2c0 { + input-enable; + pins =3D "RIIC0_SDA", "RIIC0_SCL"; + }; + + i2c1_pins: i2c1 { + input-enable; + pins =3D "RIIC1_SDA", "RIIC1_SCL"; + }; + + i2c3_pins: i2c3 { + pinmux =3D , /* RIIC3_SDA */ + ; /* RIIC3_SCL */ + }; + + qspi0_pins: qspi0 { + pins =3D "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3", + "QSPI0_SPCLK", "QSPI0_SSL"; + power-source =3D <1800>; + }; + + scif0_pins: scif0 { + pinmux =3D , /* SCIF0_TXD */ + ; /* SCIF0_RXD */ + }; + + scif2_pins: scif2 { + pinmux =3D , /* SCIF2_TXD */ + , /* SCIF2_RXD */ + , /* SCIF2_CTS# */ + ; /* SCIF2_RTS# */ + }; + + sdhi0_pins: sdhi0 { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD"; + power-source =3D <3300>; + }; + + sdhi0_uhs_pins: sdhi0 { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sdhi0_cd_pins: sdhi0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */ + sdhi0_rst_pins: sdhi0-rst { + pins =3D "SD0_RST#"; + power-source =3D <1800>; + }; + + sdhi1_pins: sdhi1 { + pins =3D "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", + "SD1_CLK", "SD1_CMD"; + power-source =3D <3300>; + }; + + spi1_pins: spi1 { + pinmux =3D , /* RSPI1_MISO */ + , /* RSPI1_MOSI# */ + ; + }; + + spi1_cs_pins: spi1-cs { + pinmux =3D ; /* RSPI1_SSL */ + }; + + usb0_vbus_pins: usb0-vbus { + pinmux =3D ; /* USB0_VBUSEN */ + }; + + usb1_vbus_pins: usb1-vbus { + pinmux =3D ; /* USB1_VBUSEN */ + }; +}; + +&sbc { + pinctrl-0 =3D <&qspi0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "winbond,w25q80bl", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + }; +}; + +&scif0 { + pinctrl-0 =3D <&scif0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; 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The SoM features: - 2x 1Gbps Ethernet with PHY - eMMC - 1/2GB DDR - WiFi + Bluetooth - SDHI Mux switching between eMMC and Carrier Board The HummingBoard IIoT features: - 3x USB-2.0 Type A connector - 2x 1Gbps RJ45 Ethernet - USB Type-C Console Port - microSD connector - RTC with backup battery - RGB Status LED - 1x M.2 B-Key connector with USB-2.0 + SIM card holder - 1x DSI Display Connector - GPIO header - 2x RS232/RS485 ports (configurable) - 2x CAN The RZ-V2L SoM shares PCB with RZ/G2L, differing only in the SoC itself. V2L is adding a powerful DRP-AI NPU which G2L lacks. Due to the similarities most code is shared, including DT overlays for eMMC, microSD, and RS485. [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= v2l-som/ [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/ Signed-off-by: Josua Mayer --- arch/arm64/boot/dts/renesas/Makefile | 11 +++++++++++ .../boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts | 16 ++++++++++++= ++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 38163ce845e7a..cff17cb8574a3 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -188,6 +188,17 @@ dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc-cr= u-csi-ov5645.dtbo r9a07g044l2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g044l2-smarc.dtb r9a07g044= l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc-cru-csi-ov5645.dtb =20 +dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-hummingboard-iiot.dtb +r9a07g054l2-hummingboard-iiot-emmc-dtbs :=3D r9a07g054l2-hummingboard-iiot= .dtb rzg2l-sr-som-emmc.dtbo +dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-hummingboard-iiot-emmc.dtb +r9a07g054l2-hummingboard-iiot-microsd-dtbs :=3D r9a07g054l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-microsd.dtbo +dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-hummingboard-iiot-microsd.dtb +dtb-$(CONFIG_ARCH_R9A07G054) +=3D rzg2l-hummingboard-iiot-rs485-a.dtbo +r9a07g054l2-hummingboard-iiot-rs485-a-dtbs :=3D r9a07g054l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo +dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-hummingboard-iiot-rs485-a.dtb +dtb-$(CONFIG_ARCH_R9A07G054) +=3D rzg2l-hummingboard-iiot-rs485-b.dtbo +r9a07g054l2-hummingboard-iiot-rs485-b-dtbs :=3D r9a07g054l2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo +dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-hummingboard-iiot-rs485-b.dtb dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) +=3D r9a07g054l2-smarc-cru-csi-ov5645.dtbo r9a07g054l2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g054l2-smarc.dtb r9a07g054= l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts = b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts new file mode 100644 index 0000000000000..d77a6ff163bea --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; 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The SoM features: - 1Gbps Ethernet with PHY - eMMC - 1/2GB DDR - WiFi + Bluetooth - SDHI Mux switching between eMMC and Carrier Board The HummingBoard IIoT features: - 3x USB-2.0 Type A connector - 1x 1Gbps RJ45 Ethernet - USB Type-C Console Port - microSD connector - RTC with backup battery - RGB Status LED - 1x M.2 B-Key connector with USB-2.0 + SIM card holder - 1x DSI Display Connector - GPIO header - 2x RS232/RS485 ports (configurable) The RZ/G2LC SoM was designed to be pin compatible to G2L SoM, with slightly reduced feature set. Descriptions for eMMC, microSD, and RS485 are shared with G2L. [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-= g2lc-som/ [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hum= mingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/ Signed-off-by: Josua Mayer --- arch/arm64/boot/dts/renesas/Makefile | 9 + .../dts/renesas/r9a07g044c2-hummingboard-iiot.dts | 20 ++ arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi | 374 +++++++++++++++++= ++++ 3 files changed, 403 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index cff17cb8574a3..04a68d472064f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -164,6 +164,15 @@ dtb-$(CONFIG_ARCH_R9A07G043) +=3D r9a07g043u11-smarc-d= u-adv7513.dtb r9a07g043u11-smarc-pmod-dtbs :=3D r9a07g043u11-smarc.dtb r9a07g043-smarc-p= mod.dtbo dtb-$(CONFIG_ARCH_R9A07G043) +=3D r9a07g043u11-smarc-pmod.dtb =20 +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-hummingboard-iiot.dtb +r9a07g044c2-hummingboard-iiot-emmc-dtbs :=3D r9a07g044c2-hummingboard-iiot= .dtb rzg2l-sr-som-emmc.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-hummingboard-iiot-emmc.dtb +r9a07g044c2-hummingboard-iiot-microsd-dtbs :=3D r9a07g044c2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-microsd.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-hummingboard-iiot-microsd.dtb +r9a07g044c2-hummingboard-iiot-rs485-a-dtbs :=3D r9a07g044c2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-hummingboard-iiot-rs485-a.dtb +r9a07g044c2-hummingboard-iiot-rs485-b-dtbs :=3D r9a07g044c2-hummingboard-i= iot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-hummingboard-iiot-rs485-b.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc-cru-csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g044c2-smarc.dtb r9a07g044= c2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts = b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts new file mode 100644 index 0000000000000..06d9d031cbe91 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include "r9a07g044c2.dtsi" +#include "rzg2lc-sr-som.dtsi" +#include "rzg2l-hummingboard-iiot-common.dtsi" + +/ { + compatible =3D "solidrun,rzg2lc-hummingboard-iiot", "solidrun,rzg2lc-sr-s= om", + "renesas,r9a07g044c2", "renesas,r9a07g044"; + model =3D "SolidRun RZ/G2LC HummingBoard IIoT"; +}; + +&vmmc { + gpio =3D <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/bo= ot/dts/renesas/rzg2lc-sr-som.dtsi new file mode 100644 index 0000000000000..0505af6926a5e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC Solidrun SOM + * + * Copyright 2023 SolidRun Ltd. + * Copyright 2025 Josua Mayer + */ + +#include +#include +/ { + aliases { + ethernet0 =3D ð0; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + mmc0 =3D &sdhi0; + mmc1 =3D &sdhi1; + rtc0 =3D &pmic; + serial0 =3D &scif0; + serial1 =3D &scif1; + serial2 =3D &scif2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + sdhi0_mux: mux-controller-0 { + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + #mux-state-cells =3D <1>; + /* + * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between + * on-SoM eMMC and board-to-board connector using one gpio: + * 0 =3D connector, 1 =3D eMMC. + */ + mux-gpios =3D <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>; + }; + + reg_pmic_buck1: regulator-pmic-buck1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + }; + + reg_pmic_buck3: regulator-pmic-buck3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_pmic_buck4: regulator-pmic-buck4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-buck4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_pmic_ldo1: regulator-pmic-ldo1 { + compatible =3D "regulator-gpio"; + regulator-name =3D "pmic-ldo1"; + gpios =3D <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + states =3D <3300000 1>, <1800000 0>; + }; + + reg_pmic_ldo2: regulator-pmic-ldo2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pmic-ldo2"; + /* + * This ldo can switch mmc host controller io voltage between + * 1.8V and 3.3V by assembly option of pull-up / pull-dow. + * Default assembly is 3.3V. + */ + regulator-min-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + mmp_reserved: linux,multimedia@68000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x68000000 0x0 0x8000000>; + reusable; + }; + + global_cma: linux,cma@58000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x58000000 0x0 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + sdhi1_pwrseq: sdhi1-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>; + }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + + memory@40000000 { + reg =3D <0x0 0x40000000 0x0 0x20000000>; + device_type =3D "memory"; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +ð0 { + phy-handle =3D <&phy0>; + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + /* + * ravb driver does not configure mac internal delays for RZ/G2L(C), + * instead delays are added by the ADIN1200 phy driver. + */ + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + interrupts-extended =3D <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal_clk { + clock-frequency =3D <24000000>; +}; + +&gpu { + mali-supply =3D <®_pmic_buck1>; +}; + +&i2c0 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + eeprom: eeprom@50 { + compatible =3D "atmel,24c01"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pmic: pmic@12 { + compatible =3D "renesas,raa215300"; + reg =3D <0x12>, <0x6f>; + reg-names =3D "main", "rtc"; + clocks =3D <&x2>; + clock-names =3D "xin"; + }; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&ostm1 { + status =3D "okay"; +}; + +&ostm2 { + status =3D "okay"; +}; + +&phyrst { + status =3D "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux =3D , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + i2c0_pins: i2c0 { + input-enable; + pins =3D "RIIC0_SDA", "RIIC0_SCL"; + }; + + i2c1_pins: i2c1 { + input-enable; + pins =3D "RIIC1_SDA", "RIIC1_SCL"; + }; + + i2c2_pins: i2c2 { + pinmux =3D , /* RIIC2_SDA */ + ; /* RIIC2_SCL */ + }; + + qspi0_pins: qspi0 { + pins =3D "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3", + "QSPI0_SPCLK", "QSPI0_SSL"; + power-source =3D <1800>; + }; + + scif0_pins: scif0 { + pinmux =3D , /* SCIF0_TXD */ + ; /* SCIF0_RXD */ + }; + + scif2_pins: scif2 { + pinmux =3D , /* SCIF2_TXD */ + , /* SCIF2_RXD */ + , /* SCIF2_CTS# */ + ; /* SCIF2_RTS# */ + }; + + sdhi0_pins: sdhi0 { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD"; + power-source =3D <3300>; + }; + + sdhi0_uhs_pins: sdhi0 { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sdhi0_cd_pins: sdhi0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */ + sdhi0_rst_pins: sdhi0-rst { + pins =3D "SD0_RST#"; + power-source =3D <1800>; + }; + + sdhi1_pins: sdhi1 { + pins =3D "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", + "SD1_CLK", "SD1_CMD"; + power-source =3D <3300>; + }; + + spi1_pins: spi1 { + pinmux =3D , /* RSPI1_MISO */ + , /* RSPI1_MOSI# */ + ; /* RSPI1_CK# */ + }; + + spi1_cs_pins: spi1-cs { + pinmux =3D ; /* RSPI1_SSL */ + }; + + usb0_vbus_pins: usb0-vbus { + pinmux =3D ; /* USB0_VBUSEN */ + }; +}; + +&sbc { + pinctrl-0 =3D <&qspi0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "winbond,w25q80bl", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + }; +}; + +&scif0 { + pinctrl-0 =3D <&scif0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&scif2 { + pinctrl-0 =3D <&scif2_pins>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; +}; + +/* WiFi */ +&sdhi1 { + /* Murata 1YN max rate is 50MHz */ + max-frequency =3D <50000000>; + bus-width =3D <4>; + cap-sdio-irq; + mmc-pwrseq =3D <&sdhi1_pwrseq>; + non-removable; + no-1-8-v; + no-sd; + pinctrl-0 =3D <&sdhi1_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <®_pmic_buck4>; + /* + * Host controller IO voltage is provided from reg_pmic_ldo2, + * WiFi module IO voltage from reg_pmic_buck4. + * Neither is configurable at run-time so either can be set here. + */ + vqmmc-supply =3D <®_pmic_ldo2>; + status =3D "okay"; +}; + +&usb2_phy0 { + vbus-supply =3D <&usb0_vbus_otg>; + status =3D "okay"; +}; + +&usb2_phy1 { + status =3D "okay"; +}; + +&wdt0 { + status =3D "okay"; +}; --=20 2.51.0