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Fortunately, VESA Display Monitor Timing Standard allows +/-0.5% pixel clock rate deviation for timings. So, for those display modes read from EDID through a bridge with DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID operation bit masks set, pixel clock rate could be adjusted to match with the PLL frequency(for the above example, the pixel clock rate is adjusted to be 148.444444MHz with about -0.03% deviation from the 148.5MHz nominal rate so that the adjusted rate matches with the 445.333333MHz PLL frequency). Instead of checking the last bridge's operation bit masks against DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID to determine if allowing +/-0.5% pixel clock rate deviation, check any bridge after this bridge, because the last bridge is usually a display connector bridge without any operation bit mask when the clock rate deviation is allowed. Fixes: ce62f8ea7e3f ("drm/bridge: imx: Add i.MX93 MIPI DSI support") Fixes: 5849eff7f067 ("drm/bridge: imx93-mipi-dsi: use drm_bridge_chain_get_= last_bridge()") Reviewed-by: Frank Li Signed-off-by: Liu Ying --- Changes in v2: - Collect Frank's R-b tag. - Add an explanation to commit message about the reason why mode validation checks bridge's operation bit masks. (Dmitry) - Copy Dmitry. - Link to v1: https://lore.kernel.org/r/20260227-imx93-mipi-dsi-fix-mode-va= lidation-v1-1-a9cd67991280@nxp.com To: Liu Ying To: Andrzej Hajda To: Neil Armstrong To: Robert Foss To: Laurent Pinchart To: Jonas Karlman To: Jernej Skrabec To: Maarten Lankhorst To: Maxime Ripard To: Thomas Zimmermann To: David Airlie To: Simona Vetter To: Frank Li To: Sascha Hauer To: Pengutronix Kernel Team To: Fabio Estevam To: Luca Ceresoli Cc: Dmitry Baryshkov Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 29 ++++++++++++++++---------= ---- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c b/drivers/gpu/drm/= bridge/imx/imx93-mipi-dsi.c index 8f312f9edf97..6d65df9ed970 100644 --- a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c @@ -493,21 +493,24 @@ static enum drm_mode_status imx93_dsi_validate_mode(struct imx93_dsi *dsi, const struct drm_display_mo= de *mode) { struct drm_bridge *dmd_bridge =3D dw_mipi_dsi_get_bridge(dsi->dmd); - struct drm_bridge *last_bridge __free(drm_bridge_put) =3D - drm_bridge_chain_get_last_bridge(dmd_bridge->encoder); =20 - if ((last_bridge->ops & DRM_BRIDGE_OP_DETECT) && - (last_bridge->ops & DRM_BRIDGE_OP_EDID)) { - unsigned long pixel_clock_rate =3D mode->clock * 1000; - unsigned long rounded_rate; + drm_for_each_bridge_in_chain_from(dmd_bridge, bridge) { + if ((bridge->ops & DRM_BRIDGE_OP_DETECT) && + (bridge->ops & DRM_BRIDGE_OP_EDID)) { + unsigned long pixel_clock_rate =3D mode->clock * 1000; + unsigned long rounded_rate; =20 - /* Allow +/-0.5% pixel clock rate deviation */ - rounded_rate =3D clk_round_rate(dsi->clk_pixel, pixel_clock_rate); - if (rounded_rate < pixel_clock_rate * 995 / 1000 || - rounded_rate > pixel_clock_rate * 1005 / 1000) { - dev_dbg(dsi->dev, "failed to round clock for mode " DRM_MODE_FMT "\n", - DRM_MODE_ARG(mode)); - return MODE_NOCLOCK; + /* Allow +/-0.5% pixel clock rate deviation */ + rounded_rate =3D clk_round_rate(dsi->clk_pixel, pixel_clock_rate); + if (rounded_rate < pixel_clock_rate * 995 / 1000 || + rounded_rate > pixel_clock_rate * 1005 / 1000) { + dev_dbg(dsi->dev, + "failed to round clock for mode " DRM_MODE_FMT "\n", + DRM_MODE_ARG(mode)); + return MODE_NOCLOCK; + } + + break; } } =20 --- base-commit: 877552aa875839314afad7154b5a561889e87ea9 change-id: 20260227-imx93-mipi-dsi-fix-mode-validation-425c872a2493 Best regards, -- =20 Regards, Liu Ying