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The trace events cover UART termios configuration, clock setup, modem control state, interrupt status, and TX/RX data, making it easier to diagnose communication issues in the field. Signed-off-by: Praveen Talari Reviewed-by: Konrad Dybcio --- v1->v2: - Removed multiple TX/RX trace events, instead used DECLARE_EVENT_CLASS and DEFINE_EVENT. --- include/trace/events/qcom_geni_serial.h | 172 ++++++++++++++++++++++++++++= ++++ 1 file changed, 172 insertions(+) diff --git a/include/trace/events/qcom_geni_serial.h b/include/trace/events= /qcom_geni_serial.h new file mode 100644 index 000000000000..5e23827881d0 --- /dev/null +++ b/include/trace/events/qcom_geni_serial.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM qcom_geni_serial + +#if !defined(_TRACE_QCOM_GENI_SERIAL_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_QCOM_GENI_SERIAL_H + +#include +#include + +TRACE_EVENT(geni_serial_set_termios, + TP_PROTO(struct device *dev, unsigned int baud, + unsigned int bits_per_char, u32 tx_trans_cfg, + u32 tx_parity_cfg, u32 rx_trans_cfg, + u32 rx_parity_cfg, u32 stop_bit_len), + TP_ARGS(dev, baud, bits_per_char, tx_trans_cfg, tx_parity_cfg, + rx_trans_cfg, rx_parity_cfg, stop_bit_len), + + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(unsigned int, baud) + __field(unsigned int, bits_per_char) + __field(u32, tx_trans_cfg) + __field(u32, tx_parity_cfg) + __field(u32, rx_trans_cfg) + __field(u32, rx_parity_cfg) + __field(u32, stop_bit_len) + ), + + TP_fast_assign(__assign_str(name); + __entry->baud =3D baud; + __entry->bits_per_char =3D bits_per_char; + __entry->tx_trans_cfg =3D tx_trans_cfg; + __entry->tx_parity_cfg =3D tx_parity_cfg; + __entry->rx_trans_cfg =3D rx_trans_cfg; + __entry->rx_parity_cfg =3D rx_parity_cfg; + __entry->stop_bit_len =3D stop_bit_len; + ), + + TP_printk("%s: baud=3D%u bpc=3D%u tx_trans=3D0x%08x tx_par=3D0x%08x r= x_trans=3D0x%08x rx_par=3D0x%08x stop=3D%u", + __get_str(name), __entry->baud, __entry->bits_per_char, + __entry->tx_trans_cfg, __entry->tx_parity_cfg, + __entry->rx_trans_cfg, __entry->rx_parity_cfg, + __entry->stop_bit_len) +); + +TRACE_EVENT(geni_serial_clk_cfg, + TP_PROTO(struct device *dev, unsigned int desired_rate, + unsigned long clk_rate, unsigned int clk_div, + unsigned int clk_idx), + TP_ARGS(dev, desired_rate, clk_rate, clk_div, clk_idx), + + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(unsigned int, desired_rate) + __field(unsigned long, clk_rate) + __field(unsigned int, clk_div) + __field(unsigned int, clk_idx) + ), + + TP_fast_assign(__assign_str(name); + __entry->desired_rate =3D desired_rate; + __entry->clk_rate =3D clk_rate; + __entry->clk_div =3D clk_div; + __entry->clk_idx =3D clk_idx; + ), + + TP_printk("%s: desired_rate=3D%u clk_rate=3D%lu clk_div=3D%u clk_idx= =3D%u", + __get_str(name), __entry->desired_rate, __entry->clk_rate, + __entry->clk_div, __entry->clk_idx) +); + +TRACE_EVENT(geni_serial_irq, + TP_PROTO(struct device *dev, u32 m_irq, u32 s_irq, + u32 dma_tx, u32 dma_rx), + TP_ARGS(dev, m_irq, s_irq, dma_tx, dma_rx), + + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(u32, m_irq) + __field(u32, s_irq) + __field(u32, dma_tx) + __field(u32, dma_rx) + ), + + TP_fast_assign(__assign_str(name); + __entry->m_irq =3D m_irq; + __entry->s_irq =3D s_irq; + __entry->dma_tx =3D dma_tx; + __entry->dma_rx =3D dma_rx; + ), + + TP_printk("%s: m_irq=3D0x%08x s_irq=3D0x%08x dma_tx=3D0x%08x dma_rx= =3D0x%08x", + __get_str(name), __entry->m_irq, __entry->s_irq, + __entry->dma_tx, __entry->dma_rx) +); + +DECLARE_EVENT_CLASS(geni_serial_data, + + TP_PROTO(struct device *dev, const u8 *buf, unsigned int len), + + TP_ARGS(dev, buf, len), + + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(unsigned int, len) + __dynamic_array(u8, data, len) + ), + + TP_fast_assign(__assign_str(name); + __entry->len =3D len; + memcpy(__get_dynamic_array(data), buf, len); + ), + + TP_printk("%s: len=3D%u data=3D%s", + __get_str(name), __entry->len, + __print_hex(__get_dynamic_array(data), __entry->len)) +); + +DEFINE_EVENT(geni_serial_data, geni_serial_tx_data, + + TP_PROTO(struct device *dev, const u8 *buf, unsigned int len), + + TP_ARGS(dev, buf, len) + +); + +DEFINE_EVENT(geni_serial_data, geni_serial_rx_data, + + TP_PROTO(struct device *dev, const u8 *buf, unsigned int len), + + TP_ARGS(dev, buf, len) + +); + +TRACE_EVENT(geni_serial_set_mctrl, + TP_PROTO(struct device *dev, unsigned int mctrl, + u32 uart_manual_rfr), + TP_ARGS(dev, mctrl, uart_manual_rfr), + + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(unsigned int, mctrl) + __field(u32, uart_manual_rfr) + ), + + TP_fast_assign(__assign_str(name); + __entry->mctrl =3D mctrl; + __entry->uart_manual_rfr =3D uart_manual_rfr; + ), + + TP_printk("%s: mctrl=3D0x%04x uart_manual_rfr=3D0x%08x", + __get_str(name), __entry->mctrl, __entry->uart_manual_rfr) +); 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Trace hooks are added at key points including termios and clock configuration, manual control get/set, interrupt handling, and data TX/RX paths. Usage examples: Enable all serial traces: echo 1 > /sys/kernel/debug/tracing/events/qcom_geni_serial/enable cat /sys/kernel/debug/tracing/trace_pipe Example trace output: 2517.938432: geni_serial_clk_cfg: a94000.serial: desired_rate=3D1843200 clk_rate=3D7372800 clk_div=3D4 clk_idx=3D0 2517.938753: geni_serial_irq: a94000.serial: m_irq=3D0x88800000 s_irq=3D0x08000111 dma_tx=3D0x00000000 dma_rx=3D0x00000000 2517.938803: geni_serial_set_termios: a94000.serial: baud=3D115200 bpc=3D8 tx_trans=3D0x00000002 tx_par=3D0x00000000 rx_trans=3D0x00000000 rx_par=3D0x00000000 stop=3D0 2517.938807: geni_serial_set_mctrl: a94000.serial: mctrl=3D0x8006 uart_manual_rfr=3D0x00000000 2517.938818: geni_serial_get_mctrl: a94000.serial: mctrl=3D0x0160 geni_ios=3D0x00000001 2517.939165: geni_serial_irq: a94000.serial: m_irq=3D0x00400000 s_irq=3D0x00000000 dma_tx=3D0x00000000 dma_rx=3D0x00000000 2517.939592: geni_serial_tx_data: a94000.serial: tx_len=3D8 data=3D61 62 63 64 65 66 67 68 2517.940610: geni_serial_irq: a94000.serial: m_irq=3D0x00000001 s_irq=3D0x00000000 dma_tx=3D0x00000003 dma_rx=3D0x00000000 2517.942174: geni_serial_irq: a94000.serial: m_irq=3D0x08000000 s_irq=3D0x08000100 dma_tx=3D0x00000000 dma_rx=3D0x00000003 2517.942323: geni_serial_rx_data: a94000.serial: rx_len=3D8 data=3D61 62 63 64 65 66 67 68 2517.942680: geni_serial_set_mctrl: a94000.serial: mctrl=3D0x8000 uart_manual_rfr=3D0x80000002 Signed-off-by: Praveen Talari Reviewed-by: Konrad Dybcio --- drivers/tty/serial/qcom_geni_serial.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index e6b0a55f0cfb..9e2de074d799 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -7,6 +7,9 @@ /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO trac= es */ #define __DISABLE_TRACE_MMIO__ =20 +#define CREATE_TRACE_POINTS +#include + #include #include #include @@ -225,7 +228,7 @@ static void qcom_geni_serial_config_port(struct uart_po= rt *uport, int cfg_flags) static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) { unsigned int mctrl =3D TIOCM_DSR | TIOCM_CAR; - u32 geni_ios; + u32 geni_ios =3D 0; =20 if (uart_console(uport)) { mctrl |=3D TIOCM_CTS; @@ -235,6 +238,8 @@ static unsigned int qcom_geni_serial_get_mctrl(struct u= art_port *uport) mctrl |=3D TIOCM_CTS; } =20 + trace_geni_serial_get_mctrl(uport->dev, mctrl, geni_ios); + return mctrl; } =20 @@ -253,6 +258,8 @@ static void qcom_geni_serial_set_mctrl(struct uart_port= *uport, if (!(mctrl & TIOCM_RTS) && !uport->suspended) uart_manual_rfr =3D UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); + + trace_geni_serial_set_mctrl(uport->dev, mctrl, uart_manual_rfr); } =20 static const char *qcom_geni_serial_get_type(struct uart_port *uport) @@ -683,6 +690,8 @@ static void qcom_geni_serial_start_tx_dma(struct uart_p= ort *uport) xmit_size =3D kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); =20 + trace_geni_serial_tx_data(uport->dev, tail, xmit_size); + qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_ON_SEND); =20 qcom_geni_serial_setup_tx(uport, xmit_size); @@ -909,8 +918,10 @@ static void qcom_geni_serial_handle_rx_dma(struct uart= _port *uport, bool drop) return; } =20 - if (!drop) + if (!drop) { + trace_geni_serial_rx_data(uport->dev, port->rx_buf, rx_in); handle_rx_uart(uport, rx_in); + } =20 ret =3D geni_se_rx_dma_prep(&port->se, port->rx_buf, DMA_RX_BUF_SIZE, @@ -1069,6 +1080,10 @@ static irqreturn_t qcom_geni_serial_isr(int isr, voi= d *dev) geni_status =3D readl(uport->membase + SE_GENI_STATUS); dma =3D readl(uport->membase + SE_GENI_DMA_MODE_EN); m_irq_en =3D readl(uport->membase + SE_GENI_M_IRQ_EN); + + trace_geni_serial_irq(uport->dev, m_irq_status, s_irq_status, + dma_tx_status, dma_rx_status); + writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); @@ -1281,8 +1296,8 @@ static int geni_serial_set_rate(struct uart_port *upo= rt, unsigned int baud) return -EINVAL; } =20 - dev_dbg(port->se.dev, "desired_rate =3D %u, clk_rate =3D %lu, clk_div =3D= %u\n, clk_idx =3D %u\n", - baud * sampling_rate, clk_rate, clk_div, clk_idx); + trace_geni_serial_clk_cfg(uport->dev, baud * sampling_rate, clk_rate, + clk_div, clk_idx); =20 uport->uartclk =3D clk_rate; port->clk_rate =3D clk_rate; @@ -1432,6 +1447,10 @@ static void qcom_geni_serial_set_termios(struct uart= _port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); + + trace_geni_serial_set_termios(uport->dev, baud, bits_per_char, + tx_trans_cfg, tx_parity_cfg, rx_trans_cfg, + rx_parity_cfg, stop_bit_len); } =20 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE --=20 2.34.1