From nobody Fri Jun 12 23:47:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DAFD302767; Mon, 11 May 2026 23:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541247; cv=none; b=O/7di1G1n2eKYXPbxkiJvyavi/Rh85W+oBAAr6pCteqPqq5Q/5uYjgf5ZkJYAD5DAibniGIhyc95zACnmR6kUTWVjYwxHoHW0i4eUDJ6q5xe93TInDHT4a9wdS31z1dKNWisxrOBRhRNryqWkUqpi5zjbQ47Q9dq0I3H7v1z4No= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541247; c=relaxed/simple; bh=S+iZ04i2tTNKAa7ATmDVdt3q8+QcE4iPJ4/MjeyQosQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ex5p+8UyNfOpWtTAm4t6eHphh4hzsqKjinS1VK1QX5xLEdLvmh6WHEVpg6jo6rDvpE6AJ+cILp6YBFw8Rrbl94U/N4Q/jqBlXU6XPPObgSqE6F6YMN5aOhro0X0dJf+9gOAMwvJRh9JM3NO3/9XgSiOW+b5SSgQwrbGRFOrL+60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Zt1fNLlW; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Zt1fNLlW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778541246; x=1810077246; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S+iZ04i2tTNKAa7ATmDVdt3q8+QcE4iPJ4/MjeyQosQ=; b=Zt1fNLlW/bUNhf3mjSUvOGOHTxAvHiNXK5ybMasQEUdR3TN8Nl5mYfCK sDnDSbU3tc1AgBdBhI4Aa6tI5TeumCysqttvjdFWh2Rw+PNjsj/mtpzbm PvE9kT4aidxngLmlLJJ4PqSYnX6pcO6+m6D6MTlzKmTHd6b9NyFeFp9NJ hufeNyYHugPu1jeUuDDlTebqiwZZSL8BLauq5fkxJutQWH0W1mZDodU9R DSv/MrbxiTVSaItEnk0p1a2vsfVCz3cjFxk1eYLnUv/G/Lujwchsha5bZ NVtn+XbUaTAKe7o5hwpBkMpzZzciXqGZ2+bwSXEUt0QMcEoq60Jz3mD8Y g==; X-CSE-ConnectionGUID: vvw6abVMT7iNr5RKSR/rCg== X-CSE-MsgGUID: 0TIFn1CyQJa8rHDUKF/FvA== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="83058099" X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="83058099" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 X-CSE-ConnectionGUID: P/JUhvM5S+etAUpxUZtoqA== X-CSE-MsgGUID: 9SRLTIrtSBahQN+ioSOB7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="267944456" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH 1/6] perf/x86/intel/uncore: Fix discovery unit lookup for multi-die systems Date: Mon, 11 May 2026 16:05:22 -0700 Message-ID: <20260511230527.26096-2-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In uncore_find_add_unit(), PMON units with the same unit ID may be added to the uncore discovery RB tree for different dies. These units are distinguished by node->die. However, intel_generic_uncore_box_ctl() uses fixes die ID -1 when looking up the discovery unit, which may retrieve the wrong node on multi-die systems. Use box->dieid instead so the correct discovery unit is selected. No functional issue has been observed so far because currently supported platforms happen to use the same unit control register for such units. Fixes: b1d9ea2e1ca4 ("perf/x86/uncore: Apply the unit control RB tree to MS= R uncore units") Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_discovery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 583cbd06b9b8..1d22d7c00ee0 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -481,7 +481,7 @@ static u64 intel_generic_uncore_box_ctl(struct intel_un= core_box *box) struct intel_uncore_discovery_unit *unit; =20 unit =3D intel_uncore_find_discovery_unit(box->pmu->type->boxes, - -1, box->pmu->pmu_idx); + box->dieid, box->pmu->pmu_idx); if (WARN_ON_ONCE(!unit)) return 0; =20 --=20 2.54.0 From nobody Fri Jun 12 23:47:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB1C362143; Mon, 11 May 2026 23:14:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541250; cv=none; b=OEGWh+2pMtD/tQJq1mjxFsAK/tTVw2BnPnU9J+X8245mLT61yulewKi8Pl9HWeLKm719ZT5dlDQkPnn8dmRLx8VLjYrA6JHKTSyPh2o8Y1S81Y0AjcQ9Ztv5XIeJBrMBOtxW5HUakO14uwxFtD70HJhut34QKW3DeK0zxUHGiWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541250; c=relaxed/simple; bh=4H9iY6p4klO+8V5I9C0fpg1tx5s/nV+3FfjItpbFmsw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lPKqGj/iv4zl1Qb1N0Mm7eyE+4upfjS8HvgjrVuRWI7S013HHRE8V1weDckMZJlZvTaHTYaymqxfnQr8MRL8JY7QxSK0H66xE/feOvHDtm4pGgu45Uc1dSLk6kWQms7hyKRM5YldyP3UKX64UeyxzL5oMQdxbPsFZyiXlxdZz/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NDhtwD6+; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NDhtwD6+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778541248; x=1810077248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4H9iY6p4klO+8V5I9C0fpg1tx5s/nV+3FfjItpbFmsw=; b=NDhtwD6+/KO09cov8R7OrmOZUNUzWa7Hc+VUG98x60LdK9r0lfn+bln0 g50+Rn3vC6RzZogiOj/yXnAbC4Hf3TSrTeR0sfuSErcnPfchZDuScjH3y jUgNCmUF0oxjt/zatbXia/ZTQl0BewoPBPRzAnSlwv+iVy3954grbAFUD UDwZcMZUf+9sYw+fCGvcXXObIxmglooeaWQHrs4NNM/QebIKnWnsWUUf6 j5X1cbA0/yTCavHhVF8UgxT84jAq9Qp/mC6zNyrDFC4XhxWM77Gg2iTs7 E1hJ8AfR8DsdGgk6Q5rdUUOMoqU7IUiHIw4oGf29afBGiFwMtlgMf0/iP Q==; X-CSE-ConnectionGUID: uvVJI8ekTMChxM0Bq+WlaQ== X-CSE-MsgGUID: 9nMHTpPMQPe/5K3IBrnsFQ== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="83058106" X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="83058106" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 X-CSE-ConnectionGUID: VJar7tStT6WGxFF5TZnsCA== X-CSE-MsgGUID: vlLwzpaUSrqmWqXtUw4jwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="267944459" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH 2/6] perf/x86/intel/uncore: Fix PCI device refcount leak in UPI discovery Date: Mon, 11 May 2026 16:05:23 -0700 Message-ID: <20260511230527.26096-3-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pci_get_domain_bus_and_slot() increments the reference count of the returned PCI device and therefore requires a matching pci_dev_put(). In skx_upi_topology_cb() and discover_upi_topology(), the lookup is performed inside a loop, but pci_dev_put() is only called once after the loop. As a result, references from all previous iterations are leaked. Move pci_dev_put(dev) into the if (dev) block immediately after upi_fill_topology() returns. Opportunistically, fix uninitialized variable in skx_upi_topology_cb(). Fixes: 4cfce57fa42d ("perf/x86/intel/uncore: Enable UPI topology discovery = for Skylake Server") Fixes: f680b6e6062e ("perf/x86/intel/uncore: Enable UPI topology discovery = for Icelake Server") Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_snbep.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 215d33e260ed..c9ce206fcbb6 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -4261,7 +4261,7 @@ static int upi_fill_topology(struct pci_dev *dev, str= uct intel_uncore_topology * static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment, int die, u64 cpu_bus_msr) { - int idx, ret; + int idx, ret =3D 0; struct intel_uncore_topology *upi; unsigned int devfn; struct pci_dev *dev =3D NULL; @@ -4274,12 +4274,12 @@ static int skx_upi_topology_cb(struct intel_uncore_= type *type, int segment, dev =3D pci_get_domain_bus_and_slot(segment, bus, devfn); if (dev) { ret =3D upi_fill_topology(dev, upi, idx); + pci_dev_put(dev); if (ret) break; } } =20 - pci_dev_put(dev); return ret; } =20 @@ -5499,6 +5499,7 @@ static int discover_upi_topology(struct intel_uncore_= type *type, int ubox_did, i devfn); if (dev) { ret =3D upi_fill_topology(dev, upi, idx); + pci_dev_put(dev); if (ret) goto err; } @@ -5506,7 +5507,6 @@ static int discover_upi_topology(struct intel_uncore_= type *type, int ubox_did, i } err: pci_dev_put(ubox); - pci_dev_put(dev); return ret; } =20 --=20 2.54.0 From nobody Fri Jun 12 23:47:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD0C1356777; Mon, 11 May 2026 23:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541248; 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11 May 2026 16:14:06 -0700 X-CSE-ConnectionGUID: u8a1BpfCT92oXCGW9M3sZg== X-CSE-MsgGUID: GsKpFoiJQICmPNyc2giBOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="267944463" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , stable@vger.kernel.org Subject: [PATCH 3/6] perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box() Date: Mon, 11 May 2026 16:05:24 -0700 Message-ID: <20260511230527.26096-4-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On some Raptor Cove CPUs, enabling uncore PMON globally at driver init may increase power consumption even when no perf events are in use. Drop adl_uncore_msr_init_box() and defer programming the global control register to enable_box(), so it is only set when a box is actually used. Cc: stable@vger.kernel.org Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_snb.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 3dbc6bacbd9d..edddd4f9ab5f 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -563,12 +563,6 @@ void tgl_uncore_cpu_init(void) skl_uncore_msr_ops.init_box =3D rkl_uncore_msr_init_box; } =20 -static void adl_uncore_msr_init_box(struct intel_uncore_box *box) -{ - if (box->pmu->pmu_idx =3D=3D 0) - wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); -} - static void adl_uncore_msr_enable_box(struct intel_uncore_box *box) { wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); @@ -587,7 +581,6 @@ static void adl_uncore_msr_exit_box(struct intel_uncore= _box *box) } =20 static struct intel_uncore_ops adl_uncore_msr_ops =3D { - .init_box =3D adl_uncore_msr_init_box, .enable_box =3D adl_uncore_msr_enable_box, .disable_box =3D adl_uncore_msr_disable_box, .exit_box =3D adl_uncore_msr_exit_box, --=20 2.54.0 From nobody Fri Jun 12 23:47:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3E43361666; 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a="83058115" X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="83058115" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 X-CSE-ConnectionGUID: lOv5iiMxTQ2cSy++dfIevw== X-CSE-MsgGUID: LwJGZv64ScGyzVsptQWSfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="267944465" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH 4/6] perf/x86/intel/uncore: Move die_to_cpu() to uncore.c Date: Mon, 11 May 2026 16:05:25 -0700 Message-ID: <20260511230527.26096-5-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move die_to_cpu() into uncore.c so it can be reused by the MSR initialization path, preparing for the introduction of an MSR global initialization callback. Add the uncore_ prefix for consistency with other uncore APIs. No functional change intended. Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore.c | 19 +++++++++++++++++++ arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_snbep.c | 21 +-------------------- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index e9cc1ba921c5..2bbe4cc1df3e 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -83,6 +83,25 @@ int uncore_device_to_die(struct pci_dev *dev) return -1; } =20 +int uncore_die_to_cpu(int die) +{ + int res =3D 0, cpu; + + /* + * Using cpus_read_lock() to ensure cpu is not going down between + * looking at cpu_online_mask. + */ + cpus_read_lock(); + for_each_online_cpu(cpu) { + if (topology_logical_die_id(cpu) =3D=3D die) { + res =3D cpu; + break; + } + } + cpus_read_unlock(); + return res; +} + static void uncore_free_pcibus_map(void) { struct pci2phy_map *map, *tmp; diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index c35918c01afa..94c68e3417b6 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -235,6 +235,7 @@ struct pci2phy_map *__find_pci2phy_map(int segment); int uncore_pcibus_to_dieid(struct pci_bus *bus); int uncore_die_to_segment(int die); int uncore_device_to_die(struct pci_dev *dev); +int uncore_die_to_cpu(int die); =20 ssize_t uncore_event_show(struct device *dev, struct device_attribute *attr, char *buf); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index c9ce206fcbb6..30c6a9306c54 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3704,25 +3704,6 @@ static int skx_msr_cpu_bus_read(int cpu, u64 *topolo= gy) return 0; } =20 -static int die_to_cpu(int die) -{ - int res =3D 0, cpu, current_die; - /* - * Using cpus_read_lock() to ensure cpu is not going down between - * looking at cpu_online_mask. - */ - cpus_read_lock(); - for_each_online_cpu(cpu) { - current_die =3D topology_logical_die_id(cpu); - if (current_die =3D=3D die) { - res =3D cpu; - break; - } - } - cpus_read_unlock(); - return res; -} - enum { IIO_TOPOLOGY_TYPE, UPI_TOPOLOGY_TYPE, @@ -3795,7 +3776,7 @@ static int skx_pmu_get_topology(struct intel_uncore_t= ype *type, u64 cpu_bus_msr; =20 for (die =3D 0; die < uncore_max_dies(); die++) { - ret =3D skx_msr_cpu_bus_read(die_to_cpu(die), &cpu_bus_msr); + ret =3D skx_msr_cpu_bus_read(uncore_die_to_cpu(die), &cpu_bus_msr); if (ret) break; =20 --=20 2.54.0 From nobody Fri Jun 12 23:47:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB338363C75; Mon, 11 May 2026 23:14:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541250; cv=none; b=ZxqQnBcoRPgovl1qUqmeZvfMW3oip3BhTAiUS+QK46gyjzeGdLTbr6HP+m4o6l3JRvKL6hW3JFVKdrC7xY9W7WnIBK66S2MLFekbMWg1X1wJT38Fr8iy0eCNyr5YoWm12s2m91M+rtseeNxZvBdaMdVGPsAa/Qo/nLB2Yb9tgsU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778541250; c=relaxed/simple; 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d="scan'208";a="267944468" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH 5/6] perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline dies Date: Mon, 11 May 2026 16:05:26 -0700 Message-ID: <20260511230527.26096-6-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the die is offline when uncore_die_to_cpu() is called, it silently returns 0, which is misleading. Return -1 in this case to indicate that all CPUs on the die are offline and the caller can take care of it accordingly. Opportunistically, replace -EPERM with -ENODEV, as -ENODEV is the appropriate error when no CPUs are online across all dies. Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/intel/uncore_snbep.c | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 2bbe4cc1df3e..19056514b081 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -85,7 +85,7 @@ int uncore_device_to_die(struct pci_dev *dev) =20 int uncore_die_to_cpu(int die) { - int res =3D 0, cpu; + int res =3D -1, cpu; =20 /* * Using cpus_read_lock() to ensure cpu is not going down between diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 30c6a9306c54..251c7bdbe30b 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3772,11 +3772,16 @@ static void pmu_free_topology(struct intel_uncore_t= ype *type) static int skx_pmu_get_topology(struct intel_uncore_type *type, int (*topology_cb)(struct intel_uncore_type*, int, int, u64)) { - int die, ret =3D -EPERM; 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d="scan'208";a="267944471" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 16:14:06 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH 6/6] perf/x86/intel/uncore: Implement global init callback for GNR uncore Date: Mon, 11 May 2026 16:05:27 -0700 Message-ID: <20260511230527.26096-7-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511230527.26096-1-zide.chen@intel.com> References: <20260511230527.26096-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Sierra Forest and Clearwater Forest, the FRZ_ALL bit in the global control register defaults to 0 at boot, but UBOX PMON units do not work until the global control register is explicitly written with 0 to trigger hardware initialization properly. Implement the generic uncore_msr_global_init() callback and add it to gnr_uncore_init[], which is shared by GNR, GRR, SRF, and CWF. Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore.c | 14 +++++++++++++- arch/x86/events/intel/uncore.h | 2 +- arch/x86/events/intel/uncore_discovery.c | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 19056514b081..a7780c5cd419 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1716,7 +1716,7 @@ static int __init uncore_mmio_init(void) return ret; } =20 -static int uncore_mmio_global_init(u64 ctl) +static int uncore_mmio_global_init(int die, u64 ctl) { void __iomem *io_addr; =20 @@ -1731,6 +1731,17 @@ static int uncore_mmio_global_init(u64 ctl) return 0; } =20 +static int uncore_msr_global_init(int die, u64 msr) +{ + int cpu =3D uncore_die_to_cpu(die); + + if (cpu =3D=3D -1) + return -ENODEV; + + wrmsrq_on_cpu(cpu, msr, 0); + return 0; +} + static const struct uncore_plat_init nhm_uncore_init __initconst =3D { .cpu_init =3D nhm_uncore_cpu_init, }; @@ -1871,6 +1882,7 @@ static const struct uncore_plat_init gnr_uncore_init = __initconst =3D { .domain[0].base_is_pci =3D true, .domain[0].discovery_base =3D UNCORE_DISCOVERY_TABLE_DEVICE, .domain[0].units_ignore =3D gnr_uncore_units_ignore, + .domain[0].global_init =3D uncore_msr_global_init, }; =20 static const struct uncore_plat_init dmr_uncore_init __initconst =3D { diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 94c68e3417b6..c2e5ccb1d72c 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -53,7 +53,7 @@ struct uncore_discovery_domain { /* MSR address or PCI device used as the discovery base */ u32 discovery_base; bool base_is_pci; - int (*global_init)(u64 ctl); + int (*global_init)(int die, u64 ctl); =20 /* The units in the discovery table should be ignored. */ int *units_ignore; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 1d22d7c00ee0..49183d607a34 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -287,7 +287,7 @@ static int __parse_discovery_table(struct uncore_discov= ery_domain *domain, if (!io_addr) return -ENOMEM; =20 - if (domain->global_init && domain->global_init(global.ctl)) { + if (domain->global_init && domain->global_init(die, global.ctl)) { ret =3D -ENODEV; goto out; } --=20 2.54.0