From nobody Sat Jun 13 00:41:25 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C02B4C9571 for ; Mon, 11 May 2026 19:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527156; cv=none; b=NsYC8KQBW4MrUaVWms/8pScsbarhl9jqTT9SyTWYNg9jNELE0ITmtUKvs2Msd/a+PsqbqDFZAirSk6YX3fYtP4qGO0LiR2KydKSbEgyG9o7LoXlyD27mNbCy3Qgsx7H/ML5fRGVXc+8/0lYK5y1FKzsRrkBQiqAlCuVGiX75E+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527156; c=relaxed/simple; bh=RSQEM4AEfXDIroL3bz9Dy4plRs5cUm5ilJwgG0nOjgk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LPu+SO3zcQigU8SoejRz+znrjPgqUDVr5WbyrXTsLKJbOG7zZ03Ig/Jjj+jcw+RH5y5t8O2Tc/ibMQi1qmBCMZK/QnYJ8j6LV84CRTBRgZQC8ONLEFul9/EfMEolMpgQcwkY/f3ZFJ0eyd23m1fxRKjsKL4G3uwz0isdacfy0Dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kRH+i/eW; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kRH+i/eW" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4891f625344so44905705e9.0 for ; Mon, 11 May 2026 12:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778527153; x=1779131953; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ert1gXzfFNzUas1j1dDUmLT9J2s7SsBhHdLE/z6vbiA=; b=kRH+i/eWUXKVzJLuLKKiuAIpv0BcY4tnRryeVOw6+v4n+uOI757mrirkENlYxOozHz VfPoBAVHpnj5FI/JkiblmozWIrt+96gkcEuN30WAJV4oEeEyWvTq++/CDaaYPgq6aanW o4AnKi9vwWPurxXozHF22F8/7uukXc0g27EQSImk7KPSfEv25BMeFp3Qq1dOROEYurX8 PI8bei4h+7yjcD/n3zFIDpjyyIN18z3PEj0FmbvKrjbXWEBC9kHmSqdkEM8XDqRSiHJp 1n/3sKBWtDRiB1WDzlWBvPtIQNxBdNpCjhjZZh5mVKbNOh5NwFAx9RxMV3N2HA+H3tJ3 rgyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778527153; x=1779131953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Ert1gXzfFNzUas1j1dDUmLT9J2s7SsBhHdLE/z6vbiA=; b=NFZcOt4ORxficY+eiI8+k6Q9cpi11d4LeG++aoS2UrYtqab3RzV4apsNbTcZukec0T 5YO+3NNo49U/f5sj2hhSm2VjpH6tBvcTVXySITBHlOovbBpMLi7CI3I8SLA+18UumI03 geBRoHphm7K2l/F/GXyr4eZ0q9/LZNyn+5Q8pWKYs0557zZeEIKhYWnoe+kkl6oUS5EJ xkyM6KA7CHeMYjsJvHcMQ0hS8ZUY8tOGG8WeVrhDYck+N+5O0Z2YydEnGNToN18fcMYu YwsI9sqI+17g8TBOYqpePD+UGXvtjsqT7WyxctYgzVDi4Ymn96S1eru81hQ6oHGk9hpe yypw== X-Forwarded-Encrypted: i=1; AFNElJ/0dm6v4dBDJuDavURZeZ4ytP2t0cLqHVcHq5whV5ICMQWrn/wst3WvkolzDfqHC/5HLa9P6pG0EvcpEaU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+qNlD+4ONNNs+uxWXrbZYfKQdNKwW28arPU4N7XzjvDlGlCDA ENzzFfAZMoFbYh3PcYZWqJfQ4U4FlVg095mmHMu1eJuLpRE7MnFwMvYe X-Gm-Gg: Acq92OFpOJf47qAkX1CA/j488JvNHZZF6Unb3Us+tetzD5DH69rmzJwhjAA+uXVzpa2 6wSOHBCnG9JIs+f3zxHAkSuqO9eA1/sxGTvM++OfjgTXNz/60xV11VjchqIBO1mKgE9nV5WHCNl GzXQvcoCzNwAq+BfqzUXklGRPQnY/45uDKX60gC/b0zZ2LqysOK3ScXm27ZRb8aLUqAKd9TbED+ 09dAg6Q+5iqdsgHVd/ddR7F/Jqav6jIXGmLBFVskMBaQ36i0HCTGFntiPV40VYa2T9yZGbRzUd7 l3+oAsddc80sSWluGX2+TmRvxYi+nspr8XcPHlo+Mb4PIB/A/YWEtG7A77sL5PIzl6tK4SOa1FD 07qSHwxkpF4W2gjN9nadS6PXmQrpvdQuiD7UCDYPVBDU52+uoV2AeV2w8sw6OnjyaQ0nFTbxaIi mLvAk9F2s1Des9ZqrHh34Aa0GV/wAmbLoh00LiOn0qqPTRoMvpAjbTMrQjMwBL3HLeCNsYVB1Mo 4jq4YGHXEDsAjRcA+7RsOxNjZoybmBSTtUyMw== X-Received: by 2002:a05:600c:c167:b0:48a:761:5816 with SMTP id 5b1f17b1804b1-48e8e207f2bmr12978725e9.8.1778527152976; Mon, 11 May 2026 12:19:12 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e687:6094:b849:9886]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e7e45ff89sm150350725e9.8.2026.05.11.12.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 12:19:12 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/4] clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations Date: Mon, 11 May 2026 20:19:07 +0100 Message-ID: <20260511191910.1945705-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Use a per-SoC PLL reference input frequency for PLL parameter calculations instead of relying on the hardcoded 24MHz constant. Add an input_fref field to struct rzv2h_pll_limits and derive the PLL reference frequency from it in rzv2h_get_pll_pars(). Fall back to the existing 24MHz value when no SoC-specific input is provided. This allows the existing PLL divider calculation logic to be reused unchanged on SoCs such as RZ/T2H, which use a 48MHz PLL reference input instead of the 24MHz reference used on RZ/V2H(P), while keeping current RZ/V2H(P) behaviour intact. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 7 ++++--- include/linux/clk/renesas.h | 5 +++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index e271c04cee34..b1d640e5c0f9 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -242,6 +242,7 @@ struct rzv2h_plldsi_div_clk { bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, struct rzv2h_pll_pars *pars, u64 freq_millihz) { + unsigned long input_fref =3D limits->input_fref ?: RZ_V2H_OSC_CLK_IN_MEGA; u64 fout_min_millihz =3D mul_u32_u32(limits->fout.min, MILLI); u64 fout_max_millihz =3D mul_u32_u32(limits->fout.max, MILLI); struct rzv2h_pll_pars p, best; @@ -254,7 +255,7 @@ bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *= limits, best.error_millihz =3D S64_MAX; =20 for (p.p =3D limits->p.min; p.p <=3D limits->p.max; p.p++) { - u32 fref =3D RZ_V2H_OSC_CLK_IN_MEGA / p.p; + u32 fref =3D input_fref / p.p; u16 divider; =20 for (divider =3D 1 << limits->s.min, p.s =3D limits->s.min; @@ -335,9 +336,9 @@ bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *= limits, continue; =20 /* PLL_M component of (output * 65536 * PLL_P) */ - output =3D mul_u32_u32(p.m * 65536, RZ_V2H_OSC_CLK_IN_MEGA); + output =3D mul_u32_u32(p.m * 65536, input_fref); /* PLL_K component of (output * 65536 * PLL_P) */ - output +=3D p.k * RZ_V2H_OSC_CLK_IN_MEGA; + output +=3D p.k * input_fref; /* Make it in mHz */ output *=3D MILLI; output =3D DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider); diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h index 0949400f44de..bd2d49e7290f 100644 --- a/include/linux/clk/renesas.h +++ b/include/linux/clk/renesas.h @@ -53,6 +53,8 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divid= er, int target) { } * various parameters used to configure a PLL. These limits ensure * the PLL operates within valid and stable ranges. * + * @input_fref: Reference input frequency to the PLL (in MHz) + * * @fout: Output frequency range (in MHz) * @fout.min: Minimum allowed output frequency * @fout.max: Maximum allowed output frequency @@ -78,6 +80,8 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divid= er, int target) { } * @k.max: Maximum delta-sigma value */ struct rzv2h_pll_limits { + u32 input_fref; + struct { u32 min; u32 max; @@ -156,6 +160,7 @@ struct rzv2h_pll_div_pars { =20 #define RZV2H_CPG_PLL_DSI_LIMITS(name) \ static const struct rzv2h_pll_limits (name) =3D { \ + .input_fref =3D 24 * MEGA, \ .fout =3D { .min =3D 25 * MEGA, .max =3D 375 * MEGA }, \ .fvco =3D { .min =3D 1600 * MEGA, .max =3D 3200 * MEGA }, \ .m =3D { .min =3D 64, .max =3D 533 }, \ --=20 2.54.0 From nobody Sat Jun 13 00:41:25 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 732594D2ED1 for ; Mon, 11 May 2026 19:19:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527157; cv=none; b=bo7lDfxe9Lh9fOPETMq+c4DE5XDaHOKcPhvXVUHKSObImL3wCCgogYgi5ms4owre7+OJmuVRzTwKANCZ3ZKCW0aCrYDBPODdayYbq6rWICoQPLVkq15WY4H8WmZr5tPkbSJzlbwB/xmxZ8td7R0mnAmAk7YaaG5mMG9zjFVc2lE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527157; c=relaxed/simple; bh=LBeDEgZcG53jxDrJXYhFxbZX8rocP0frMxZVg1RlP94=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LPs4vbkj+2qr5cyx99d4CW1ZFVOWilSeY2c2q0Th4TigKZMospv4Sp879nCMEniFELLQFZy1FWylsAHUjPJYPPxj3LgVmOdx60c/BeZr6xNg2f92KEjNmjAPYQRysL4jfq2u2F1hf1VAGYcnUe58t8gXs1PbLrsGohOvC+jkZJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=g9vskC3i; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g9vskC3i" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-48e82c23840so12222225e9.3 for ; Mon, 11 May 2026 12:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778527154; x=1779131954; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a1ZSKqDKys1YDO0iK340T9vdYLek+xBsPl8I5xs6dy4=; b=g9vskC3iHYV33tUkLOuXaeGikjhJ8MuQqcwRTCR8OsL3Hk4QLfA/7gEmceUVxRA1XU Ak4ntIOMrzT8o9t55bIQihcHVAsXNWas2AgzcOkTpJ5pfk04a9q7g1jQupl/zi8tQcli RIB/2QvbyLuHnYd6phr7hnapiiGN80beXuDUMgueCYn6G4wrkowd9wb3bS9c+VxKJXzi VzD5YPQdhY5AYz8cfm2F/eQ2i0Yr8Oy3w2W/W//4BqkEuMcrsdSrEvonK8gQNaN+vUHZ 9uNSkFpiu3tIZDYSMDrinhdDp8ut6jr1xmHhsPg8fqNbUW7p5W4v5nGCphI+lcXW6sLW rQVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778527154; x=1779131954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=a1ZSKqDKys1YDO0iK340T9vdYLek+xBsPl8I5xs6dy4=; b=JgmbVMc4wq6q9ReGP3Hom/baOfWVMgXketVtxiTWX+XxZ7JyUfszFCkxugcgPYlPv5 OreVqk86eimaXzuFJeNhnVGnyAaKP76sNHCOZMUxvYTD3TWWzoU2BE3LwRQYSCBvUzDP xg1j4K1xaioMN44+YuIZOXjDNLN55ZWP/n36LKYfrlhzHjRw4CyC2PxLE/CnpjRc3mQS /I0aY93XrIba4OJs9j8pNJRAwk8W4VnHcltdsQbafufQJvarBCp07r7nBBEfU7fPagz6 oun3R+T9S12OkkCmcPXUkiZQNgix6jWwmIkA34LtugUVFTv8cI53+NnJXvtVQSQmiwq+ gOhg== X-Forwarded-Encrypted: i=1; AFNElJ9bmyZBHG8xB9DoiZPqMjXyFEtQTRDzfx7fIkfUeQZc8vgP1MpWg6RQ67qgXJLg8zl4um6wMtCw+czlPTE=@vger.kernel.org X-Gm-Message-State: AOJu0Yyj7A9eGOnZE8sIxlxLgK1N3eI0e/5ZenKFwN8MWVKRaUJ/b7QD 3+yGUEK4/ckw8ToNSQyhGzph6XumeUB3+oZygg0aX17jNr4TQMrCrO+A X-Gm-Gg: Acq92OHRGXu1s11PdwX8VXq0/MhyXajcMHnxYfA1xosjWlttUIaaWE7J+fjH8/MF3gM Hr0hqb67cnQWQCQtrBmsc5hxkFpjh9E06z3wr3FpP/EOfBF1DbiwBmofrNBYR9E1KM1pLgh6sH1 ItSJF8Pvq/FuICVXpDRTNPOau2xZQjEXpA0ccNu+53lLfctOCAzNtYrBK3UgI02ryYLhc0rIpoI UgilbkvusK4Q3PjMJkrYk/o5qYVbH18O1jd3xt3ASccoehbkmNvrheEfQVzF9TShC+5MfX2IHuu hzKrMIzEWH3GWIfVkz5cq3DujhuGNz1Yr4ICw/U8q5f8kCLrglQ47t3kKo/aC/vUQ42/LldpypY As+hssxQixPmz345SEYvPHgz8fDKIlPBnsyg97w9OONsqCZHmHGWPMlC73SQn6f5SOephjPJLsX 2BUvypCM6qqRgb6twBbRZc0+VojpiXjTx+/5IHz1clREJ8VvrH2iEie4qJ+itgpRWYlPRvJew41 0JabuLY/mqL7B4hftzQuoaakJtWDyyUGH31cA== X-Received: by 2002:a05:600c:c166:b0:48e:6f39:f7be with SMTP id 5b1f17b1804b1-48e6f39f7d2mr195440165e9.10.1778527153714; Mon, 11 May 2026 12:19:13 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e687:6094:b849:9886]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e7e45ff89sm150350725e9.8.2026.05.11.12.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 12:19:13 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/4] clk: renesas: cpg-mssr: Add table-driven MSTP dummy-read delay for LCDC on RZ/T2H Date: Mon, 11 May 2026 20:19:08 +0100 Message-ID: <20260511191910.1945705-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Per the RZ/T2H hardware manual, to secure processing after release from the module-stop state, dummy read the same MSTPCRm register at least seven times for most IP blocks, at least 100 times for LCDC and at least 300 times for RTC before proceeding with subsequent processing. The existing udelay(10) satisfies the seven dummy-read requirement for most IP blocks. Extend this to support per-IP dummy-read requirements by introducing a table-driven lookup, rzt2h_mstp_delay_table, where each entry records the MSTPCRm register index, bit position and the minimum dummy-read count from the hardware manual, converted to microseconds via RZT2H_MSTP_READS_TO_US(). Introduce cpg_rzt2h_mstp_get_delay_us() to replace the open-coded udelay(10) calls. In cpg_mstp_clock_endisable() the exact register and bit are known so the lookup matches on both fields. In cpg_mssr_resume_noirq() the register is known but not the individual bit, so pass RZT2H_MSTP_ANY_BIT causing the lookup to match on the register alone and return the delay for the first matching entry. Add an entry for LCDC which requires at least 100 dummy reads. Adding support for further IP blocks with non-default requirements only needs a new entry in rzt2h_mstp_delay_table with no logic changes needed. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/renesas-cpg-mssr.c | 65 +++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index 5b84cbee030b..e6bf5062e40e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -96,6 +96,24 @@ static const u16 mstpcr_for_gen4[] =3D { #define RZT2H_MSTPCR_BLOCK(x) ((x) >> RZT2H_MSTPCR_BLOCK_SHIFT) #define RZT2H_MSTPCR_OFFSET(x) ((x) & RZT2H_MSTPCR_OFFSET_MASK) =20 +/* Dummy read counts as specified by the RZ/T2H hardware manual */ +#define RZT2H_MSTP_DEFAULT_DUMMY_READS 7 +#define RZT2H_MSTP_LCDC_DUMMY_READS 100 + +/* + * Time per dummy read in nanoseconds, derived from the original udelay(10) + * which was used to satisfy the 7 dummy-read requirement: + * 10000 ns / 7 reads =3D 1429 ns per read. + */ +#define RZT2H_MSTP_DUMMY_READ_NS 1429 +#define RZT2H_MSTP_READS_TO_US(n) (((n) * RZT2H_MSTP_DUMMY_READ_NS) / 1000) +#define RZT2H_MSTP_DEFAULT_DELAY_US RZT2H_MSTP_READS_TO_US(RZT2H_MSTP_DEFA= ULT_DUMMY_READS) + +#define RZT2H_MSTPCRM_INDEX 12 +#define RZT2H_MSTPCRM04_LCDC 4 + +#define RZT2H_MSTP_ANY_BIT U32_MAX + static const u16 mstpcr_for_rzt2h[] =3D { RZT2H_MSTPCR(0, 0x300), /* MSTPCRA */ RZT2H_MSTPCR(0, 0x304), /* MSTPCRB */ @@ -113,6 +131,35 @@ static const u16 mstpcr_for_rzt2h[] =3D { RZT2H_MSTPCR(1, 0x334), /* MSTPCRN */ }; =20 +/** + * struct rzt2h_mstp_delay_entry - MSTP dummy-read requirement for RZ/T2H + * + * @reg: Index into control_regs[]. Exact match. + * @bit: MSTP bit position, or RZT2H_MSTP_ANY_BIT for register-level match. + * @delay_us: Computed delay in microseconds to satisfy the dummy read req= uirement. + */ +struct rzt2h_mstp_delay_entry { + u32 reg; + u32 bit; + u32 delay_us; +}; + +/* + * Per RZ/T2H HW manual: to secure processing after release from the + * module-stop state, dummy read the same register at least seven times + * (except RTC and LCDC) after writing to initiate release from the + * module-stop state. For RTC, dummy read at least 300 times and for + * LCDC, at least 100 times. + * + * Instead of performing the actual dummy reads, an equivalent delay is + * added using udelay(), computed from the required read count via + * RZT2H_MSTP_READS_TO_US(). + */ +static const struct rzt2h_mstp_delay_entry rzt2h_mstp_delay_table[] =3D { + { RZT2H_MSTPCRM_INDEX, RZT2H_MSTPCRM04_LCDC, + RZT2H_MSTP_READS_TO_US(RZT2H_MSTP_LCDC_DUMMY_READS) }, +}; + /* * Standby Control Register offsets (RZ/A) * Base address is FRQCR register @@ -253,6 +300,20 @@ static void cpg_rzt2h_mstp_write(struct cpg_mssr_priv = *priv, u16 offset, u32 val writel(value, base + RZT2H_MSTPCR_OFFSET(offset)); } =20 +static unsigned int cpg_rzt2h_mstp_get_delay_us(u32 reg, u32 bit) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(rzt2h_mstp_delay_table); i++) { + const struct rzt2h_mstp_delay_entry *e =3D &rzt2h_mstp_delay_table[i]; + + if (e->reg =3D=3D reg && (e->bit =3D=3D bit || bit =3D=3D RZT2H_MSTP_ANY= _BIT)) + return e->delay_us; + } + + return RZT2H_MSTP_DEFAULT_DELAY_US; +} + static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) { struct mstp_clock *clock =3D to_mstp_clock(hw); @@ -312,7 +373,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, = bool enable) * register, we simply add a delay after the read operation. */ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]); - udelay(10); + udelay(cpg_rzt2h_mstp_get_delay_us(reg, bit)); return 0; } =20 @@ -1142,7 +1203,7 @@ static int cpg_mssr_resume_noirq(struct device *dev) cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], newval); /* See cpg_mstp_clock_endisable() on why this is necessary. */ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]); - udelay(10); + udelay(cpg_rzt2h_mstp_get_delay_us(reg, RZT2H_MSTP_ANY_BIT)); continue; } else writel(newval, priv->pub.base0 + priv->control_regs[reg]); --=20 2.54.0 From nobody Sat Jun 13 00:41:25 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E3774D2EE0 for ; Mon, 11 May 2026 19:19:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527157; cv=none; b=NLgiRT//eAR2N/e/5kTVBgaP4STKp2MhuBhSqutmvWg/z8a2nviLQ9ltPenSs0YZlouDi7jTb83tomv9sMIeuBbq0sS4nsciAdtPv9J02djBdNNnrEnQI4W2ytrDJSXjOQPTA9bPqphDmmwYZKuihJ0dl3nQfsEVql0xDEBKWPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527157; c=relaxed/simple; bh=bRtHKL8Ghq1igkZvpCdDlmBm9XyVW19EMHHP+BJzPeE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CC2mtUQ1Ml5H+p7vgf9NZg3Bsq8LavwMHYs8f381ocDRLYmYqe2cQmMNothrncdzYLcxcntp0TMQZyCyZAVv7SRe5GKGcuCvb5foVUCC49/ALoF2gEnpmfYgeP4socKGhzZeV5f4vX4iiYkDMEndpwzScjowt/95XlWMVbKEVx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YXG32A/X; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YXG32A/X" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso40089375e9.2 for ; Mon, 11 May 2026 12:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778527154; x=1779131954; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=POtlnulhl/F66NG/qN2X+H18Iihe7TwpdtVefEviDCE=; b=YXG32A/XZZ+8zSJWbfvSNysUE+YaEWVKjg4+GAc9udh5cmrHpZxFqesh2VXJ0bDvu1 28LBjfkkZWhmsadbLmy5o48MglU2iHL6dnIYKkHZE8msCv3xuGSqj2fF4lyLCjCniAuw flvGlo/wuNsuzT6o0Z489bgskYG3ii/j49LV6R/cXgB3UT8wSAH30L+Wn4VKOTEmFT3L gYC7cgk9Fm8b/PHO+7dHLMghVhdKSP4W8PwOSKUWFiUpUBLzeh8SFuqG2BBQ2XWpF/tF lt3XLWPr1jQoYdaCsNRuxDc83nwKbc9vhMJxu06epaDQ9XV0WmV67nZsr1bHLF/WFmt3 wznA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778527154; x=1779131954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=POtlnulhl/F66NG/qN2X+H18Iihe7TwpdtVefEviDCE=; b=H1+1TZUWPuGRC1n/GtOtxAIBKZxKS+SAJjCxmiXFvKq2HAgBzNJGw3jam4o9sfEyXF Sf4D2AXr7oU9bzziCRYOACBXOHE1i3JHGt1u6pIsuNt91kF2S+mEEpNh2jRzAkbjLSKM RQtO2rQt8GP04sOl5R0rIoG9Hs0Cxs7XoLcj5DzjCOlAsG9Q6kTY/Tdn0Nwy23ffcsfc nbkhH9Kn+Qt7w5yCfpYj2/+YghrcO8F9a9FlkX69RZVQmMcfvBxBYT/AUvEhHNSx++aY BNmVyyZMAsusmkQOcEBiVLjKbKdDPkw/SW+PvtnKo/eDvj+T6WUH2jN6btM9Z0AaEKk0 KWtA== X-Forwarded-Encrypted: i=1; AFNElJ+4BRHBaibtA4EqusXqMKW4uMj1PXZ19kwvgPMMbiZgGvaoTIJw4z1+yDrdSzx6jtB9yuFP+l+GWS1pdPs=@vger.kernel.org X-Gm-Message-State: AOJu0YyaQlmWFOSFPJC911cCr5YNd6w7U8lpx//OCiEP8bHXX0L5ec4Z JzUtlgeg8M/cR9lNeAnt+uh9RGve+EQjOsZ22tPo1JtpRYpPYeVfl2iZ X-Gm-Gg: Acq92OFw6WZuWQtBeGEksJMcPicB4jR2KJd8DJcuOKAEp6i7QKtVcdi2IrOkR7dc7nS gR1f1TjwVX/GfxKh6wvRqo4Va1bRox9p75+jzyVvnhh5zx+Fo+WPy/B438XHgBkiWWmq5co43Uf 441lYXlFPVMGwHMY9qlq/eCnUKnu8nr7bfoBd0L3lRf6uVPXK86vBVs2IT13mAxgXFFpwTcUvqE RI+B9O+SiWLbk22sJhC2bk6l7OQlUY5WS3Pml1Y6IuMQ0dDp3MyZXa6VaXFlV7ecEZX91XPxX3m rX8rUSiGL5q4wBhQlaui/uiBeeCrJ8nYriIoaDlEzIvuHGXQ1B8ED5wgIVKsHWu3ClGTwIONyva 1jVZXxlxiMs/sE7z67I4QBwKe/LNGKZmotFNyNQVufYZqUtTEP6gW8Z8Uaqj1em1OEDfDpAx1p7 Nq8Ro+WVhK2NeG+NWxceNMMBerFBzhyaPUIDJHvPPx1THXqM2PZSdUjE55pNIreXhKTlpofvFT2 D9IhSovpJ03sThKcqQ98xb1IQYR7VsD839rKg== X-Received: by 2002:a05:600c:1797:b0:48d:366:b962 with SMTP id 5b1f17b1804b1-48e51e0a8a8mr217354635e9.6.1778527154318; Mon, 11 May 2026 12:19:14 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e687:6094:b849:9886]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e7e45ff89sm150350725e9.8.2026.05.11.12.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 12:19:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID Date: Mon, 11 May 2026 20:19:09 +0100 Message-ID: <20260511191910.1945705-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the LCDC clockd (LCDC_CLKD) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. LCDC_CLKD is used as the operating clock for LCDC. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index c4863e444458..f6cb8d649a46 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -34,5 +34,6 @@ #define R9A09G077_XSPI_CLK0 22 #define R9A09G077_XSPI_CLK1 23 #define R9A09G077_PCLKCAN 24 +#define R9A09G077_LCDC_CLKD 25 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 0d53f1e65077..312e563b322e 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -34,5 +34,6 @@ #define R9A09G087_XSPI_CLK0 22 #define R9A09G087_XSPI_CLK1 23 #define R9A09G087_PCLKCAN 24 +#define R9A09G087_LCDC_CLKD 25 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ --=20 2.54.0 From nobody Sat Jun 13 00:41:25 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 074FC4D2EEF for ; Mon, 11 May 2026 19:19:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527160; cv=none; b=RcdjiMVIBftV9XxHZm7nurrYVL8sMb7A7PcIpSCNj7R6wUmOJRQfr+UDjsJlE4C2itvMZs6bl6GZOrVQJMUa3mDarSOC0ugnMlFbXyLfLbpJrLTgxa8gsNR+yz2M37SjLmrwXs3dIrOeBz8izHQRdQwF7xVGwnBMChkEWeKbci4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778527160; c=relaxed/simple; bh=ZigNsJmaRyQgS7Nx1ftxPvxo5zNU4Rbsp5V4RUUy8N8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hxNgKRFe4opDNvvuu4nNjcTmuVZXE4RJoASDLm51jR8nv/0payk41lKOfVC5U+ndrTsqT3C9O3zcbPevoCBlN9FEdoSL1UXTPWjfqUc/AoseLBNUz+LPpNkcA9GgE10R9w7bjlbRyEmVlXv29/tySBjoR8Os4bFHaeGZX5s2hxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KGasw8KM; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KGasw8KM" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so79994265e9.2 for ; Mon, 11 May 2026 12:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778527155; x=1779131955; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KKBaB/p67PNxx3pcTtiBcPK7gt5VXbXPk8rGGrXAwZg=; b=KGasw8KMJwOHG8+9gsHmJO/PEUoeSYmCXL650dNFdN90YkoOx/w2HhQJRA1bFZRtey yIjKmN9NrEWNkjUTFlUSr3JLb24Oh7pa7QCta8QprFsr0qgnIeTI1SHmx7x6K0RP8b0j AYWnJXSp5ZrUpG2MZEb3K0jMlaRgFzikzI/0ANU+70FwCf9a7DjQDBdj6+Kp5ZjJ30BM XbaKwEN1o6XNtkh3wIkg0SiieodFYEoOXOFcMBGHLRS/D48kOISSrvB+N4fVa46G6c27 q1WdvA4bNWlFSQrvjhZy0FixZNtJDwHka4MXhWbTQueNpnBNqLulgh25yW4wArqjQpiU a10A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778527155; x=1779131955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=KKBaB/p67PNxx3pcTtiBcPK7gt5VXbXPk8rGGrXAwZg=; b=TgMNbnbRtXsjds4gjxDJj7fiZOMfKv026KqNPNhoz267OnbBsr1fYmFXvrbS0LeJ5A H8ZXE4dEpmefNOzLBYnbflGOF7SbhPjzb033aLPA0zDSZC2LPKdxx83YEDlWq/xDUFww /l6kfOUjKvIrYiFP8JbhHpMLnlwJ7HXdwUx+QvJ2g4GpJUEia9iQlEvq1IvtWvU6rumB JXAgMVR10IzT3x69XoVtgSOT32AVHwEMEgL0y8VdH9at1crge87rNVp6W/faWDTBxdcZ vAnmTqkjbyPyKzgwNy56myIY5D9Aqsfcdxf130gh0HwgA42Hq2iydmJ5sr2UbX6b9ety G7PA== X-Forwarded-Encrypted: i=1; AFNElJ/3E/QWeU8YLKVo0Zf6+QH/PXohifvM2EUn7cTSw8/YlC1YfRhzYOepAdHypvKsN3P5FyCoqUz4ATWUqfA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx1tPOnxJkJAiRQ/osxuzp81Y09EDQwlCqGE8rnA+sEbSqaWrvx +yRQDiXYxMHN0HTGbqHzjaJ8XQi0HwllwWKmsR1mLpoxSnR0irGb++Wh X-Gm-Gg: Acq92OEDBSg4BLIaAT0wgWVeISVKovrLqIFGDA9+BgNUgDFvT2w5f3G1hZbMjABjKQh /KvLPk7c7f7HumT22lSD9+rXLLUf3jf9rcTC5evD0NrHtVdrBfo5TCE1P/PqWoDh+MZvBZxnZr5 xVK2vtWi8lPT9E9AVjOC1rFcZw82IyLeFJlBBf00A7WHz6JRIakVJPDmkBggwawYBI648hv0xza YNBQyHSHsw3FHVMIqobTZx9I7CLVdI2DfA/zT+2knn/y8jwdbIZQsbadP63UgfeQz7mmLRQjSLx KwQjoE4WFrHu6OSifYKaq2rWf4R1xsR2MRsCqmI2vkmqMslzwmqKce/U+FgyKRyBF/+P/WPRmgg 4KANmkO51eKqnmVF5NTNd+9GVSI5QIyAjSbbEsBHFK4yQje9CgNdiw6q1uTCJHS/l/KxG68Ib5H ZKJFeiZen34JIFNoAALXmlgjKWMLXbj9i2/xdIrpIQ7RG7V4b8oblFP1oKbqD6QS3KNv2p7Mo9N /JDlXPPj1lRF0bJ/IBUgQHJ59VoyxY6j/n8cw== X-Received: by 2002:a05:600c:8b08:b0:48a:5501:7995 with SMTP id 5b1f17b1804b1-48e51f32ca9mr436145235e9.18.1778527155270; Mon, 11 May 2026 12:19:15 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:e687:6094:b849:9886]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e7e45ff89sm150350725e9.8.2026.05.11.12.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 12:19:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/4] clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline Date: Mon, 11 May 2026 20:19:10 +0100 Message-ID: <20260511191910.1945705-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260511191910.1945705-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the clock definitions and PLL logic required to supply the LCDC (VSPD/FCPVD/DU) blocks on the RZ/T2H (R9A09G077) SoC. The RZ/T2H display subsystem depends on a dedicated PLL (PLL3) and a set of new derived clocks. Introduce a new PLL clock type and implement rate recalculation, programming and locking sequences for PLL3 using the RZ/T2H specific divider and VCO limits. Add the corresponding muxes and divider entries, expose the LCDC core clock, and register the LCDC module clock using the correct PCLK parent. This enables the RZ/T2H clock driver to generate the display pipeline clocking tree needed by the DU and VSP-based composition engines, allowing upcoming display support to be integrated without duplicating CPG logic. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/Kconfig | 2 + drivers/clk/renesas/r9a09g077-cpg.c | 369 +++++++++++++++++++++++++++- 2 files changed, 370 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0203ecbb3882..5be45d9f9672 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -218,10 +218,12 @@ config CLK_R9A09G057 config CLK_R9A09G077 bool "RZ/T2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR + select CLK_RZV2H =20 config CLK_R9A09G087 bool "RZ/N2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR + select CLK_RZV2H =20 config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index f777601a23b9..48052e7b93fd 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -8,16 +8,23 @@ =20 #include #include +#include #include #include +#include +#include #include #include +#include #include +#include =20 #include #include #include "renesas-cpg-mssr.h" =20 +MODULE_IMPORT_NS("RZV2H_CPG"); + #define RZT2H_REG_BLOCK_SHIFT 11 #define RZT2H_REG_OFFSET_MASK GENMASK(10, 0) #define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) = | \ @@ -66,11 +73,26 @@ #define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2) #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2) #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2) +#define LCDCDIVSEL CONF_PACK(SCKCR3, 20, 4) + +#define PLL3EN FIELD_PREP_CONST(OFFSET_MASK, (0xc0)) + +#define CPG_PLLEN BIT(0) +#define CPG_PLL3_VCO_CTR0(x) ((x) + 0x4) +#define CPG_PLL3_VCO_CTR0_PDIV GENMASK(21, 16) +#define CPG_PLL3_VCO_CTR0_MDIV GENMASK(9, 0) +#define CPG_PLL3_VCO_CTR1(x) ((x) + 0x8) +#define CPG_PLL3_VCO_CTR1_KDIV GENMASK(31, 16) +#define CPG_PLL3_VCO_CTR1_SDIV GENMASK(2, 0) +#define CPG_PLL_MON(x) ((x) - 0x10) +#define CPG_PLL_MON_LOCK BIT(0) =20 enum rzt2h_clk_types { CLK_TYPE_RZT2H_DIV =3D CLK_TYPE_CUSTOM, /* Clock with divider */ CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */ CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */ + CLK_TYPE_RZT2H_PLL3, /* PLL3 Clock */ + CLK_TYPE_RZT2H_LCDCDIV, /* LCDC divider clock */ }; =20 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ @@ -83,10 +105,51 @@ enum rzt2h_clk_types { #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, .flag =3D 0) +#define DEF_PLL3(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_PLL3, .conf =3D _conf, \ + .parent =3D _parent) +#define DEF_DIV_LCDC(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_LCDCDIV, .conf =3D _conf, \ + .parent =3D _parent, .dtable =3D _dtable, .flag =3D CLK_SET_RATE_PARENT) + +struct pll_clk { + void __iomem *reg; + const struct rzv2h_pll_limits *limits; + struct device *dev; + struct rzv2h_pll_pars pll_parameters; + struct clk_hw hw; + unsigned long cur_rate; +}; + +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +struct r9a09g077_lcdc_div_clk { + const struct clk_div_table *dtable; + void __iomem *reg; + struct device *dev; + struct clk_hw hw; + u32 conf; + u8 divider; +}; + +#define to_lcdc_div_clk(_hw) \ + container_of(_hw, struct r9a09g077_lcdc_div_clk, hw) + +#define RZT2H_MAX_LCDC_DIV_TABLES 16 + +static const struct rzv2h_pll_limits r9a09g077_cpg_pll3_limits =3D { + .input_fref =3D 48 * MEGA, + .fout =3D { .min =3D 25 * MEGA, .max =3D 430 * MEGA }, + .fvco =3D { .min =3D 1600 * MEGA, .max =3D 3200 * MEGA }, + .m =3D { .min =3D 0x40, .max =3D 0x3ff }, + .p =3D { .min =3D 0x2, .max =3D 0x8 }, + .s =3D { .min =3D 0x0, .max =3D 0x6 }, + .k =3D { .min =3D -32768, .max =3D 32767 }, +}; =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G077_PCLKCAN, + LAST_DT_CORE_CLK =3D R9A09G077_LCDC_CLKD, =20 /* External Input Clocks */ CLK_EXTAL, @@ -96,10 +159,12 @@ enum clk_ids { CLK_PLL0, CLK_PLL1, CLK_PLL2, + CLK_PLL3, CLK_PLL4, CLK_SEL_CLK_PLL0, CLK_SEL_CLK_PLL1, CLK_SEL_CLK_PLL2, + CLK_SEL_CLK_PLL3, CLK_SEL_CLK_PLL4, CLK_PLL4D1, CLK_PLL4D1_DIV3, @@ -107,6 +172,7 @@ enum clk_ids { CLK_PLL4D3, CLK_PLL4D3_DIV10, CLK_PLL4D3_DIV20, + CLK_PLL4D50, CLK_SCI0ASYNC, CLK_SCI1ASYNC, CLK_SCI2ASYNC, @@ -119,6 +185,7 @@ enum clk_ids { CLK_SPI3ASYNC, CLK_DIVSELXSPI0_SCKCR, CLK_DIVSELXSPI1_SCKCR, + CLK_LCDDIVSEL, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -130,6 +197,26 @@ static const struct clk_div_table dtable_1_2[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_32[] =3D { + {0, 2}, + {1, 4}, + {2, 6}, + {3, 8}, + {4, 10}, + {5, 12}, + {6, 14}, + {7, 16}, + {8, 18}, + {9, 20}, + {10, 22}, + {11, 24}, + {12, 26}, + {13, 28}, + {14, 30}, + {15, 32}, + {0, 0}, +}; + static const struct clk_div_table dtable_6_8_16_32_64[] =3D { {6, 64}, {5, 32}, @@ -152,6 +239,7 @@ static const struct clk_div_table dtable_24_25_30_32[] = =3D { static const char * const sel_clk_pll0[] =3D { ".loco", ".pll0" }; static const char * const sel_clk_pll1[] =3D { ".loco", ".pll1" }; static const char * const sel_clk_pll2[] =3D { ".loco", ".pll2" }; +static const char * const sel_clk_pll3[] =3D { ".loco", ".pll3" }; static const char * const sel_clk_pll4[] =3D { ".loco", ".pll4" }; static const char * const sel_clk_pll4d1_div3_div4[] =3D { ".pll4d1_div3",= ".pll4d1_div4" }; static const char * const sel_clk_pll4d3_div10_div20[] =3D { ".pll4d3_div1= 0", ".pll4d3_div20" }; @@ -173,10 +261,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[= ] __initconst =3D { sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL, sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY), + DEF_MUX(".sel_clk_pll3", CLK_SEL_CLK_PLL3, SEL_PLL, + sel_clk_pll3, ARRAY_SIZE(sel_clk_pll3), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL, sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY), =20 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1), + DEF_FIXED(".pll4d50", CLK_PLL4D50, CLK_SEL_CLK_PLL4, 50, 1), + DEF_PLL3(".pll3", CLK_PLL3, CLK_PLL4D50, PLL3EN), DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), DEF_FIXED(".pll4d3", CLK_PLL4D3, CLK_SEL_CLK_PLL4, 3, 1), @@ -229,6 +321,7 @@ static const struct cpg_core_clk r9a09g077_core_clks[] = __initconst =3D { DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1), DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1), DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1), + DEF_FIXED("PCLKAL", R9A09G077_CLK_PCLKAL, CLK_PLL4D1, 24, 1), DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1), DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1), DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1), @@ -242,6 +335,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] = __initconst =3D { FSELXSPI1, dtable_6_8_16_32_64), DEF_MUX("PCLKCAN", R9A09G077_PCLKCAN, FSELCANFD, sel_clk_pll4d3_div10_div20, ARRAY_SIZE(sel_clk_pll4d3_div10_div20), 0), + DEF_DIV_LCDC("LCDCDIV", R9A09G077_LCDC_CLKD, CLK_SEL_CLK_PLL3, LCDCDIVSEL, + dtable_2_32), }; =20 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =3D { @@ -272,6 +367,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC), DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL), DEF_MOD("spi3", 602, CLK_SPI3ASYNC), + DEF_MOD("lcdc", 1204, R9A09G077_CLK_PCLKAL), DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM), DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM), }; @@ -481,6 +577,272 @@ r9a09g077_cpg_fselxspi_div_clk_register(struct device= *dev, return hw->clk; } =20 +static unsigned long r9a09g077_cpg_pll3_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + unsigned int ctr0, ctr1; + u8 pdiv, sdiv; + u64 rate; + u16 mdiv; + s16 kdiv; + + ctr0 =3D readl(CPG_PLL3_VCO_CTR0(pll_clk->reg)); + ctr1 =3D readl(CPG_PLL3_VCO_CTR1(pll_clk->reg)); + + pdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR0_PDIV, ctr0); + mdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR0_MDIV, ctr0); + kdiv =3D (s16)FIELD_GET(CPG_PLL3_VCO_CTR1_KDIV, ctr1); + sdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR1_SDIV, ctr1); + + rate =3D mul_u64_u32_shr(parent_rate, (mdiv << 16) + kdiv, 16 + sdiv); + + return DIV_ROUND_CLOSEST_ULL(rate, pdiv); +} + +static int r9a09g077_cpg_pll3_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + u64 rate_millihz; + + if (req->rate =3D=3D pll_clk->cur_rate) + return 0; + + rate_millihz =3D mul_u32_u32(req->rate, MILLI); + if (!rzv2h_get_pll_pars(pll_clk->limits, &pll_clk->pll_parameters, + rate_millihz)) { + dev_dbg(pll_clk->dev, + "failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + req->rate =3D DIV_ROUND_CLOSEST_ULL(pll_clk->pll_parameters.freq_millihz,= MILLI); + pll_clk->cur_rate =3D req->rate; + + return 0; +} + +static int r9a09g077_cpg_pll3_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzv2h_pll_pars *params =3D &pll_clk->pll_parameters; + void __iomem *offset =3D pll_clk->reg; + u32 val; + int ret; + + /* Put PLL into standby mode */ + writel(0, offset); + ret =3D readl_poll_timeout_atomic(CPG_PLL_MON(offset), + val, !(val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(pll_clk->dev, "Failed to put PLL into standby mode"); + return ret; + } + + /* Output clock setting 1 */ + val =3D readl(CPG_PLL3_VCO_CTR0(offset)); + FIELD_MODIFY(CPG_PLL3_VCO_CTR0_MDIV, &val, params->m); + FIELD_MODIFY(CPG_PLL3_VCO_CTR0_PDIV, &val, params->p); + writel(val, CPG_PLL3_VCO_CTR0(offset)); + + /* Output clock setting 2 */ + val =3D readl(CPG_PLL3_VCO_CTR1(offset)); + FIELD_MODIFY(CPG_PLL3_VCO_CTR1_KDIV, &val, params->k); + FIELD_MODIFY(CPG_PLL3_VCO_CTR1_SDIV, &val, params->s); + writel(val, CPG_PLL3_VCO_CTR1(offset)); + + writel(CPG_PLLEN, offset); + + /* PLL normal mode transition, output clock stability check */ + ret =3D readl_poll_timeout_atomic(CPG_PLL_MON(offset), + val, (val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + writel(0, offset); + dev_err(pll_clk->dev, "Failed to put PLL into normal mode"); + return ret; + } + + return 0; +} + +static const struct clk_ops r9a09g077_cpg_pll3_ops =3D { + .recalc_rate =3D r9a09g077_cpg_pll3_clk_recalc_rate, + .determine_rate =3D r9a09g077_cpg_pll3_determine_rate, + .set_rate =3D r9a09g077_cpg_pll3_set_rate, +}; + +static struct clk * __init +r9a09g077_cpg_pll3_clk_register(struct device *dev, + const struct cpg_core_clk *core, + void __iomem *addr, + struct cpg_mssr_pub *pub, + const struct rzv2h_pll_limits *limits) +{ + struct clk_init_data init =3D {}; + const struct clk *parent; + const char *parent_name; + struct pll_clk *pll_clk; + int ret; + + parent =3D pub->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + pll_clk =3D devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &r9a09g077_cpg_pll3_ops; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + pll_clk->dev =3D dev; + pll_clk->hw.init =3D &init; + pll_clk->reg =3D addr; + pll_clk->limits =3D limits; + + ret =3D devm_clk_hw_register(dev, &pll_clk->hw); + if (ret) + return ERR_PTR(ret); + + return pll_clk->hw.clk; +} + +static int r9a09g077_cpg_lcdc_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + struct pll_clk *pll_clk =3D to_pll(clk_hw_get_parent(clk_hw_get_parent(hw= ))); + u8 table[RZT2H_MAX_LCDC_DIV_TABLES] =3D { 0 }; + struct rzv2h_pll_div_pars dsi_params; + const struct clk_div_table *div; + unsigned int i =3D 0; + u64 freq_millihz; + + for (div =3D dsi_div->dtable; div->div; div++) { + if (i >=3D RZT2H_MAX_LCDC_DIV_TABLES) + return -EINVAL; + table[i++] =3D div->div; + } + + freq_millihz =3D mul_u32_u32(req->rate, MILLI); + + if (!rzv2h_get_pll_divs_pars(pll_clk->limits, &dsi_params, table, + i, freq_millihz)) { + dev_err(dsi_div->dev, + "LCDC divider failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_params.div.freq_millihz, MILLI); + req->best_parent_rate =3D req->rate * dsi_params.div.divider_value; + dsi_div->divider =3D dsi_params.div.divider_value; + pll_clk->cur_rate =3D req->best_parent_rate; + pll_clk->pll_parameters =3D dsi_params.pll; + + return 0; +} + +static int r9a09g077_cpg_lcdc_div_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + const struct clk_div_table *clkt; + bool divider_found =3D false; + u32 val, shift; + + for (clkt =3D dsi_div->dtable; clkt->div; clkt++) { + if (clkt->div =3D=3D dsi_div->divider) { + divider_found =3D true; + break; + } + } + + if (!divider_found) + return -EINVAL; + + shift =3D GET_SHIFT(dsi_div->conf); + val =3D readl(dsi_div->reg); + val &=3D ~(clk_div_mask(GET_WIDTH(dsi_div->conf)) << shift); + val |=3D clkt->val << shift; + writel(val, dsi_div->reg); + + return 0; +} + +static unsigned long +r9a09g077_cpg_lcdc_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + u32 div; + + div =3D readl(dsi_div->reg); + div >>=3D GET_SHIFT(dsi_div->conf); + div &=3D clk_div_mask(GET_WIDTH(dsi_div->conf)); + div =3D dsi_div->dtable[div].div; + + return DIV_ROUND_CLOSEST_ULL(parent_rate, div); +} + +static const struct clk_ops r9a09g077_cpg_lcdc_div_ops =3D { + .recalc_rate =3D r9a09g077_cpg_lcdc_div_recalc_rate, + .determine_rate =3D r9a09g077_cpg_lcdc_div_determine_rate, + .set_rate =3D r9a09g077_cpg_lcdc_div_set_rate, +}; + +static struct clk * __init +r9a09g077_cpg_lcdc_div_clk_register(struct device *dev, + const struct cpg_core_clk *core, + void __iomem *addr, + struct cpg_mssr_pub *pub) +{ + struct r9a09g077_lcdc_div_clk *clk_hw_data; + struct clk **clks =3D pub->clks; + struct clk_init_data init; + const struct clk *parent; + const char *parent_name; + struct clk_hw *hw; + int ret; + + parent =3D clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data =3D devm_kzalloc(dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->dtable =3D core->dtable; + clk_hw_data->reg =3D addr; + clk_hw_data->conf =3D core->conf; + clk_hw_data->dev =3D dev; + clk_hw_data->divider =3D 32; /* Initialize divider for LCDC */ + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &r9a09g077_cpg_lcdc_div_ops; + init.flags =3D core->flag; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + hw =3D &clk_hw_data->hw; + hw->init =3D &init; + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw->clk; +} + static struct clk * __init r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *= core, const struct cpg_mssr_info *info, @@ -497,6 +859,11 @@ r9a09g077_cpg_clk_register(struct device *dev, const s= truct cpg_core_clk *core, return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub); case CLK_TYPE_RZT2H_FSELXSPI: return r9a09g077_cpg_fselxspi_div_clk_register(dev, core, addr, pub); + case CLK_TYPE_RZT2H_PLL3: + return r9a09g077_cpg_pll3_clk_register(dev, core, pub->base1 + offset, + pub, &r9a09g077_cpg_pll3_limits); + case CLK_TYPE_RZT2H_LCDCDIV: + return r9a09g077_cpg_lcdc_div_clk_register(dev, core, addr, pub); default: return ERR_PTR(-EINVAL); } --=20 2.54.0