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Mon, 11 May 2026 10:27:39 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Carolina Jubran , Simon Horman , Gal Pressman , Kees Cook , Dragos Tatulea , , , Subject: [PATCH net-next 1/5] net/mlx5e: remove channel count limit for XOR8 RSS hash Date: Mon, 11 May 2026 20:27:15 +0300 Message-ID: <20260511172719.330490-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260511172719.330490-1-tariqt@nvidia.com> References: <20260511172719.330490-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002321:EE_|DS0PR12MB7826:EE_ X-MS-Office365-Filtering-Correlation-Id: e66f99ef-0eb9-4eb4-8b2a-08deaf82a99b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|82310400026|18002099003|56012099003|22082099003|11063799003; X-Microsoft-Antispam-Message-Info: tgvARal6la+2HLQ7msL/1ECGn9mDt6qmNVCken2oZ21Ve2o1p0L+X2auokKbA83oKbE3V88tSe0npwUqiYlw40GS9L8BleJmI8srfYBd7bd0D3dhtcjJUi2DRaPsOJFznL/rCNcoB5uURmIP9h+ISJtGg8xyHLzdeI7qe+Owv65NCovAEj6FtS5cGAQvb8RvSiPfqQ8a7rIp/OX1Dzre+U3jvPjLFDcucnpUl9fUe5FO0kw6//lpHj0Eocx1Sz3zyp1S0/5jnVsGb9cr8p/IuxDj3u4eD+DtFGHHa7TJ8znp/pQB3wH1trYOnIBN6LrC1pQoUtuH8OUUkarAIT9w5qBbx+vOfgoK+9iJCczdeftII6DfX2uv3EEbeHwDp4xA99uNe8bYOHSoXL1me0G9jLLxBdbbHtQxKxPCFwgwjx9xg70j2J4HqNdGxaN+4lIGD5CH4VHyMaMWmvF1ZoCGQninE+CqaUyLnre/+udXN66WrKfsuJJ0s0oLSqPPxHgmh7TJQ5MnnNrKHNyKfLat7fFV1i7Aq7zMqxS5YKaaZgWu51lBWmMNDBNRfYZW83f+OIR/8J7d3/QTMNL0vSkCGZDVnpzl2XAtz24hyYlB8TISDElCoqjujkw6LEcYHJZTeVPAWjgdtLDRAJSEnJWE9He/jDMNwbnGbcW79LkxEO0wW3POVLwjXvjNJkd7kqTnvIQGpR3NuRjD1Jnz2/SqXcIdo/jZeI5VnAxsDSMRtAY= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(1800799024)(82310400026)(18002099003)(56012099003)(22082099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zWn1D8mlzaxjLw43jQ96Owgtfl+HiU37IPj+8MWnFAn+SMagUIB7BSsHC+vMaMf0/ywMEJW0zlBrU+f9ruaVSv0o5N8tV8dwGatVEstu7WOql0KQg4CMyTa3TtYP4DaLhTUSnHfg5p7eguMNz3fRjTvvQfL0fDhLVonKDEPYp40zaJIDll3L+GD/3EM7pj30VgzPbcPnZviqm+zsWI18zOlBorypsAEPycY3m4LrfyTmmT8BdnUA+pEV9pYv1Kiqc7LtmyAOyArCp+LcvKW6U7hDJxQZjXiJmQZ5TLyNGhG+IKjiIB9YUmbgwC2M19jwHQ2AuxP4m4GPsQ1c+6+rithLrXeu6Uj3wV7MBYLbmydpSIfX5/2xnMNQdgMIcm9Jt1VDm1FrZSgjhmVMHf5cXLHhqIDtOPBNG77iQQSF1vnKQL8F7VpVY2qBxLon29UM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 17:28:05.8035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e66f99ef-0eb9-4eb4-8b2a-08deaf82a99b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7826 Content-Type: text/plain; charset="utf-8" From: Yael Chemla mlx5e_ethtool_set_channels() and mlx5e_rxfh_hfunc_check() rejected channel counts that would produce an indirection table larger than 256 entries when the XOR8 hash function was active. This check was introduced in commit 49e6c9387051 ("net/mlx5e: RSS, Block XOR hash with over 128 channels"). XOR8 yields an 8-bit hash, so in practice only up to 256 entries in the indirection table can be reached due to limited entropy. However, this does not provide a strong justification for prohibiting larger indirection tables. Remove the limitation. Signed-off-by: Yael Chemla Reviewed-by: Nimrod Oren Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rqt.c | 7 --- .../net/ethernet/mellanox/mlx5/core/en/rqt.h | 1 - .../ethernet/mellanox/mlx5/core/en_ethtool.c | 48 ------------------- 3 files changed, 56 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.c index 8d9a3b5ec973..bcafb4bf9415 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c @@ -179,13 +179,6 @@ u32 mlx5e_rqt_size(struct mlx5_core_dev *mdev, unsigne= d int num_channels) return min_t(u32, rqt_size, max_cap_rqt_size); } =20 -#define MLX5E_MAX_RQT_SIZE_ALLOWED_WITH_XOR8_HASH 256 - -unsigned int mlx5e_rqt_max_num_channels_allowed_for_xor8(void) -{ - return MLX5E_MAX_RQT_SIZE_ALLOWED_WITH_XOR8_HASH / MLX5E_UNIFORM_SPREAD_R= QT_FACTOR; -} - void mlx5e_rqt_destroy(struct mlx5e_rqt *rqt) { mlx5_core_destroy_rqt(rqt->mdev, rqt->rqtn); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.h index 2f9e04a8418f..e0bc30308c77 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h @@ -38,7 +38,6 @@ static inline u32 mlx5e_rqt_get_rqtn(struct mlx5e_rqt *rq= t) } =20 u32 mlx5e_rqt_size(struct mlx5_core_dev *mdev, unsigned int num_channels); -unsigned int mlx5e_rqt_max_num_channels_allowed_for_xor8(void); int mlx5e_rqt_redirect_direct(struct mlx5e_rqt *rqt, u32 rqn, u32 *vhca_id= ); int mlx5e_rqt_redirect_indir(struct mlx5e_rqt *rqt, u32 *rqns, u32 *vhca_i= ds, unsigned int num_rqns, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index bb61e2179078..a6da0219723c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -511,17 +511,6 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, =20 mutex_lock(&priv->state_lock); =20 - if (mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc =3D=3D ETH_RSS_HASH= _XOR) { - unsigned int xor8_max_channels =3D mlx5e_rqt_max_num_channels_allowed_fo= r_xor8(); - - if (count > xor8_max_channels) { - err =3D -EINVAL; - netdev_err(priv->netdev, "%s: Requested number of channels (%d) exceeds= the maximum allowed by the XOR8 RSS hfunc (%d)\n", - __func__, count, xor8_max_channels); - goto out; - } - } - /* If RXFH is configured, changing the channels number is allowed only if * it does not require resizing the RSS table. This is because the previo= us * configuration may no longer be compatible with the new RSS table. @@ -1501,29 +1490,6 @@ static int mlx5e_get_rxfh(struct net_device *netdev,= struct ethtool_rxfh_param * return 0; } =20 -static int mlx5e_rxfh_hfunc_check(struct mlx5e_priv *priv, - const struct ethtool_rxfh_param *rxfh, - struct netlink_ext_ack *extack) -{ - unsigned int count; - - count =3D priv->channels.params.num_channels; - - if (rxfh->hfunc =3D=3D ETH_RSS_HASH_XOR) { - unsigned int xor8_max_channels =3D mlx5e_rqt_max_num_channels_allowed_fo= r_xor8(); - - if (count > xor8_max_channels) { - NL_SET_ERR_MSG_FMT_MOD( - extack, - "Number of channels (%u) exceeds the max for XOR8 RSS (%u)", - count, xor8_max_channels); - return -EINVAL; - } - } - - return 0; -} - static int mlx5e_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh, struct netlink_ext_ack *extack) @@ -1535,16 +1501,11 @@ static int mlx5e_set_rxfh(struct net_device *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); - if (err) - goto unlock; - err =3D mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, rxfh->indir, rxfh->key, hfunc =3D=3D ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, rxfh->input_xfrm =3D=3D RXH_XFRM_NO_CHANGE ? NULL : &symmetric); =20 -unlock: mutex_unlock(&priv->state_lock); return err; } @@ -1561,10 +1522,6 @@ static int mlx5e_create_rxfh_context(struct net_devi= ce *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); - if (err) - goto unlock; - err =3D mlx5e_rx_res_rss_init(priv->rx_res, rxfh->rss_context, priv->channels.params.num_channels); if (err) @@ -1601,16 +1558,11 @@ static int mlx5e_modify_rxfh_context(struct net_dev= ice *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); - if (err) - goto unlock; - err =3D mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, rxfh->indir, rxfh->key, hfunc =3D=3D ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, rxfh->input_xfrm =3D=3D RXH_XFRM_NO_CHANGE ? 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Mon, 11 May 2026 10:27:44 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Carolina Jubran , Simon Horman , Gal Pressman , Kees Cook , Dragos Tatulea , , , Subject: [PATCH net-next 2/5] net/mlx5e: advertise max RSS indirection table size to ethtool Date: Mon, 11 May 2026 20:27:16 +0300 Message-ID: <20260511172719.330490-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260511172719.330490-1-tariqt@nvidia.com> References: <20260511172719.330490-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002326:EE_|MN2PR12MB4077:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ba9ea9c-27b8-428f-bee4-08deaf82ac72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|56012099003|18002099003|22082099003|11063799003; X-Microsoft-Antispam-Message-Info: mW539ee9RctI5IPH4BLYZPvNYgguoy2IjEv4Iv71JTQXeM/ngKpi+fQkgWvEgJ2T91MTyheIV/Nj4tAR8x4uU9a5/O/vTLcmAc1U/l5usQe2v1hI8TDTvaKW/gQMf9NVzzRD2kKPi71Sv/Dfqj9XwRltbokxNzbFT4LVGdADiVM5eKpQXo+sybYB4aTXL8yGlGwpON/dzDj/7bwl1I0SDM7PkYMTIfo2wUoyuRZUiDElZlMs6obylj3j56kYdqBAvRDuAWAKv8ypUKIPL68auS/F7mZOb/9pASQjSde0DvKdF4VHg7Qf4PvQxeWYl6gzbVsP8vDmrFnvCBFJGU5LfDjkBIf/nvt9JJ72qLob2c20UcTvnNmOu1nNg58k6fS2Kdy70bbZfzm3DTLSVz2qBFY2+yyakj2OpmZY+pmuWMRWsz+RXcbsl8/pS9MCUkBpBN73GrxWSbnxnQCVlhGAhXpBhwuT8HKxjG4MjMHpusSdtbQbUsD7fkagKnpxEbNHr0XdZZvD7K+r8umk3cEwwmDUl4IAYJI0954XTLDvtUAi9H9DqNbCcmWRUCmayvKc58nOd1DSwhy9p2B8DSCmMlMYF1anA7XIMzbnJ/CvK/pkmKfoViKyd6YZvnUWt8CJeFMXo6qdrRTq3hgXNid5iszmN3w8968RSWz8MJ0QSzRTASdOePsRJrZEccEtYkpuK4MNgiq9fr6RHV8XeEEnMcsAxBCZeRPNTfnHtRiMgyQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(7416014)(376014)(56012099003)(18002099003)(22082099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pfqpu3Zt2VZNhSlcntrPW1bPSzpo0xBLFLHV+tORxLvBcGqxzE+BUJTgmLbV/oLsqb/hbtzusgsP5/LWMC0pPLXo4iMV0YZuDB9g7zSRHhStBuVk5m4LQPRxyvdDdjMDnvIJ1stu8jjkQMoReg44CZ6ICIHUP+dDykAFUsa2daGGKCXK1CsrV/vZe8S2GDvqUZwLPR79Eks0/3fUzxVDuMOddUA/yKXgOgH1pPgW/1dHj16ADOyPydfbIkMiKUSqaUHV4Bsm1WfctcURcx8ptybNuu8r0mJfgiyHeoC2qU66OjC1QoyeisQDr9UlegeT6iHNBO+2umiQICNY8IAKZJYsa1h82+VF34Vsmw/rabNevKpmyMTGBtWbiR3cU6dM4BggM6u0faRtvT5VNNU6xNHpBzdJUG8sn2cNtuZItNPFz6pEPLNQTL3XZfkDyLDS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 17:28:10.5669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ba9ea9c-27b8-428f-bee4-08deaf82ac72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4077 Content-Type: text/plain; charset="utf-8" From: Yael Chemla Set rxfh_indir_space to the maximum indirection table size the driver can support: the next power of two above MLX5E_MAX_NUM_CHANNELS times MLX5E_UNIFORM_SPREAD_RQT_FACTOR. Without this, ethtool_rxfh_ctxs_can_resize() returns -EINVAL, blocking non-default RSS contexts from tracking indirection table size changes when the channel count changes. Signed-off-by: Yael Chemla Reviewed-by: Nimrod Oren Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c | 2 -- drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 5 +++++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.c index bcafb4bf9415..a3382f6a6b74 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.c @@ -168,8 +168,6 @@ int mlx5e_rqt_init_indir(struct mlx5e_rqt *rqt, struct = mlx5_core_dev *mdev, return err; } =20 -#define MLX5E_UNIFORM_SPREAD_RQT_FACTOR 2 - u32 mlx5e_rqt_size(struct mlx5_core_dev *mdev, unsigned int num_channels) { u32 rqt_size =3D max_t(u32, MLX5E_INDIR_MIN_RQT_SIZE, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.h index e0bc30308c77..680700e7437f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h @@ -7,6 +7,7 @@ #include =20 #define MLX5E_INDIR_MIN_RQT_SIZE (BIT(8)) +#define MLX5E_UNIFORM_SPREAD_RQT_FACTOR 2 =20 struct mlx5_core_dev; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Carolina Jubran , Simon Horman , Gal Pressman , Kees Cook , Dragos Tatulea , , , Subject: [PATCH net-next 3/5] net/mlx5e: resize non-default RSS indirection tables on channel change Date: Mon, 11 May 2026 20:27:17 +0300 Message-ID: <20260511172719.330490-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260511172719.330490-1-tariqt@nvidia.com> References: <20260511172719.330490-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|DS7PR12MB9474:EE_ X-MS-Office365-Filtering-Correlation-Id: 352fcfbc-ee04-4a96-0534-08deaf82b0fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|22082099003|56012099003|18002099003|11063799003; X-Microsoft-Antispam-Message-Info: pRz5jsJD0x3mu1/bXqdgypwSjHx85A2guWbQI0NHrFmZtZ5CZTT2aQHCFRpUEEQYjjy3BiCot6WcqQKYENDnzlcAPc/vL8pJZINY7AyHfzLk/ju3B5O2i/65gljVNzKFrOo223FNyiLQo5TOxpwmvLBd7oyvyYJzF9hXIkYcgzPB6Y89880zyk/Pi4JVe9eapkKgt9NC2ADeGWtFHj+3wtyF64EU9DoWgMvNtOQ6krOBwGpz5MrM3a9cLtztTPcX8JFG39gNTFAFdLlGC5Q9EXgm9xNW9JmXCow3rEaBT7K9CfJDrAVUMw5SBYdRWskdIzwNlIQ7nGCBByPwn/yj+fXE/GwEinjBG2Q/Ge4bgp86Fw/DR7+00CHbw+cBdhX0CuIBJihrp3gKJzhUdwklI//o65LBtwyveorXw9YA6+0dv4reK79NpqHdBl6WpVWgH7FAmidDGThAts92nK9aNqpc77sbmAHaVqYzTjqlvh3bp/r2bvH35kEY47OZs7YV0dbvA1e8vWgmm/IsycvXRFmMx0Ju51wp/ajMsiFeV5EeUGFSk9CKI7DzfpInqQjyODCyjLnjBHxS7iRFQerIYiq1G1gy3ZHhHY49gxPy3BFG/QyWnKACFxKWrbGG2cCgActoT4GCxMd8cu2frWb0Zms6KYtrwCKPtYTmnPFwvdLrmSIPLXtFkbVpWlR94tffoCYs2SQUo9O91tgGx6RUBPS85VilkpfAa7021rXLFAY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014)(22082099003)(56012099003)(18002099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wqf7nWjEMahbQ0H+9vSbJbT2hiJdZ/tCYkDIIER2kCe6DCfiEniy0crvh3I5QQrEMMTOXqYRW3lSQsgTzwfXoAY6ZrYGDuXliMBV7AQs7uoCuCVV/VP8V9ATIvELrKp68Nt74cilRsP4lXCbHtKNEzJckGylkOgf6iqHtcHKPDJLJIsYiluQdD2PhWjX/z1jtFzK4JJ4ruPgPASc8zdH2sIR3sXuuoRaw+CxPoMCgNnyZHuyEv82tiA94OsM/8lQyAuYzYhOOpfRHDTpxw3KWfVfMDPcGucq6GGHqv+IoJ+5AiHGMzM/mkpnlKTzDROMGGDbkVsErJfRmVLm5uQ8mgg+elpr5Q1rroCeddvOF2ff/Qh2nEPsIN7tP1NLxMSzaBn/PIf7A4otic1t21DCx2odKC7chWhNueegMXYIuJc88uGTKz/dDsadLTY+IhI9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 17:28:18.1759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 352fcfbc-ee04-4a96-0534-08deaf82b0fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9474 Content-Type: text/plain; charset="utf-8" From: Yael Chemla When the channel count changes and the RQT size changes with it, a problem arise for non-default RSS contexts. The driver-side indirection table grows actual_table_size without filling the new entries; stale entries from a prior larger configuration may be re-exposed, causing mlx5e_calc_indir_rqns() to WARN on an out-of-range index. Replace mlx5e_rss_params_indir_modify_actual_size() with mlx5e_rss_ctx_resize(), which fills new entries by replicating the existing pattern, matching what ethtool_rxfh_ctxs_resize() does for the same case. And restrict the loop to non-default contexts. Call ethtool_rxfh_ctxs_can_resize() before acquiring state_lock to validate that all non-default contexts can be resized, and ethtool_rxfh_ctxs_resize() after releasing it to fold or unfold their indirection tables. Both functions acquire rss_lock internally and cannot be called under state_lock. RTNL, held by all set_channels callers, serialises context creation and deletion making the pre-lock check safe. Guard both ethtool calls on mlx5e_rx_res_rss_cnt() > 1: skip the validation and resize when no non-default contexts exist. This naturally covers representors and IPoIB, which share mlx5e_ethtool_set_channels() but cannot have non-default RSS contexts. Signed-off-by: Yael Chemla Reviewed-by: Nimrod Oren Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rss.c | 16 +++++++-- .../net/ethernet/mellanox/mlx5/core/en/rss.h | 3 +- .../ethernet/mellanox/mlx5/core/en/rx_res.c | 15 ++++++-- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 35 +++++++++++++++++-- 4 files changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index a2ec67a122d9..992a78580a40 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -85,9 +85,21 @@ bool mlx5e_rss_get_inner_ft_support(struct mlx5e_rss *rs= s) return rss->params.inner_ft_support; } =20 -void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels) +void mlx5e_rss_set_indir_actual_size(struct mlx5e_rss *rss, u32 size) { - rss->indir.actual_table_size =3D mlx5e_rqt_size(rss->mdev, num_channels); + rss->indir.actual_table_size =3D size; +} + +/* Handles non-default contexts, replicate existing pattern into new entri= es, + * matching what ethtool_rxfh_ctxs_resize() does. + */ +void mlx5e_rss_ctx_resize(struct mlx5e_rss *rss, u32 new_size) +{ + u32 old_size =3D rss->indir.actual_table_size; + u32 i; + + for (i =3D old_size; i < new_size; i++) + rss->indir.table[i] =3D rss->indir.table[i % old_size]; } =20 int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index 17664757a561..e48070e02979 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -34,7 +34,7 @@ struct mlx5e_rss; int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, u32 actual_table_size, u32 max_table_size); void mlx5e_rss_params_indir_cleanup(struct mlx5e_rss_params_indir *indir); -void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels); +void mlx5e_rss_ctx_resize(struct mlx5e_rss *rss, u32 new_size); struct mlx5e_rss * mlx5e_rss_init(struct mlx5_core_dev *mdev, const struct mlx5e_rss_params *params, @@ -46,6 +46,7 @@ void mlx5e_rss_refcnt_dec(struct mlx5e_rss *rss); unsigned int mlx5e_rss_refcnt_read(struct mlx5e_rss *rss); =20 bool mlx5e_rss_get_inner_ft_support(struct mlx5e_rss *rss); +void mlx5e_rss_set_indir_actual_size(struct mlx5e_rss *rss, u32 size); u32 mlx5e_rss_get_tirn(struct mlx5e_rss *rss, enum mlx5_traffic_types tt, bool inner); bool mlx5e_rss_valid_tir(struct mlx5e_rss *rss, enum mlx5_traffic_types tt= , bool inner); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.c index 92974b11ec75..d81a91eb7664 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c @@ -42,11 +42,20 @@ static u32 *get_vhca_ids(struct mlx5e_rx_res *res, int = offset) =20 void mlx5e_rx_res_rss_update_num_channels(struct mlx5e_rx_res *res, u32 nc= h) { + u32 new_size =3D mlx5e_rqt_size(res->mdev, nch); int i; =20 - for (i =3D 0; i < MLX5E_MAX_NUM_RSS; i++) { - if (res->rss[i]) - mlx5e_rss_params_indir_modify_actual_size(res->rss[i], nch); + WARN_ON_ONCE(res->rss_active); + + /* Default context */ + mlx5e_rss_set_indir_actual_size(res->rss[0], new_size); + + /* Non-default contexts */ + for (i =3D 1; i < MLX5E_MAX_NUM_RSS; i++) { + if (res->rss[i]) { + mlx5e_rss_ctx_resize(res->rss[i], new_size); + mlx5e_rss_set_indir_actual_size(res->rss[i], new_size); + } } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index c483008e33e9..4462cf29e977 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -499,11 +499,15 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *pri= v, { struct mlx5e_params *cur_params =3D &priv->channels.params; unsigned int count =3D ch->combined_count; + int new_rqt_size, cur_rqt_size; struct mlx5e_params new_params; bool arfs_enabled; + bool has_rss_ctxs; bool opened; int err =3D 0; =20 + ASSERT_RTNL(); + if (!count) { netdev_info(priv->netdev, "%s: combined_count=3D0 not supported\n", __func__); @@ -513,16 +517,33 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *pri= v, if (cur_params->num_channels =3D=3D count) return 0; =20 + new_rqt_size =3D mlx5e_rqt_size(priv->mdev, count); + /* Validate that all non-default RSS contexts can be resized before + * committing to the channel count change. + * ethtool_rxfh_ctxs_can_resize() acquires rss_lock internally and + * cannot be called under state_lock (rss_lock -> state_lock ordering). + */ + has_rss_ctxs =3D priv->rx_res && mlx5e_rx_res_rss_cnt(priv->rx_res) > 1; + if (has_rss_ctxs) { + err =3D ethtool_rxfh_ctxs_can_resize(priv->netdev, new_rqt_size); + if (err) + return err; + } + mutex_lock(&priv->state_lock); =20 + if (!priv->rx_res) { + err =3D -EINVAL; + goto out; + } + + cur_rqt_size =3D mlx5e_rqt_size(priv->mdev, cur_params->num_channels); + /* If RXFH is configured, changing the channels number is allowed only if * it does not require resizing the RSS table. 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Carolina Jubran , Simon Horman , Gal Pressman , Kees Cook , Dragos Tatulea , , , Subject: [PATCH net-next 4/5] net/mlx5e: resize configured default RSS context table on channel change Date: Mon, 11 May 2026 20:27:18 +0300 Message-ID: <20260511172719.330490-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260511172719.330490-1-tariqt@nvidia.com> References: <20260511172719.330490-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002323:EE_|DM6PR12MB4108:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b73a113-4b45-4610-9b09-08deaf82b498 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|1800799024|82310400026|22082099003|18002099003|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: v+/8yMdJCTjglomwbfCZWCji1ljFSAfElNJEh/8iA3h9AmKkvu9pptOYzHrUpP1z1B8nq3Oo52scq0xYZJZ8ninDwmWOsg+Zg+gbnisdSNv03QVHIib1GcPlo933kABSbYucza1euevyMfNos7Og6M3x/ys4DiccBUZfZopuPER5dJcDPq0qCmhjA+K2eIAAthoo9cK3CFG29lCw9L3moGq6KiazRayt8xEnzoKjDAjBqLCXsJCkOqWUgea4xg03UTnsmh0Xa07jNext9KV8DfkU8X00tOBfNDVueAO4V2kRbyUcB/5U508PnZ7v+UzgM9ekznA4smSy2jRUWsDPLMEBNglsurtaARxcS5wOZmkaftiyQxWRwnM/EptIJUaUyVjdIvOcx4DEaOd/YaMlXNxwFMhsWNMZtBHzJq+7QW6Hw9/1t3zG0oCwfC9RaG78O8DpsSf4eaaSKnAynVSXeFL/geoWtZVz611cWj4/n7Haogzv4/Y+N6K0RfrKEMGnq2VcIXJHMCcrNGbOPOprF4/tO88keH+C7aH5U1Z6cbW7Uy9FKsOPexHgmqKJci+ECT5D/ITXd3QUuQcz2NpZuJlGFbjV3+VXHPXFIDUV8AvYO69zql9JwaK3qK3WXNsZSsUoxRqi9mGYWcty2ZDhraMmRCSaSGVigNdBbhf5WL5RqUiKGQpT7aE4r9GPA9H6laWX5xezyvUft9q+vAmqhEbUs1ut1A5NOwi1rxMvU4Q= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(1800799024)(82310400026)(22082099003)(18002099003)(56012099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /HHw8T6whY7+DhzH8G8c4iefVgQqtBSV6Ooncz7hSEOw1dHlQ87hJ5lNblmdhyBbRAH80wN1P9p55j+IWDBC+IRe376kb5np82gZewe4FnGXLhSe02Zk2fco6kiByA1f2ambS2tQ2tS4tf2ONUEmfXlxRCJh2x8Y+xBMyJrFC9RiKC8pT++qCfZoqLLeXX0KG9fGpQSOccadVnZmYpq+4nHoGiYP7zIFgepyJottVuaN9zMyZMQ603lJdtonH6AqR6cBv2mMvWZzsOQ8U9eizLSke0peJE2gyrxnWtLTnwL0/rbw8eTQSmqm/nhyOpCgaS9wKcVcDIfVYytm6uNBLlCKIMKBWZvzY/Ak5Ej5IFqzUAA/lYzha3Bu7kIf24qDsD8PFn0HY2kBMH/9mgX1eZjfDB037yIICesiFAFWji9R1XnXi5Pt7bEYqOjvklql X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 17:28:24.2418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b73a113-4b45-4610-9b09-08deaf82b498 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002323.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4108 Content-Type: text/plain; charset="utf-8" From: Yael Chemla mlx5e_ethtool_set_channels() rejected channel count changes that required a different RQT size when the default context indirection table was user-configured. This restriction was introduced by commit ee3572409f74 ("net/mlx5e: RSS, Block changing channels number when RXFH is configured"). Lift the restriction. Validate the resize upfront with ethtool_rxfh_indir_can_resize(), then fold or unfold the table in-place via ethtool_rxfh_indir_resize() inside state_lock, before mlx5e_safe_switch_params(), so the preactivate callback sees the correct table content when it programs the HW. Signed-off-by: Yael Chemla Reviewed-by: Nimrod Oren Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rss.c | 13 +++++++++ .../net/ethernet/mellanox/mlx5/core/en/rss.h | 3 +++ .../ethernet/mellanox/mlx5/core/en/rx_res.c | 27 ++++++++++++------- .../ethernet/mellanox/mlx5/core/en/rx_res.h | 4 +-- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 22 +++++++-------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 9 +++---- 6 files changed, 49 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index 992a78580a40..de435df7ca50 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB // Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. =20 +#include #include "rss.h" =20 #define mlx5e_rss_warn(__dev, format, ...) \ @@ -85,6 +86,11 @@ bool mlx5e_rss_get_inner_ft_support(struct mlx5e_rss *rs= s) return rss->params.inner_ft_support; } =20 +u32 *mlx5e_rss_get_indir_table(struct mlx5e_rss *rss) +{ + return rss->indir.table; +} + void mlx5e_rss_set_indir_actual_size(struct mlx5e_rss *rss, u32 size) { rss->indir.actual_table_size =3D size; @@ -102,6 +108,13 @@ void mlx5e_rss_ctx_resize(struct mlx5e_rss *rss, u32 n= ew_size) rss->indir.table[i] =3D rss->indir.table[i % old_size]; } =20 +void mlx5e_rss_indir_resize(struct mlx5e_rss *rss, struct net_device *netd= ev, + u32 new_size) +{ + ethtool_rxfh_indir_resize(netdev, rss->indir.table, + rss->indir.actual_table_size, new_size); +} + int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, u32 actual_table_size, u32 max_table_size) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index e48070e02979..1bb0434612a4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -35,6 +35,8 @@ int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_i= ndir *indir, u32 actual_table_size, u32 max_table_size); void mlx5e_rss_params_indir_cleanup(struct mlx5e_rss_params_indir *indir); void mlx5e_rss_ctx_resize(struct mlx5e_rss *rss, u32 new_size); +void mlx5e_rss_indir_resize(struct mlx5e_rss *rss, struct net_device *netd= ev, + u32 new_size); struct mlx5e_rss * mlx5e_rss_init(struct mlx5_core_dev *mdev, const struct mlx5e_rss_params *params, @@ -46,6 +48,7 @@ void mlx5e_rss_refcnt_dec(struct mlx5e_rss *rss); unsigned int mlx5e_rss_refcnt_read(struct mlx5e_rss *rss); =20 bool mlx5e_rss_get_inner_ft_support(struct mlx5e_rss *rss); +u32 *mlx5e_rss_get_indir_table(struct mlx5e_rss *rss); void mlx5e_rss_set_indir_actual_size(struct mlx5e_rss *rss, u32 size); u32 mlx5e_rss_get_tirn(struct mlx5e_rss *rss, enum mlx5_traffic_types tt, bool inner); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.c index d81a91eb7664..e940635f5dcb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c @@ -40,15 +40,31 @@ static u32 *get_vhca_ids(struct mlx5e_rx_res *res, int = offset) return multi_vhca ? res->rss_vhca_ids + offset : NULL; } =20 -void mlx5e_rx_res_rss_update_num_channels(struct mlx5e_rx_res *res, u32 nc= h) +/* Updates the indirection table SW shadow, does not update the HW resourc= es yet + */ +void mlx5e_rx_res_rss_update_num_channels(struct mlx5e_rx_res *res, u32 nc= h, + struct net_device *netdev) { u32 new_size =3D mlx5e_rqt_size(res->mdev, nch); int i; =20 WARN_ON_ONCE(res->rss_active); =20 - /* Default context */ + /* Default context: fold/unfold user-configured table, then update size + * and reset to uniform when unconfigured. + */ + mlx5e_rss_indir_resize(res->rss[0], netdev, new_size); + + /* mlx5e_rss_indir_resize() is a no-op when the table is not + * user-configured. actual_table_size is updated after the resize + * because ethtool_rxfh_indir_resize() uses it as the old size to + * replicate the pattern; updating it first would make the grow a no-op. + * It must be updated before mlx5e_rss_set_indir_uniform() so that + * the uniform fill covers all new entries, not just the old ones. + */ mlx5e_rss_set_indir_actual_size(res->rss[0], new_size); + if (!netif_is_rxfh_configured(netdev)) + mlx5e_rss_set_indir_uniform(res->rss[0], nch); =20 /* Non-default contexts */ for (i =3D 1; i < MLX5E_MAX_NUM_RSS; i++) { @@ -218,13 +234,6 @@ static void mlx5e_rx_res_rss_disable(struct mlx5e_rx_r= es *res) } } =20 -/* Updates the indirection table SW shadow, does not update the HW resourc= es yet */ -void mlx5e_rx_res_rss_set_indir_uniform(struct mlx5e_rx_res *res, unsigned= int nch) -{ - WARN_ON_ONCE(res->rss_active); - mlx5e_rss_set_indir_uniform(res->rss[0], nch); -} - void mlx5e_rx_res_rss_get_rxfh(struct mlx5e_rx_res *res, u32 rss_idx, u32 *indir, u8 *key, u8 *hfunc, bool *symmetric) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.h b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.h index 675780120a20..8fff18d64978 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.h @@ -48,7 +48,6 @@ void mlx5e_rx_res_xsk_update(struct mlx5e_rx_res *res, st= ruct mlx5e_channels *ch unsigned int ix, bool xsk); =20 /* Configuration API */ -void mlx5e_rx_res_rss_set_indir_uniform(struct mlx5e_rx_res *res, unsigned= int nch); void mlx5e_rx_res_rss_get_rxfh(struct mlx5e_rx_res *res, u32 rss_idx, u32 *indir, u8 *key, u8 *hfunc, bool *symmetric); @@ -68,7 +67,8 @@ int mlx5e_rx_res_rss_destroy(struct mlx5e_rx_res *res, u3= 2 rss_idx); int mlx5e_rx_res_rss_cnt(struct mlx5e_rx_res *res); int mlx5e_rx_res_rss_index(struct mlx5e_rx_res *res, struct mlx5e_rss *rss= ); struct mlx5e_rss *mlx5e_rx_res_rss_get(struct mlx5e_rx_res *res, u32 rss_i= dx); -void mlx5e_rx_res_rss_update_num_channels(struct mlx5e_rx_res *res, u32 nc= h); +void mlx5e_rx_res_rss_update_num_channels(struct mlx5e_rx_res *res, u32 nc= h, + struct net_device *netdev); =20 /* Workaround for hairpin */ struct mlx5e_rss_params_hash mlx5e_rx_res_get_current_hash(struct mlx5e_rx= _res *res); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index 4462cf29e977..300d1cb2e070 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -501,6 +501,7 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, unsigned int count =3D ch->combined_count; int new_rqt_size, cur_rqt_size; struct mlx5e_params new_params; + struct mlx5e_rss *rss0; bool arfs_enabled; bool has_rss_ctxs; bool opened; @@ -538,19 +539,16 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *pri= v, } =20 cur_rqt_size =3D mlx5e_rqt_size(priv->mdev, cur_params->num_channels); + rss0 =3D mlx5e_rx_res_rss_get(priv->rx_res, 0); =20 - /* If RXFH is configured, changing the channels number is allowed only if - * it does not require resizing the RSS table. This is because the previo= us - * configuration may no longer be compatible with the new RSS table. - */ - if (netif_is_rxfh_configured(priv->netdev)) { - if (new_rqt_size !=3D cur_rqt_size) { - err =3D -EINVAL; - netdev_err(priv->netdev, - "%s: RXFH is configured, block changing channels number that affect= s RSS table size (new: %d, current: %d)\n", - __func__, new_rqt_size, cur_rqt_size); - goto out; - } + if (!ethtool_rxfh_indir_can_resize(priv->netdev, + mlx5e_rss_get_indir_table(rss0), + cur_rqt_size, new_rqt_size)) { + netdev_err(priv->netdev, + "%s: cannot resize RSS table (%u -> %u); reset indirection table to = allow this change\n", + __func__, cur_rqt_size, new_rqt_size); + err =3D -EINVAL; + goto out; } =20 /* Don't allow changing the number of channels if HTB offload is active, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 85b1ccbd351f..a904e468c197 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3296,12 +3296,9 @@ static int mlx5e_num_channels_changed(struct mlx5e_p= riv *priv) } =20 /* This function may be called on attach, before priv->rx_res is created.= */ - if (priv->rx_res) { - mlx5e_rx_res_rss_update_num_channels(priv->rx_res, count); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Nimrod Oren , Yael Chemla , Carolina Jubran , Simon Horman , Gal Pressman , Kees Cook , Dragos Tatulea , , , Subject: [PATCH net-next 5/5] net/mlx5e: increase RSS indirection table spread factor Date: Mon, 11 May 2026 20:27:19 +0300 Message-ID: <20260511172719.330490-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260511172719.330490-1-tariqt@nvidia.com> References: <20260511172719.330490-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|DM6PR12MB4354:EE_ X-MS-Office365-Filtering-Correlation-Id: e93986bf-5f88-4282-4d66-08deaf82b72e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700016|18002099003|56012099003|22082099003|11063799003; X-Microsoft-Antispam-Message-Info: SoVJwc5VgTj3Ba3ouOmsZ3lBrys3vBTF6AxqGEXxeGCuMB9l3ZH+jZjiCq1VwvmT5ET/FmJLzoaurolm+Sn/kB5rj4H/xZ69FpJqXbDSkMeXDEZpzUntaotjESb/BsFRZJn+mvYg/iAb1BI1fXFm/dhLqf9yCOJA15LbmYmZbXkdnzj/9ekDIGv1sK7jvoOTkz27+EnJ/saRa/rdQdr0tpImuU2SpZN++nO2P59EGtPG9H/Z/Xst+BufaVl+DkmVAz8181CGeLIOz6Hhyyjj34DukcYFODdDo5EE5QmVkt8RVXK81UOEVDHfKgdoHsmsyD6yFi7EnvqksCLInXTrmZ1wyFGUrjmtzIikEmx89P4VJVwdY/UkWJa1ki76xVDPNOGUFge3psUClC3liDp5msP9XzmQZzkEgowwFMDYRhdFbXs+xMA6FTHPtoawUgYR7BjI4MoGrlpKrV1p3ZPsN5AaYIceEXAMUOu259/jdKy0U7dkI0zSXuU6tkXXLUO1f5bQHO63Y3Y+hRASRQZ6J6xAIoui69Gzj/zI46/FjQ4+gES6QS7lX7xDDqeluMzDzXVBL2Ew1uZEdQvJoHQ/eaBf5yjJsvS1S9uslHXkJGvampJGk5yOGzLld+hqfYcdUPac/9ycI9bNP67RlOzpUXHzpEO6jJvmNuQPm6y419IWtBcA90wCDm8baBxBy3s3cl4AxOCe/AwjfdeddPtTvpheXZex22ECgvnZSCwzKjs= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700016)(18002099003)(56012099003)(22082099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EBeqxH3zRSM9CL8v5xp7qNT5Oqjvro12rMxP05hPRlfYAgRi5yic386YLvglvxYiDv2zL9TDO6bil64tHZoZzDKsOtrlYy2JtmUsj2kk2hXcn+6rIXKCqTi9RbD9CP9a2XhZClrKnNrbTa0I1EJupz7lVaOXbIAmFHPRV88MwuboYQvenOwTG4fZL+zB/kxxy3OxNzaS5cTnkz+K/Rws/2sE9srnk4OyO+/5vP/yRM9SxaDl0egY3xaqSRX3S31+A/9umtly6lfQbEELk8aliaBY/YUvL+XIicjCsCDPB+Uguyca4jKUmsueOug77abdnB117Irzb8FE8QdHCz1MAIpixUaQUR4aGAwBG2Ilm/dRZXp952oo/4/UWIlIk+f43zCPHJCKxnOYri/392CSAg3lNQvjtFQR8OIYrlUWuSipZVz1C/BOkOeDPZfAapNN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 17:28:28.5573 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e93986bf-5f88-4282-4d66-08deaf82b72e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4354 Content-Type: text/plain; charset="utf-8" From: Yael Chemla Increase the RQT uniform spread factor from 2 to 4 so that each channel gets more indirection table entries and traffic is spread more evenly. For num_channels > 64 imbalance drops from up to ~50% to up to ~25%. For 64 or fewer channels the 256 entry minimum already provides at least 4x coverage and the table size is unchanged by this commit. This satisfies the minimum 4x coverage requirement validated by the generic RSS selftest commit 9e3d4dae9832 ("selftests: drv-net: rss: validate min RSS table size"). The 4x spread factor is best-effort and the table size is always capped by the device's log_max_rqt_size capability. Signed-off-by: Yael Chemla Reviewed-by: Nimrod Oren Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rqt.h index 680700e7437f..c6d0a92b132c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rqt.h @@ -7,7 +7,7 @@ #include =20 #define MLX5E_INDIR_MIN_RQT_SIZE (BIT(8)) -#define MLX5E_UNIFORM_SPREAD_RQT_FACTOR 2 +#define MLX5E_UNIFORM_SPREAD_RQT_FACTOR 4 =20 struct mlx5_core_dev; =20 --=20 2.44.0