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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965d36a12sm17694642b3a.27.2026.05.11.00.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 00:51:53 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 1/2] dt-bindings: display: verisilicon,dc: generalize for DCUltra Lite variant Date: Mon, 11 May 2026 15:51:41 +0800 Message-ID: <20260511075142.54752-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260511075142.54752-1-a0987203069@gmail.com> References: <20260511075142.54752-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the verisilicon,dc base schema to accommodate the Nuvoton MA35D1 DCUltra Lite (a previous generation of the DC8000 series) which has a different clock topology, no reset control, and a single output. - Replace the fixed clock/reset item lists with minItems/maxItems ranges so sub-schemas can enforce variant-specific constraints - Add a 'port' property (single-port alias) alongside the existing 'ports' for single-output variants - Remove the mandatory 'ports' requirement from the base schema; sub-schemas shall enforce their own port topology - Add a 'select' stanza so the validator matches any node whose compatible contains a known Verisilicon DC string, including SoC-specific glue - Relax additionalProperties to allow unevaluatedProperties enforcement in sub-schemas - Fix a minor whitespace issue in the port@0 description Add nuvoton,ma35d1-dcu.yaml as a sub-schema for the Nuvoton MA35D1 DCUltra Lite display controller: The Nuvoton MA35D1 integrates the Verisilicon DCUltra Lite display controller. It is a single-output display controller with a 32-bit RGB (DPI) interface. Unlike the DC8000, it does not have discoverable chip identity registers, does not support the CONFIG_EX commit path, and uses dedicated IRQ status/enable registers at offsets 0x147C/0x1480. The clock topology uses two clocks (bus gate and pixel divider) and does not require explicit reset control from the driver. Signed-off-by: Joey Lu --- .../bindings/display/nuvoton,ma35d1-dcu.yaml | 94 +++++++++++++++++++ .../bindings/display/verisilicon,dc.yaml | 64 +++++++------ 2 files changed, 131 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/nuvoton,ma35d= 1-dcu.yaml diff --git a/Documentation/devicetree/bindings/display/nuvoton,ma35d1-dcu.y= aml b/Documentation/devicetree/bindings/display/nuvoton,ma35d1-dcu.yaml new file mode 100644 index 000000000000..9279004ae27c --- /dev/null +++ b/Documentation/devicetree/bindings/display/nuvoton,ma35d1-dcu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/nuvoton,ma35d1-dcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 DCUltra Lite display controller + +maintainers: + - Joey Lu + +description: + The Nuvoton MA35D1 integrates the Verisilicon DCUltra Lite display + controller. It is a single-output display controller with a 32-bit + RGB (DPI) interface. + +select: + properties: + compatible: + contains: + enum: + - nuvoton,ma35d1-dcu + required: + - compatible + +allOf: + - $ref: http://devicetree.org/schemas/display/verisilicon,dc.yaml# + +properties: + compatible: + const: nuvoton,ma35d1-dcu + + reg: + maxItems: 1 + description: + Register range of the DCUltra Lite controller. The address space + is 0x2000 bytes. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus clock that gates register access (DCU_GATE) + - description: Pixel clock divider for display timing (DCUP_DIV) + + clock-names: + items: + - const: core + - const: pix0 + + resets: + maxItems: 1 + description: + Optional reset for the display controller. The driver does not + assert or deassert this reset; it may be used by firmware or + boot loaders to bring the hardware to a clean state. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port to the downstream display device (e.g. RGB panel). + The DCUltra Lite supports a single parallel RGB output. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - port + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display@40260000 { + compatible =3D "nuvoton,ma35d1-dcu"; + reg =3D <0x40260000 0x2000>; + interrupts =3D ; + clocks =3D <&clk DCU_GATE>, <&clk DCUP_DIV>; + clock-names =3D "core", "pix0"; + resets =3D <&sys MA35D1_RESET_DISP>; + + port { + dpi_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 9dc35ab973f2..00884529f8c1 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -9,15 +9,34 @@ title: Verisilicon DC-series display controllers maintainers: - Icenowy Zheng =20 +description: + Verisilicon DC-series display controllers. + +# Select any node whose compatible contains one of the known Verisilicon DC +# or DC-derived compatible strings, including SoC-specific glue variants. +select: + properties: + compatible: + contains: + enum: + - verisilicon,dc + - thead,th1520-dc8200 + - nuvoton,ma35d1-dcu + required: + - compatible + properties: $nodename: pattern: "^display@[0-9a-f]+$" =20 compatible: - items: - - enum: - - thead,th1520-dc8200 - - const: verisilicon,dc # DC IPs have discoverable ID/revision regis= ters + # Enumerated in full so the schema validator can verify any compatible + # string against this list, including those from child schemas. + contains: + enum: + - verisilicon,dc + - thead,th1520-dc8200 + - nuvoton,ma35d1-dcu =20 reg: maxItems: 1 @@ -26,32 +45,24 @@ properties: maxItems: 1 =20 clocks: - items: - - description: DC Core clock - - description: DMA AXI bus clock - - description: Configuration AHB bus clock - - description: Pixel clock of output 0 - - description: Pixel clock of output 1 + minItems: 2 + maxItems: 5 =20 clock-names: - items: - - const: core - - const: axi - - const: ahb - - const: pix0 - - const: pix1 + minItems: 2 + maxItems: 5 =20 resets: - items: - - description: DC Core reset - - description: DMA AXI bus reset - - description: Configuration AHB bus reset + minItems: 1 + maxItems: 3 =20 reset-names: - items: - - const: core - - const: axi - - const: ahb + minItems: 1 + maxItems: 3 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Single video output port for single-output variants. =20 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -59,7 +70,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: The first output channel , endpoint 0 should be + description: The first output channel, endpoint 0 should be used for DPI format output and endpoint 1 should be used for DP format output. =20 @@ -75,9 +86,8 @@ required: - interrupts - clocks - clock-names - - ports =20 -additionalProperties: false +additionalProperties: true =20 examples: - | --=20 2.43.0 From nobody Sat Jun 13 03:28:27 2026 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADA3F3A9D9C for ; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965d36a12sm17694642b3a.27.2026.05.11.00.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 00:51:56 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 2/2] drm/verisilicon: add support for Nuvoton MA35D1 DCUltra Lite display controller Date: Mon, 11 May 2026 15:51:42 +0800 Message-ID: <20260511075142.54752-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260511075142.54752-1-a0987203069@gmail.com> References: <20260511075142.54752-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Nuvoton MA35D1 SoC integrates a Verisilicon DCUltra Lite display controller, which is a previous generation of the DC8000 series. While the general register layout is similar to the DC8000, there are several key differences that require per-variant handling in the driver. Add a vs_dc_info platform data structure (in vs_hwdb.h) to describe per-IP-variant capabilities, and use it throughout the driver to select the correct code paths at runtime. Key differences between DC8000 and DCUltra Lite handled: 1. No chip identity registers (0x0020-0x0030): DCUltra Lite uses static platform data instead of reading model/revision/customer_id from HW. 2. No CONFIG_EX commit mechanism: DC8000 uses registers at 0x1CC0 (FB_CONFIG_EX), 0x24D8 (FB_TOP_LEFT), 0x24E0 (FB_BOTTOM_RIGHT), 0x2510 (FB_BLEND_CONFIG), 0x2518 (PANEL_CONFIG_EX). DCUltra Lite omits all of these and instead uses enable/reset bits in FB_CONFIG (bit 0 =3D enable, bit 4 =3D reset) for direct framebuffer updates. 3. No PANEL_START register (0x1CCC): DCUltra Lite panel output starts when PANEL_CONFIG.RUNNING is set; no separate multi-display sync start register is needed. 4. Different IRQ registers: DCUltra Lite uses 0x147C (IRQ_STA) / 0x1480 (IRQ_EN); DC8000 uses 0x0010 (IRQ_ACK) / 0x0014 (IRQ_EN). 5. Different clock/reset topology: DCUltra Lite requires only "core" (bus gate) and "pix0" (pixel divider) clocks with no reset lines managed by the driver. DC8000 needs core/axi/ahb clocks and three resets. 6. Single output only: DCUltra Lite has one display output; per-output index logic is still in place but display_count is fixed at 1. 7. Reduced register space: max_register is 0x2000 vs DC8000's 0x2544. Add the "nuvoton,ma35d1-dcu" compatible string to the OF match table, extend Kconfig to allow building on ARCH_MA35 platforms, and expose vs_formats_no_yuv444 as the default format table for DCUltra Lite (YUV444 blending is a DC8000-only feature). All changes have been tested on Nuvoton MA35D1 hardware and are functioning correctly. Signed-off-by: Joey Lu --- drivers/gpu/drm/verisilicon/Kconfig | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 28 ++-- drivers/gpu/drm/verisilicon/vs_crtc.c | 13 +- drivers/gpu/drm/verisilicon/vs_dc.c | 129 ++++++++++++------ drivers/gpu/drm/verisilicon/vs_dc.h | 1 + drivers/gpu/drm/verisilicon/vs_drm.c | 16 ++- drivers/gpu/drm/verisilicon/vs_hwdb.c | 2 +- drivers/gpu/drm/verisilicon/vs_hwdb.h | 25 ++++ .../gpu/drm/verisilicon/vs_primary_plane.c | 43 +++--- .../drm/verisilicon/vs_primary_plane_regs.h | 2 + 10 files changed, 187 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisili= con/Kconfig index 7cce86ec8603..295d246eb4b4 100644 --- a/drivers/gpu/drm/verisilicon/Kconfig +++ b/drivers/gpu/drm/verisilicon/Kconfig @@ -2,7 +2,7 @@ config DRM_VERISILICON_DC tristate "DRM Support for Verisilicon DC-series display controllers" depends on DRM && COMMON_CLK - depends on RISCV || COMPILE_TEST + depends on RISCV || ARCH_MA35 || COMPILE_TEST select DRM_BRIDGE_CONNECTOR select DRM_CLIENT_SELECTION select DRM_DISPLAY_HELPER diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/veri= silicon/vs_bridge.c index 7a93049368db..225af322de32 100644 --- a/drivers/gpu/drm/verisilicon/vs_bridge.c +++ b/drivers/gpu/drm/verisilicon/vs_bridge.c @@ -164,13 +164,16 @@ static void vs_bridge_enable_common(struct vs_crtc *c= rtc, VSDC_DISP_PANEL_CONFIG_CLK_EN); regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), VSDC_DISP_PANEL_CONFIG_RUNNING); - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_RUNNING(output)); =20 - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + if (dc->info->has_config_ex) { + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + } } =20 static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, @@ -228,14 +231,17 @@ static void vs_bridge_atomic_disable(struct drm_bridg= e *bridge, struct vs_dc *dc =3D crtc->dc; unsigned int output =3D crtc->id; =20 - regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, - VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | - VSDC_DISP_PANEL_START_RUNNING(output)); regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), VSDC_DISP_PANEL_CONFIG_RUNNING); =20 - regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), - VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + if (dc->info->has_config_ex) { + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); + } } =20 static const struct drm_bridge_funcs vs_dpi_bridge_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisi= licon/vs_crtc.c index 9080344398ca..2f3e6d41c657 100644 --- a/drivers/gpu/drm/verisilicon/vs_crtc.c +++ b/drivers/gpu/drm/verisilicon/vs_crtc.c @@ -18,6 +18,7 @@ #include "vs_dc.h" #include "vs_dc_top_regs.h" #include "vs_drm.h" +#include "vs_hwdb.h" #include "vs_plane.h" =20 static void vs_crtc_atomic_disable(struct drm_crtc *crtc, @@ -132,7 +133,11 @@ static int vs_crtc_enable_vblank(struct drm_crtc *crtc) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); + if (dc->info->family =3D=3D VS_DC_FAMILY_DCULTRA_LITE) + regmap_write(dc->regs, VSDC_DISP_IRQ_EN, BIT(0)); + else + regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(vcrtc->id)); =20 return 0; } @@ -142,7 +147,11 @@ static void vs_crtc_disable_vblank(struct drm_crtc *cr= tc) struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id= )); + if (dc->info->family =3D=3D VS_DC_FAMILY_DCULTRA_LITE) + regmap_write(dc->regs, VSDC_DISP_IRQ_EN, 0); + else + regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, + VSDC_TOP_IRQ_VSYNC(vcrtc->id)); } =20 static const struct drm_crtc_funcs vs_crtc_funcs =3D { diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c index dad9967bc10b..82a6a26f6d81 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -9,21 +9,45 @@ #include =20 #include "vs_crtc.h" +#include "vs_crtc_regs.h" #include "vs_dc.h" #include "vs_dc_top_regs.h" #include "vs_drm.h" #include "vs_hwdb.h" =20 -static const struct regmap_config vs_dc_regmap_cfg =3D { +static const struct regmap_config vs_dc8000_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D sizeof(u32), - /* VSDC_OVL_CONFIG_EX(1) */ .max_register =3D 0x2544, }; =20 +static const struct regmap_config vs_dcultra_lite_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D sizeof(u32), + .max_register =3D 0x2000, +}; + +static const struct vs_dc_info vs_dc8000_info =3D { + .family =3D VS_DC_FAMILY_DC8000, + .has_chip_id =3D true, + .has_config_ex =3D true, + .regmap_cfg =3D &vs_dc8000_regmap_cfg, +}; + +static const struct vs_dc_info vs_dcultra_lite_info =3D { + .family =3D VS_DC_FAMILY_DCULTRA_LITE, + .display_count =3D 1, + .has_chip_id =3D false, + .has_config_ex =3D false, + .regmap_cfg =3D &vs_dcultra_lite_regmap_cfg, + .formats =3D &vs_formats_no_yuv444, +}; + static const struct of_device_id vs_dc_driver_dt_match[] =3D { - { .compatible =3D "verisilicon,dc" }, + { .compatible =3D "verisilicon,dc", .data =3D &vs_dc8000_info }, + { .compatible =3D "nuvoton,ma35d1-dcu", .data =3D &vs_dcultra_lite_info }, {}, }; MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); @@ -33,6 +57,13 @@ static irqreturn_t vs_dc_irq_handler(int irq, void *priv= ate) struct vs_dc *dc =3D private; u32 irqs; =20 + if (dc->info->family =3D=3D VS_DC_FAMILY_DCULTRA_LITE) { + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &irqs); + if (irqs & BIT(0)) + vs_drm_handle_irq(dc, VSDC_TOP_IRQ_VSYNC(0)); + return IRQ_HANDLED; + } + regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); =20 vs_drm_handle_irq(dc, irqs); @@ -43,6 +74,7 @@ static irqreturn_t vs_dc_irq_handler(int irq, void *priva= te) static int vs_dc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + const struct vs_dc_info *info; struct vs_dc *dc; void __iomem *regs; unsigned int port_count, i; @@ -55,6 +87,10 @@ static int vs_dc_probe(struct platform_device *pdev) return -ENODEV; } =20 + info =3D of_device_get_match_data(dev); + if (!info) + return -ENODEV; + port_count =3D of_graph_get_port_count(dev->of_node); if (!port_count) { dev_err(dev, "can't find DC downstream ports\n"); @@ -75,15 +111,31 @@ static int vs_dc_probe(struct platform_device *pdev) if (!dc) return -ENOMEM; =20 - dc->rsts[0].id =3D "core"; - dc->rsts[1].id =3D "axi"; - dc->rsts[2].id =3D "ahb"; + dc->info =3D info; =20 - ret =3D devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, - dc->rsts); - if (ret) { - dev_err(dev, "can't get reset lines\n"); - return ret; + if (info->family =3D=3D VS_DC_FAMILY_DC8000) { + dc->rsts[0].id =3D "core"; + dc->rsts[1].id =3D "axi"; + dc->rsts[2].id =3D "ahb"; + + ret =3D devm_reset_control_bulk_get_optional_shared(dev, + VSDC_RESET_COUNT, dc->rsts); + if (ret) { + dev_err(dev, "can't get reset lines\n"); + return ret; + } + + dc->axi_clk =3D devm_clk_get_enabled(dev, "axi"); + if (IS_ERR(dc->axi_clk)) { + dev_err(dev, "can't get axi clock\n"); + return PTR_ERR(dc->axi_clk); + } + + dc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(dc->ahb_clk)) { + dev_err(dev, "can't get ahb clock\n"); + return PTR_ERR(dc->ahb_clk); + } } =20 dc->core_clk =3D devm_clk_get_enabled(dev, "core"); @@ -92,28 +144,18 @@ static int vs_dc_probe(struct platform_device *pdev) return PTR_ERR(dc->core_clk); } =20 - dc->axi_clk =3D devm_clk_get_enabled(dev, "axi"); - if (IS_ERR(dc->axi_clk)) { - dev_err(dev, "can't get axi clock\n"); - return PTR_ERR(dc->axi_clk); - } - - dc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); - if (IS_ERR(dc->ahb_clk)) { - dev_err(dev, "can't get ahb clock\n"); - return PTR_ERR(dc->ahb_clk); - } - irq =3D platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "can't get irq\n"); return irq; } =20 - ret =3D reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); - if (ret) { - dev_err(dev, "can't deassert reset lines\n"); - return ret; + if (info->family =3D=3D VS_DC_FAMILY_DC8000) { + ret =3D reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); + if (ret) { + dev_err(dev, "can't deassert reset lines\n"); + return ret; + } } =20 regs =3D devm_platform_ioremap_resource(pdev, 0); @@ -123,23 +165,30 @@ static int vs_dc_probe(struct platform_device *pdev) goto err_rst_assert; } =20 - dc->regs =3D devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); + dc->regs =3D devm_regmap_init_mmio(dev, regs, info->regmap_cfg); if (IS_ERR(dc->regs)) { ret =3D PTR_ERR(dc->regs); goto err_rst_assert; } =20 - ret =3D vs_fill_chip_identity(dc->regs, &dc->identity); - if (ret) - goto err_rst_assert; + if (info->has_chip_id) { + ret =3D vs_fill_chip_identity(dc->regs, &dc->identity); + if (ret) + goto err_rst_assert; =20 - dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, - dc->identity.revision, dc->identity.customer_id); + dev_info(dev, "Found DC%x rev %x customer %x\n", + dc->identity.model, dc->identity.revision, + dc->identity.customer_id); =20 - if (port_count > dc->identity.display_count) { - dev_err(dev, "too many downstream ports than HW capability\n"); - ret =3D -EINVAL; - goto err_rst_assert; + if (port_count > dc->identity.display_count) { + dev_err(dev, "too many downstream ports than HW capability\n"); + ret =3D -EINVAL; + goto err_rst_assert; + } + } else { + /* Fill identity from platform data */ + dc->identity.display_count =3D info->display_count; + dc->identity.formats =3D info->formats; } =20 for (i =3D 0; i < dc->identity.display_count; i++) { @@ -168,7 +217,8 @@ static int vs_dc_probe(struct platform_device *pdev) return 0; =20 err_rst_assert: - reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); + if (info->family =3D=3D VS_DC_FAMILY_DC8000) + reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); return ret; } =20 @@ -180,7 +230,8 @@ static void vs_dc_remove(struct platform_device *pdev) =20 dev_set_drvdata(&pdev->dev, NULL); =20 - reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); + if (dc->info->family =3D=3D VS_DC_FAMILY_DC8000) + reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); } =20 static void vs_dc_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h index ed1016f18758..f0613519af37 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -31,6 +31,7 @@ struct vs_dc { struct clk *pix_clk[VSDC_MAX_OUTPUTS]; struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; =20 + const struct vs_dc_info *info; struct vs_drm_dev *drm_dev; struct vs_chip_identity identity; }; diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisil= icon/vs_drm.c index fd259d53f49f..ff0fc6673006 100644 --- a/drivers/gpu/drm/verisilicon/vs_drm.c +++ b/drivers/gpu/drm/verisilicon/vs_drm.c @@ -27,6 +27,7 @@ #include "vs_dc.h" #include "vs_dc_top_regs.h" #include "vs_drm.h" +#include "vs_hwdb.h" =20 #define DRIVER_NAME "verisilicon" #define DRIVER_DESC "Verisilicon DC-series display controller driver" @@ -72,12 +73,19 @@ static struct drm_mode_config_helper_funcs vs_mode_conf= ig_helper_funcs =3D { .atomic_commit_tail =3D drm_atomic_helper_commit_tail, }; =20 -static void vs_mode_config_init(struct drm_device *drm) +static void vs_mode_config_init(struct drm_device *drm, struct vs_dc *dc) { drm->mode_config.min_width =3D 0; drm->mode_config.min_height =3D 0; - drm->mode_config.max_width =3D 8192; - drm->mode_config.max_height =3D 8192; + + if (dc->info->family =3D=3D VS_DC_FAMILY_DCULTRA_LITE) { + drm->mode_config.max_width =3D 1920; + drm->mode_config.max_height =3D 1080; + } else { + drm->mode_config.max_width =3D 8192; + drm->mode_config.max_height =3D 8192; + } + drm->mode_config.funcs =3D &vs_mode_config_funcs; drm->mode_config.helper_private =3D &vs_mode_config_helper_funcs; } @@ -125,7 +133,7 @@ int vs_drm_initialize(struct vs_dc *dc, struct platform= _device *pdev) if (ret) return ret; =20 - vs_mode_config_init(drm); + vs_mode_config_init(drm, dc); =20 /* Enable connectors polling */ drm_kms_helper_poll_init(drm); diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisi= licon/vs_hwdb.c index 09336af0900a..39402d75d841 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.c +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c @@ -78,7 +78,7 @@ static const u32 vs_formats_array_with_yuv444[] =3D { /* TODO: non-RGB formats */ }; =20 -static const struct vs_formats vs_formats_no_yuv444 =3D { +const struct vs_formats vs_formats_no_yuv444 =3D { .array =3D vs_formats_array_no_yuv444, .num =3D ARRAY_SIZE(vs_formats_array_no_yuv444) }; diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisi= licon/vs_hwdb.h index 92192e4fa086..655cf93ca3aa 100644 --- a/drivers/gpu/drm/verisilicon/vs_hwdb.h +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h @@ -14,6 +14,29 @@ struct vs_formats { unsigned int num; }; =20 +enum vs_dc_family { + VS_DC_FAMILY_DC8000, + VS_DC_FAMILY_DCULTRA_LITE, +}; + +/** + * struct vs_dc_info - per-SoC DC platform data + * @family: DC IP family (DC8000, DCUltra Lite, etc.) + * @display_count: number of display outputs (0 =3D auto-detect from DT/HW) + * @has_chip_id: whether chip identity registers exist + * @has_config_ex: whether CONFIG_EX commit mechanism exists + * @regmap_cfg: regmap configuration for this variant + * @formats: supported pixel formats (NULL =3D auto-detect from chip ID) + */ +struct vs_dc_info { + enum vs_dc_family family; + u32 display_count; + bool has_chip_id; + bool has_config_ex; + const struct regmap_config *regmap_cfg; + const struct vs_formats *formats; +}; + struct vs_chip_identity { u32 model; u32 revision; @@ -23,6 +46,8 @@ struct vs_chip_identity { const struct vs_formats *formats; }; =20 +extern const struct vs_formats vs_formats_no_yuv444; + int vs_fill_chip_identity(struct regmap *regs, struct vs_chip_identity *ident); =20 diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/d= rm/verisilicon/vs_primary_plane.c index 1f2be41ae496..197d5d683e22 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane.c +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c @@ -55,8 +55,9 @@ static int vs_primary_plane_atomic_check(struct drm_plane= *plane, =20 static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) { - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_COMMIT); + if (dc->info->has_config_ex) + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_COMMIT); } =20 static void vs_primary_plane_atomic_enable(struct drm_plane *plane, @@ -69,11 +70,13 @@ static void vs_primary_plane_atomic_enable(struct drm_p= lane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); - regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, - VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); + if (dc->info->has_config_ex) { + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, + VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); + } =20 vs_primary_plane_commit(dc, output); } @@ -88,8 +91,9 @@ static void vs_primary_plane_atomic_disable(struct drm_pl= ane *plane, unsigned int output =3D vcrtc->id; struct vs_dc *dc =3D vcrtc->dc; =20 - regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), - VSDC_FB_CONFIG_EX_FB_EN); + if (dc->info->has_config_ex) + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); =20 vs_primary_plane_commit(dc, output); } @@ -126,6 +130,11 @@ static void vs_primary_plane_atomic_update(struct drm_= plane *plane, VSDC_FB_CONFIG_UV_SWIZZLE_EN, vs_state->format.uv_swizzle); =20 + /* DCUltra Lite requires explicit enable/reset bits in FB_CONFIG */ + if (!dc->info->has_config_ex) + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE | VSDC_FB_CONFIG_RESET); + dma_addr =3D vs_fb_get_dma_addr(fb, &state->src); =20 regmap_write(dc->regs, VSDC_FB_ADDRESS(output), @@ -133,16 +142,18 @@ static void vs_primary_plane_atomic_update(struct drm= _plane *plane, regmap_write(dc->regs, VSDC_FB_STRIDE(output), fb->pitches[0]); =20 - regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), - VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); - regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), - VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, - state->crtc_y + state->crtc_h)); regmap_write(dc->regs, VSDC_FB_SIZE(output), VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); =20 - regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), - VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); + if (dc->info->has_config_ex) { + regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); + regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, + state->crtc_y + state->crtc_h)); + regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), + VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); + } =20 vs_primary_plane_commit(dc, output); } diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/= gpu/drm/verisilicon/vs_primary_plane_regs.h index cbb125c46b39..288064760b48 100644 --- a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h @@ -16,6 +16,8 @@ #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) =20 #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) +#define VSDC_FB_CONFIG_ENABLE BIT(0) +#define VSDC_FB_CONFIG_RESET BIT(4) #define VSDC_FB_CONFIG_CLEAR_EN BIT(8) #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) #define VSDC_FB_CONFIG_ROT(v) ((v) << 11) --=20 2.43.0