From nobody Sat Jun 13 03:31:15 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EDA2B2F6188; Mon, 11 May 2026 06:51:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482321; cv=none; b=kmLf76rGYm2UgKeun8YASpqa2Vx01w4voR4aBNaFdtoaBnwhdRziJr+IPf7drRNhhAA/5zgAs9x8ihzZ2g3yQ6ataHiTcqIhVhFl7meD/Qn+4aut/sTN6lIMwuPodwb6f5DFZO8tBHhh5c00TiaERpdbMb/XCtauGW67/2X0+5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482321; c=relaxed/simple; bh=4J8l7fsKFXFSBuTKZXv5aOaG/rKtRLTDXjblKlUbBFM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dbS6MOUG8Yp72VTRiF1eCu5Yyu8p7vDOfO8ETO+AGnzG3PtRRfqsJdH4LMqNxeUt/7YI2k/SLjMoWwUkIJJ5uGv4XKdOgfElpYDPw8QtVp7CxIUZOzRO0LVmf5y5l1awk2fE8dI/pCP/MZib1sBcMcizPmVoOuCWT3AbfzVgS6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxrcCNfAFq5owIAA--.2961S3; Mon, 11 May 2026 14:51:57 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAx28GEfAFqAOh+AA--.42931S3; Mon, 11 May 2026 14:51:49 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] LoongArch: KVM: Check msgint feature in interrupt post Date: Mon, 11 May 2026 14:51:42 +0800 Message-Id: <20260511065146.680650-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260511065146.680650-1-maobibo@loongson.cn> References: <20260511065146.680650-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAx28GEfAFqAOh+AA--.42931S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Interrupt AVEC is valid only if VM has msgint feature, and this feature is checked in interrupt handling. Since interrupt handling is executing in VM context switch, and it is hot path, here move the feature checking in interrupt post rather than interrupt handling. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 6 ++++++ arch/loongarch/kvm/interrupt.c | 5 ----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index 3784ab4ccdb5..ccf938d89f02 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -95,12 +95,18 @@ struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm,= int cpuid); */ static inline void kvm_queue_irq(struct kvm_vcpu *vcpu, unsigned int irq) { + if (!kvm_guest_has_msgint(&vcpu->arch) && (irq =3D=3D INT_AVEC)) + return; + set_bit(irq, &vcpu->arch.irq_pending); clear_bit(irq, &vcpu->arch.irq_clear); } =20 static inline void kvm_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int irq) { + if (!kvm_guest_has_msgint(&vcpu->arch) && (irq =3D=3D INT_AVEC)) + return; + clear_bit(irq, &vcpu->arch.irq_pending); set_bit(irq, &vcpu->arch.irq_clear); } diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index a18c60dffbba..48dd56aa4dc5 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -36,8 +36,6 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigne= d int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; dmsintc_inject_irq(vcpu); fallthrough; case INT_TI: @@ -75,9 +73,6 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned = int priority) =20 switch (priority) { case INT_AVEC: - if (!kvm_guest_has_msgint(&vcpu->arch)) - break; - fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: --=20 2.39.3 From nobody Sat Jun 13 03:31:15 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC4422E9729; Mon, 11 May 2026 06:51:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482322; cv=none; b=VZDQi3fP6nnToatewbmbDyOzJI5htZQrMTMkX3TFfzrKqLk1xdRCJQ7ydK996gtGxL2pnejkn+ik+njFPoXaNUxIr5DRaQ00vdGAsGhYHUcO2NwG6ZPi/G78tjzwRiLdO8ubXzJb3GxINyTXQNG0Sao+cWL3I483xvNnIXddwZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482322; c=relaxed/simple; bh=bkdPL4aU5AVbNIddBr38AQpKTrA6P6EU41ehqvOotp4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=msPETxe3hTcA9b3E40TmGCGjzmmlbEnj9/HpeL4Cwcn4Hv5Rqve8jPTms1PzQjxd0Y9oPRXZEqcpfHVxDUMNS2hoS0YK40knhKNifFQCUvyzV87UszGguxhXMR0Wv0Q0uwtJSQssSy+O8pkRrXPQE+hZ344D2uVjUbHJld28Pl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx13iOfAFq64wIAA--.2026S3; Mon, 11 May 2026 14:51:58 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAx28GEfAFqAOh+AA--.42931S4; Mon, 11 May 2026 14:51:57 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] LoongArch: KVM: Use existing macro about interrupt bit mask Date: Mon, 11 May 2026 14:51:43 +0800 Message-Id: <20260511065146.680650-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260511065146.680650-1-maobibo@loongson.cn> References: <20260511065146.680650-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAx28GEfAFqAOh+AA--.42931S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With interrupt post, register CSR_GINTC and CSR_GSTAT is used, and CSR_GSTAT is used for percpu interrupt injection and CSR_GINTC is for external hardware interrupt injection. Here use existing macro about interrupt bit of register CSR_GINTC and CSR_GSTAT, rather than hard coded constant value. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 33 +++++++++++++++------------ 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index ccf938d89f02..e504c3822e6f 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -10,22 +10,27 @@ #include =20 /* Controlled by 0x5 guest estat */ -#define CPU_SIP0 (_ULCAST_(1)) -#define CPU_SIP1 (_ULCAST_(1) << 1) -#define CPU_PMU (_ULCAST_(1) << 10) -#define CPU_TIMER (_ULCAST_(1) << 11) -#define CPU_IPI (_ULCAST_(1) << 12) -#define CPU_AVEC (_ULCAST_(1) << 14) +#define CPU_SIP0 BIT(INT_SWI0) +#define CPU_SIP1 BIT(INT_SWI1) +#define CPU_PMU BIT(INT_PCOV) +#define CPU_TIMER BIT(INT_TI) +#define CPU_IPI BIT(INT_IPI) +#define CPU_AVEC BIT(INT_AVEC) +#define KVM_ESTAT_IRQ_MASK (CPU_SIP0 | CPU_SIP1 | CPU_PMU | CPU_TIMER \ + | CPU_IPI | CPU_AVEC) =20 /* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */ -#define CPU_IP0 (_ULCAST_(1)) -#define CPU_IP1 (_ULCAST_(1) << 1) -#define CPU_IP2 (_ULCAST_(1) << 2) -#define CPU_IP3 (_ULCAST_(1) << 3) -#define CPU_IP4 (_ULCAST_(1) << 4) -#define CPU_IP5 (_ULCAST_(1) << 5) -#define CPU_IP6 (_ULCAST_(1) << 6) -#define CPU_IP7 (_ULCAST_(1) << 7) +#define GINTC_VIP_DELTA (INT_HWI0 - CSR_GINTC_VIP_SHIFT) +#define CPU_IP0 BIT(INT_HWI0 - GINTC_VIP_DELTA) +#define CPU_IP1 BIT(INT_HWI1 - GINTC_VIP_DELTA) +#define CPU_IP2 BIT(INT_HWI2 - GINTC_VIP_DELTA) +#define CPU_IP3 BIT(INT_HWI3 - GINTC_VIP_DELTA) +#define CPU_IP4 BIT(INT_HWI4 - GINTC_VIP_DELTA) +#define CPU_IP5 BIT(INT_HWI5 - GINTC_VIP_DELTA) +#define CPU_IP6 BIT(INT_HWI6 - GINTC_VIP_DELTA) +#define CPU_IP7 BIT(INT_HWI7 - GINTC_VIP_DELTA) +#define KVM_GINTC_IRQ_MASK (CPU_IP0 | CPU_IP1 | CPU_IP2 | CPU_IP3 \ + | CPU_IP4 | CPU_IP5 | CPU_IP6 | CPU_IP7) =20 #define MNSEC_PER_SEC (NSEC_PER_SEC >> 20) =20 --=20 2.39.3 From nobody Sat Jun 13 03:31:15 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C38342EC0A1; Mon, 11 May 2026 06:51:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482322; cv=none; b=VQ7w11S6YwlVoHbi5B8CjCw6vkPrOMmrIYPm/St4QShqP/Agv1xCEM7XdxJChQnBcReQgJhFwVu/7url8fO+svxCv5PRLVAN/7RLqa71bKLTXT76G4UTgQrHn6WBFmYURBM/HjruZICD4fFQAnOEWfWma/8lVqTQh+ICAQxn81A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482322; c=relaxed/simple; bh=OEhVC3HTdlFrE1Ut6EHZaB9hLmN9TaXIQyV4fSmq+U4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jULigVu40Kf2aCoHcKniODxHpM3+wyKkDz+BAcmRWrbX0UZktFkZ1J3qKsN9YdBAs3M/y2Kpt0o6hVicUv6xISdGM7sI5Vs2XlNjKRJBdwC0hZUzLOXAK9Nkpp32bsh75qFj0TNqHagwT0pBAZHUlblGMkS0MuiyKBsyTKubtgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx+HiOfAFq74wIAA--.2040S3; Mon, 11 May 2026 14:51:58 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAx28GEfAFqAOh+AA--.42931S5; Mon, 11 May 2026 14:51:58 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] LoongArch: KVM: Clear interrupt with batch mode Date: Mon, 11 May 2026 14:51:44 +0800 Message-Id: <20260511065146.680650-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260511065146.680650-1-maobibo@loongson.cn> References: <20260511065146.680650-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAx28GEfAFqAOh+AA--.42931S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With bitmask method, interrupt can be clear with batch mode, rather than one by one. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 37 ++++++++++++---------------------- 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 48dd56aa4dc5..a3f6e5f75dfb 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -62,21 +62,13 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) return 1; } =20 -static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_clear); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -84,27 +76,24 @@ static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigne= d int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - clear_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + clear_csr_gintc(irq); } =20 void kvm_deliver_intr(struct kvm_vcpu *vcpu) { unsigned int priority; unsigned long *pending =3D &vcpu->arch.irq_pending; - unsigned long *pending_clr =3D &vcpu->arch.irq_clear; + unsigned long mask; =20 - for_each_set_bit(priority, pending_clr, EXCCODE_INT_NUM) - kvm_irq_clear(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + kvm_irq_clear(vcpu, mask); + } =20 for_each_set_bit(priority, pending, EXCCODE_INT_NUM) kvm_irq_deliver(vcpu, priority); --=20 2.39.3 From nobody Sat Jun 13 03:31:15 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 63414302149; Mon, 11 May 2026 06:52:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482324; cv=none; b=nk63A2/5Mrtidf3VyYYi75uqpdLsHP/oMjUOz76QOUCZor+fysq1fYKU+FvNGDPkMVZ58Upq9ky4cM4mKhKTUcBAQLSJEDB/CdcKWiNurbrH1/DLAyKhgzbyc37dby+U076G5sUxYVnvYahzes5RgWEd74DGKaJ8YZ6TwuGYxn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482324; c=relaxed/simple; bh=Rm2/WHlYQCxLU+XwtLydiVNkDktoFkH3+mkPNJFowYQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TMjED3QEDfhnI8AvFvsFfl1TajaKBDSel9HvTMosy/09y4nGJSR+gNV/KeGIU2Sl4b/N0iui/ph76lX5OSQL/xSVxsZERNrBYALOFE1KGlkBpGlS7MLigmvoaDBCmO7+oTEhIc5ryaoaWcDEowUU7SZED2D3fRqY4nAks6vfIeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxZniQfAFq84wIAA--.2007S3; Mon, 11 May 2026 14:52:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxHMKQfAFqB+h+AA--.43621S2; Mon, 11 May 2026 14:52:00 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] LoongArch: KVM: Deliver interrupt with batch method Date: Mon, 11 May 2026 14:51:45 +0800 Message-Id: <20260511065146.680650-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260511065146.680650-1-maobibo@loongson.cn> References: <20260511065146.680650-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxHMKQfAFqB+h+AA--.43621S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With bitmask method, interrupt can be delivered with batch mode, rather than one by one. Also remove unused array priority_to_irqp[] here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/interrupt.c | 58 +++++++++------------------------- 1 file changed, 15 insertions(+), 43 deletions(-) diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index a3f6e5f75dfb..380aabb3d4d0 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -9,39 +9,16 @@ #include #include =20 -static unsigned int priority_to_irq[EXCCODE_INT_NUM] =3D { - [INT_TI] =3D CPU_TIMER, - [INT_IPI] =3D CPU_IPI, - [INT_SWI0] =3D CPU_SIP0, - [INT_SWI1] =3D CPU_SIP1, - [INT_HWI0] =3D CPU_IP0, - [INT_HWI1] =3D CPU_IP1, - [INT_HWI2] =3D CPU_IP2, - [INT_HWI3] =3D CPU_IP3, - [INT_HWI4] =3D CPU_IP4, - [INT_HWI5] =3D CPU_IP5, - [INT_HWI6] =3D CPU_IP6, - [INT_HWI7] =3D CPU_IP7, - [INT_AVEC] =3D CPU_AVEC, -}; - -static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) +static void kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned long mask) { - unsigned int irq =3D 0; + unsigned long irq; unsigned long old, new; =20 - clear_bit(priority, &vcpu->arch.irq_pending); - if (priority < EXCCODE_INT_NUM) - irq =3D priority_to_irq[priority]; - - switch (priority) { - case INT_AVEC: - dmsintc_inject_irq(vcpu); - fallthrough; - case INT_TI: - case INT_IPI: - case INT_SWI0: - case INT_SWI1: + irq =3D mask & KVM_ESTAT_IRQ_MASK; + if (irq) { + if (irq & CPU_AVEC) + dmsintc_inject_irq(vcpu); + old =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); new =3D kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); @@ -49,17 +26,11 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsig= ned int priority) /* Inject TI if TVAL inverted */ if (new > old) set_gcsr_estat(CPU_TIMER); - break; - - case INT_HWI0 ... INT_HWI7: - set_csr_gintc(irq); - break; - - default: - break; } =20 - return 1; + irq =3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + if (irq) + set_csr_gintc(irq); } =20 static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned long mask) @@ -85,8 +56,6 @@ static void kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned= long mask) =20 void kvm_deliver_intr(struct kvm_vcpu *vcpu) { - unsigned int priority; - unsigned long *pending =3D &vcpu->arch.irq_pending; unsigned long mask; =20 mask =3D READ_ONCE(vcpu->arch.irq_clear); @@ -95,8 +64,11 @@ void kvm_deliver_intr(struct kvm_vcpu *vcpu) kvm_irq_clear(vcpu, mask); } =20 - for_each_set_bit(priority, pending, EXCCODE_INT_NUM) - kvm_irq_deliver(vcpu, priority); + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + kvm_irq_deliver(vcpu, mask); + } } =20 int kvm_pending_timer(struct kvm_vcpu *vcpu) --=20 2.39.3 From nobody Sat Jun 13 03:31:15 2026 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B8E6364E84; Mon, 11 May 2026 06:52:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482325; cv=none; b=JlCnxLBku134yOJtF7aZQjlIfVAqcv5QGGQkKyAY/XFXrLCWZaWJzmj8BWHEpIM2J3fA4N6bEN5vN3FlPtQl3jO0K+uXl+qDCaoh7FVyj+XSsJFQ007uRO3WqhB6j+UzYjae6IAiFKR5xbdsZ2lL6iX0JXcQLivha8L55S5PzHk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778482325; c=relaxed/simple; bh=yySU/2VefMU+3RTLM6qWKdRgl0f7r5AnAooo3KhZsh4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RxP4Fe26WejIaN1WKpJ5QUvmCSZh6nd/Mec47CQ1QTzlvYcI7UI1Q9JK/BDGlHCJDAogG6ETwZrve8UE2fUcumwNPjA4TuvzuEaJr9xstN7vjgCdDVDNZknf1uTjz+0VlqdXxX3P0OWm9t/9Zpk50q/jFuGMY5/NLhorV3etXNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx3emRfAFq9owIAA--.26288S3; Mon, 11 May 2026 14:52:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxHMKQfAFqB+h+AA--.43621S3; Mon, 11 May 2026 14:52:00 +0800 (CST) From: Bibo Mao To: Huacai Chen Cc: kernel@xen0n.name, kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] LoongArch: KVM: Simple interrupt status acquire interface Date: Mon, 11 May 2026 14:51:46 +0800 Message-Id: <20260511065146.680650-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260511065146.680650-1-maobibo@loongson.cn> References: <20260511065146.680650-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxHMKQfAFqB+h+AA--.43621S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" When VM is migrating, interrupts status are stored in software CSR estat register, also new injected interrupts are cached in vcpu::arch::irq_pending. With interrupt statuc acquire interface, there is expensive vcpu_load() and vcpu_put() function call to sync cached vcpu::arch::irq_pending. Here new internal API kvm_vcpu_sync_intr() is added to sync cached pending irq to software CSR estat register. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_vcpu.h | 1 + arch/loongarch/kvm/interrupt.c | 42 +++++++++++++++++++++++++++ arch/loongarch/kvm/vcpu.c | 22 +++++++------- 3 files changed, 54 insertions(+), 11 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_vcpu.h b/arch/loongarch/include= /asm/kvm_vcpu.h index e504c3822e6f..a6e8bdf631ae 100644 --- a/arch/loongarch/include/asm/kvm_vcpu.h +++ b/arch/loongarch/include/asm/kvm_vcpu.h @@ -54,6 +54,7 @@ int kvm_emu_idle(struct kvm_vcpu *vcpu); int kvm_pending_timer(struct kvm_vcpu *vcpu); int kvm_handle_fault(struct kvm_vcpu *vcpu, int fault); void kvm_deliver_intr(struct kvm_vcpu *vcpu); +void kvm_vcpu_sync_intr(struct kvm_vcpu *vcpu); void kvm_deliver_exception(struct kvm_vcpu *vcpu); =20 void kvm_own_fpu(struct kvm_vcpu *vcpu); diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 380aabb3d4d0..24925c238a65 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -71,6 +71,48 @@ void kvm_deliver_intr(struct kvm_vcpu *vcpu) } } =20 +void kvm_vcpu_sync_intr(struct kvm_vcpu *vcpu) +{ + struct loongarch_csrs *csr =3D vcpu->arch.csr; + unsigned long mask, val; + + if (!csr) + return; + + mask =3D READ_ONCE(vcpu->arch.irq_clear); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_clear, 0); + + /* + * sync cached irq_clear to sw state + * + * When VM is migrated to other physical machines or + * snapshot is created, cached irq pending state should + * be synced + */ + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT); + val &=3D ~(mask & KVM_ESTAT_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, val); + + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC); + val &=3D ~((mask >> 2) & KVM_GINTC_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, val); + } + + mask =3D READ_ONCE(vcpu->arch.irq_pending); + if (mask) { + mask =3D xchg_relaxed(&vcpu->arch.irq_pending, 0); + /* sync cached irq_pending to sw state */ + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT); + val |=3D (mask & KVM_ESTAT_IRQ_MASK); + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, val); + + val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC); + val |=3D (mask >> 2) & KVM_GINTC_IRQ_MASK; + kvm_write_sw_gcsr(csr, LOONGARCH_CSR_GINTC, val); + } +} + int kvm_pending_timer(struct kvm_vcpu *vcpu) { return test_bit(INT_TI, &vcpu->arch.irq_pending); diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index e28084c49e68..2c8bda939dc9 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -610,18 +610,11 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigne= d int id, u64 *val) =20 if (id =3D=3D LOONGARCH_CSR_ESTAT) { preempt_disable(); - vcpu_load(vcpu); - /* - * Sync pending interrupts into ESTAT so that interrupt - * remains during VM migration stage - */ - kvm_deliver_intr(vcpu); - vcpu->arch.aux_inuse &=3D ~KVM_LARCH_SWCSR_LATEST; - vcpu_put(vcpu); + kvm_vcpu_sync_intr(vcpu); preempt_enable(); =20 /* ESTAT IP0~IP7 get from GINTC */ - gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; + gintc =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & KVM_GINTC_IRQ_MAS= K; *val =3D kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2); return 0; } @@ -1635,6 +1628,15 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int= cpu) =20 /* Restore timer state regardless */ kvm_restore_timer(vcpu); + + /* + * Restore Root.GINTC from unused Guest.GINTC register + * + * SW state about LOONGARCH_CSR_GINTC is updated with get_csr() + * ioctl command only and without set_csr(). Update HW state + * from changed SW state. + */ + write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); =20 /* Don't bother restoring registers multiple times unless necessary */ @@ -1697,8 +1699,6 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int = cpu) kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR3); } =20 - /* Restore Root.GINTC from unused Guest.GINTC register */ - write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); write_csr_gstat(csr->csrs[LOONGARCH_CSR_GSTAT]); =20 /* --=20 2.39.3