From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D0237A4AF; Mon, 11 May 2026 06:00:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479249; cv=none; b=OCFTKAzNFgFWJa9QbXUsKWdrBmcLCnH5SmutylAWhr184UMk4UWvnUM9pQkOjg2XD17r+HeOaR1eXy8U2Q6398elGYk1UvdDZaSmKwjjmYWI68h/jsmO+BWH9iwwLF/yMo/hLbfBcW+9mKvRro5G6xVIp6+44yfldyxI5luxat0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479249; c=relaxed/simple; bh=cS0gPoIZztMU6uUA/maOjPHae7NRcrAb51ohsfYsz6A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Am04Urt02MZxZE3DfGYKXDynO+jl30a3hhP+cjL+MEOQFM3W7LqwuOiiyVTE3JKTOwYPSSB5j7+PtyboyeLn+1DsnAAC5fCrvaQdMq+NsB8ovVSLiIEXIBlgADYObk2yTB4w6D2J+QZ4HgRZMaUcy3EX+OniYMQEnhkNRbWFCfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=AOGpWrBk; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="AOGpWrBk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=cf tsOZtxX29kXCinzIdqB457AE+U27lG7aeLpYLPKCg=; b=AOGpWrBklUKzXiHe2e RmH+uBtaO+tn+gDtsITdEf3uD00xsvLlIzYTWEKKYgjPmqae3s74XytRXwTM7MSm GfmPj4SYpIVWELdmhCsmrNnyG2z6I35CmztiTlg6+1AB2Ogdr9s4kQ9Lec2m4NBb lU+4ubeQT0WG3InU0r7WRV538= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S3; Mon, 11 May 2026 13:59:27 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 1/7] PCI: Add pci_host_common_link_train_delay() helper Date: Mon, 11 May 2026 13:59:17 +0800 Message-Id: <20260511055923.37117-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cr15uw48KryxGryDtF4fZrb_yoW8CFyrpa 98AF13CF40grW3uwsxAa4DWryYq3Z5t3yUK397G3sayr9rtrsavFWv93yIqF1rJFZ8Zr17 A3W5K3Z7Cr4xtF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piGNtfUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwAHqmoBcEDaRwAA3o Content-Type: text/plain; charset="utf-8" PCIe r6.0, sec 6.6.1 (Conventional Reset) requires that for a Downstream Port supporting Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending any Configuration Request. Introduce a static inline helper pci_host_common_link_train_delay() that checks the given max_link_speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s, etc.) and calls msleep(100) only when the speed is greater than 5.0 GT/s. This allows multiple host controller drivers to share the same mandatory delay without duplicating the logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pci-host-common.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h index b5075d4bd7eb..d709f7e3e11a 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -10,6 +10,9 @@ #ifndef _PCI_HOST_COMMON_H #define _PCI_HOST_COMMON_H =20 +#include +#include "../pci.h" + struct pci_ecam_ops; =20 int pci_host_common_probe(struct platform_device *pdev); @@ -20,4 +23,18 @@ void pci_host_common_remove(struct platform_device *pdev= ); =20 struct pci_config_window *pci_host_common_ecam_create(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops); + +/** + * pci_host_common_link_train_delay - Wait 100 ms if link speed > 5 GT/s + * @max_link_speed: the maximum link speed (2 =3D 5.0 GT/s, 3 =3D 8.0 GT/s= , ...) + * + * Must be called after Link training completes and before the first + * Configuration Request is sent. + */ +static inline void pci_host_common_link_train_delay(int max_link_speed) +{ + if (max_link_speed > 2) + msleep(PCIE_RESET_CONFIG_WAIT_MS); +} + #endif --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CFB352C52; Mon, 11 May 2026 06:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479294; cv=none; b=N4mulzOMWf2CkdUrP4PsicBClaS7VMJi/7f5l/GztPCw1ds3440/fT6FQa2x9xDtIP41kckv30n2+7YxFBYHr2tuxSTUGcyZvtV6pEE/kwAIBRL73+E1PqSCyn9Gplb8f/ggjoPm1GOMD5ETa9dPWgbKHJ6rCxlMfBWN3GBRCoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479294; c=relaxed/simple; bh=cq4KgLVqEhYBzdkePUxJNjSZCRk4Zbg0Y37IIyZo1ck=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ellif+Bkh0qcO4FUdNG+v9i9sq+APlQT7yhpo1aEQGS0p4vI0anH8S+Q3to6zqKKvWgXK0D7DtHFTx1cETsVjfC1XUJe1j6Cv2mYYvBDbKdojgmiK74U0+UCOEnXSSBq4MIGkIe5nPJeDH6ZMX50Z3vr32vyPTRAJHkQoIfgeho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=bck2fIe7; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="bck2fIe7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=5H RDmkwuTXDuZJGei1txWEOw2r+VmFfM3ynY2WMvNBA=; b=bck2fIe7amFprUHlmJ q1lGetsNo57cHCFA11BNEFian56I50SssO6cZazn1m+FY3AxXp5FpPUZPKo4m3f9 nneF77wm8WcUINOTc8MNVq2vUhCU6n5OeH6s2ZLNG45VSDhMKhFg5I3zy+sbV05d Ni1P/3O/qAzASguJu/QD9f3l8= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S4; Mon, 11 May 2026 13:59:28 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 2/7] PCI: cadence: Add post-link delay for LGA and j721e glue driver Date: Mon, 11 May 2026 13:59:18 +0800 Message-Id: <20260511055923.37117-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxGFWUWFyktFy3trW5Ar4fXwb_yoWrCF43pa y7GFyfG3WIqFWY9a1kZ3WUXryaqFn8A3srJ3929w1xWF17Cr98JF42gF1fJFZxKrZrAr17 ZF1DtF9rGr1ayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEVyIbUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAEHqmoBcEHmwgAA3W Content-Type: text/plain; charset="utf-8" The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1. Add a 'max_link_speed' field to struct cdns_pcie. In the common host layer function cdns_pcie_host_start_link(), after the link has been successfully established, call pci_host_common_link_train_delay() to insert the required delay. For the j721e glue driver, set cdns_pcie.max_link_speed from the existing link speed logic. For other LGA-based glue drivers (sky1, sg2042), the common LGA host setup (pcie-cadence-host.c) provides a fallback reading of the device tree property "max-link-speed" when available. This ensures that the delay is not missed on those platforms once they enable the property. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-j721e.c | 1 + drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence.h | 2 ++ 4 files changed, 11 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index bfdfe98d5aba..ee85b8e04f5b 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie = *pcie, (pcie_get_link_speed(link_speed) =3D=3D PCI_SPEED_UNKNOWN)) link_speed =3D 2; =20 + pcie->cdns_pcie.max_link_speed =3D link_speed; val =3D link_speed - 1; ret =3D regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 2b0211870f02..18e4b6c760b5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -14,6 +14,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../pci-host-common.h" =20 #define LINK_RETRAIN_TIMEOUT HZ =20 @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, if (!ret && rc->quirk_retrain_flag) ret =3D cdns_pcie_retrain(pcie, pcie_link_up); =20 + if (!ret) + pci_host_common_link_train_delay(pcie->max_link_speed); + return ret; } EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 0bc9e6e90e0e..058e4e619654 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -13,6 +13,7 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../../pci.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -397,6 +398,9 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) rc->device_id =3D 0xffff; of_property_read_u32(np, "device-id", &rc->device_id); =20 + if (pcie->max_link_speed < 1) + pcie->max_link_speed =3D of_pci_get_max_link_speed(np); + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); if (IS_ERR(pcie->reg_base)) { dev_err(dev, "missing \"reg\"\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 574e9cf4d003..042a4c49bb9a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data { * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + * @max_link_speed: Maximum supported link speed */ struct cdns_pcie { void __iomem *reg_base; @@ -98,6 +99,7 @@ struct cdns_pcie { struct device_link **link; const struct cdns_pcie_ops *ops; const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + int max_link_speed; }; =20 /** --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD67311963; Mon, 11 May 2026 06:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479293; cv=none; b=fI3ecNeSd3HdrCwok/MNmgAU08KhzybiQ6H8qTfzhhBbm7LhaCH3KyfIYH7cpzrYA4XyqcdoSwSEe+byZQKgF86JR2fMRKa27nf/NKPk5OfgszI4+9DP0vHHPZp1NLW0dSqlg81H/cbzV0hISEDS6I9mN+OSDNRFEpetxBZbc9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479293; c=relaxed/simple; bh=sCG/6nz+kCl6xv1OnkuX5tl+ax34MkmU6lYopVED1Yw=; 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(unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S5; Mon, 11 May 2026 13:59:29 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 3/7] PCI: cadence: HPA: Add post-link delay Date: Mon, 11 May 2026 13:59:19 +0800 Message-Id: <20260511055923.37117-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZF1xur48Kr4kAr43WF4Uurg_yoW8tFyxpa 4DWFyfKF18Xr4Y9an3Aa45XryaqFn8A3y7t3yv9w1xZrnrCr4DtFnFgF1xWa43KFZrAr17 J3ZrtF9rGr15ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziBT5dUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwIHqmoBcELaegAA3V Content-Type: text/plain; charset="utf-8" The Cadence HPA (High Performance Architecture IP) specific link setup function cdns_pcie_hpa_host_link_setup() waits for the link to come up but does not implement the required 100 ms delay after link training completes for speeds > 5.0 GT/s (PCIe r6.0 sec 6.6.1). Add a call to pci_host_common_link_train_delay() immediately after the link is confirmed to be up, using the max_link_speed field. Also, in the HPA host setup function, read the device tree property "max-link-speed" to initialize max_link_speed if not already set by a glue driver. This ensures compliance for HPA-based platforms. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pcie-cadence-host-hpa.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c index 0f540bed58e8..8ef58ed01daa 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -15,6 +15,8 @@ =20 #include "pcie-cadence.h" #include "pcie-cadence-host-common.h" +#include "../pci-host-common.h" +#include "../../pci.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x3F, @@ -304,6 +306,8 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *= rc) ret =3D cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); if (ret) dev_dbg(dev, "PCIe link never came up\n"); + else + pci_host_common_link_train_delay(pcie->max_link_speed); =20 return ret; } @@ -313,6 +317,7 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) { struct device *dev =3D rc->pcie.dev; struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; struct pci_host_bridge *bridge; enum cdns_pcie_rp_bar bar; struct cdns_pcie *pcie; @@ -343,6 +348,9 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) rc->cfg_res =3D res; } =20 + if (pcie->max_link_speed < 1) + pcie->max_link_speed =3D of_pci_get_max_link_speed(np); + /* Put EROM Bar aperture to 0 */ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); =20 --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF4591E1DFC; Mon, 11 May 2026 06:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479315; cv=none; b=Ts+45kXGa8AENmXUX/7qWvInI6TMaW9Wkbhd4Y5TD+MzB4r4+puHJ4l1yzwvs52k3iVPe3n+tU0sFhLRUa2WFshwsACc8KZFqQMnmKJlQUJQUq+49D7ERVFwuddCqCwGm7O0/qrTZd39X7Uo0o4Fd6NOM0oZKA7Fm7TPwVPyfC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479315; c=relaxed/simple; bh=JGnORuPyUIrGJJCc8Wen2ejXoaRNQOlKuGiR3Bu1uRE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TXAsIRiPhBvr2MczUDvdWI0RTrS7u81jErJn9/S4PbA6ZXPU1viZIR4vbdkl/t0Y7GKCIHRHw2c3Nyw/X6YSnF/8m+289BwcnH94omkvEeA38WbEZruIrzKliZzNX4pk1YdfNwowByisrlKJ6W6JIv7lfTVJopkLqlwdg9AE7xc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=C/CkCLCW; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="C/CkCLCW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=gp Th2sXANIfpdVqv2Gr/e9DfeCO6TQqHfjZ6e0H2hT0=; b=C/CkCLCW9LZ+dw6HvA f+1uZgkftp911eDNvIcvsyxg2Hu9tQRKRfw8uN8BaErFVGXtnwHczQ7TO3wETDpZ qzCTfEuQhqnTGQb/Pbz9/A7xN85k6wjC50GfbJpCLYPUadx0SCxhWHldNRulZF9O cVzvb04Ushvf/0d6q6t5vFTk8= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S6; Mon, 11 May 2026 13:59:30 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 4/7] PCI: dwc: Use common pci_host_common_link_train_delay() helper Date: Mon, 11 May 2026 13:59:20 +0800 Message-Id: <20260511055923.37117-5-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7tw1rAFW5Cry3Wr45ArWxXrb_yoW8Xw15pa 98AFyFyFWrJF43uanrCasxZry5X3Z8Cay7GFZaga4fZ347ArZFqw10g34SqFyxJrZFvr1a 9r17tFnrGw4xAF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piQVy7UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAMHqmoBcEPnAAAA3V Content-Type: text/plain; charset="utf-8" The DWC driver already implements the 100 ms delay required by PCIe r6.0 sec 6.6.1 by checking pci->max_link_speed and calling msleep(100). Replace the open-coded msleep() with the new common helper pci_host_common_link_train_delay() to reduce code duplication and improve maintainability. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c11cf61b8319..7021d21bb601 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -22,6 +22,7 @@ #include #include =20 +#include "../pci-host-common.h" #include "../../pci.h" #include "pcie-designware.h" =20 @@ -799,13 +800,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) return -ETIMEDOUT; } =20 - /* - * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link - * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms - * after Link training completes before sending a Configuration Request. - */ - if (pci->max_link_speed > 2) - msleep(PCIE_RESET_CONFIG_WAIT_MS); + pci_host_common_link_train_delay(pci->max_link_speed); =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85637352C52; Mon, 11 May 2026 06:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479312; cv=none; b=aLfp5d3Ch4vUg/Wa94hwhsr9F01BIEjJ8aTXNlLnLjxt2FNmLclHIpULj7yy0VkJ03GkyU4esR6/ot6tP+ZN5wxlQ0ZYoDYElS6/rT+r2DT8TsEEVhIoXm0xCfOwlJ1d6GbZFuWPHdYtOUM5gs5w6YTYKKEaz2TbHP7faqKPweo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479312; c=relaxed/simple; bh=uGFlkESZeslg6/xCj0O+7hMaNsZM715EOfZvtiNdq9A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a9eStA47p6ttUMyDdIasg5Gi5JH141etXRc9EZfd4CLH3prPpiokZNdQQIzKzAjeO3av+nPtWpfAiZObkpd/DPBr5R5dw8xbCgZw+XLT8QFWMjmO6W7egMU1TCalwz4QNYwi7X78AmWiHTba2Kf+z4IxDuMNqqmIH1hcYfGl4Ow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=n9yyHcx3; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="n9yyHcx3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=1e cGNcMfeL57lqoMV/cq9YpZtyuaLsHgkfsd6N4p2xk=; b=n9yyHcx3ovhtpJtiFB NVilXX1R5JxVhSuWXygYOH1bVLWQ40P+/vTynDrH18LkYEjRqEGXDCzwdhp2Ty15 QZJiT4t+MSNNVKaHBsf7ngVKrNUMVNFpt0uUt0x9tVNjxXAdmZ3CrxAXTsum5/gZ kmXqXY7peM6eIIvi7WeXUwaNk= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S7; Mon, 11 May 2026 13:59:32 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 5/7] PCI: aardvark: Add 100 ms delay after link training Date: Mon, 11 May 2026 13:59:21 +0800 Message-Id: <20260511055923.37117-6-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFWfGF4fJw1UXryftF1fZwb_yoW8GFWrpa y3Cr9rtrs5tr43ua17Aa4fWFy3Wan0ka47Jr92gw13ZFnrKryUJr1jk3sagF17AFWvvr13 Ca45t3Z3Gr43Xa7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zErb1nUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAQIq2oBcETnHQAA3G Content-Type: text/plain; charset="utf-8" The Aardvark PCIe controller driver waits for the link to come up but does not implement the mandatory 100 ms delay after link training completes for speeds greater than 5.0 GT/s (PCIe r6.0 sec 6.6.1). The driver already maintains a 'link_gen' field that holds the negotiated link speed. Use it together with pci_host_common_link_train_delay() to insert the required delay immediately after confirming that the link is up. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pci-aardvark.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index e34bea1ff0ac..fd9c7d53e8a7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -26,6 +26,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" #include "../pci-bridge-emul.h" =20 @@ -350,8 +351,10 @@ static int advk_pcie_wait_for_link(struct advk_pcie *p= cie) =20 /* check if the link is up or not */ for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (advk_pcie_link_up(pcie)) + if (advk_pcie_link_up(pcie)) { + pci_host_common_link_train_delay(pcie->link_gen); return 0; + } =20 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); } --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51E7437CD32; Mon, 11 May 2026 06:00:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479244; cv=none; b=dJYXL1y6Ej+/3qXeO0I9cQi0oD+bkNHKoSVDXa4lmJyQ6k/N/LVfdIKiXakibTpFmx2rdRa219SNI4pCTPT+GPq4rr1jhu6plRHrhXOh9yhGBmvLg1I/s1SzI9k8lymrQ1EspkO32/T386SjsvAOYgV5vFT08UGhUHIxOQWJzSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479244; c=relaxed/simple; bh=vsOIjRenkm3Ua3PGEVq5zLtIJuo8T6YnUo3IuCxYFyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=e9RRIkwEB/sGYnvyQ4mDGmJsV3ov+HCAZUtxr2QrjO2oMKUUY3WyyIHv6F0dNMckCwUnviBDho7i2vqDLCDPLha4kS4tRxQmmZs8Wa8KjOCbg8ZcGncYUnSrFAnfwdh9+0NLbG0L7KEK3BJoyjpF1zcrqcYWwG8j34w1nne5X+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=He7KE0CX; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="He7KE0CX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=hv /1t/xGsQygAr/vopI1Yy4bj8nhzgu3manFIYqiKFY=; b=He7KE0CXg8bR10NsVH pcJV9X76hZYnFm/9lfgZrZ5UIaZhx2VpNgb/D3HxSRwOzoTvHiEFOSQ5/Uliw50z /JGdpUgP+ryZyY+LkzknGzUbyh+tQZFM+1QFuLCHO2l5b3ZvqF8pORJ7yZBwBF2k I0QId1gYDu34JLI+Wl1JfrA2E= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S8; Mon, 11 May 2026 13:59:33 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 6/7] PCI: mediatek-gen3: Add 100 ms delay after link up Date: Mon, 11 May 2026 13:59:22 +0800 Message-Id: <20260511055923.37117-7-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S8 X-Coremail-Antispam: 1Uf129KBjvdXoW7Jr4kWw4fAw18WF4rJF1kZrb_yoWkKrcE9a yxZFWfZayjkrySkFnayFyrZr9Yy3s7Wr10qF4fKF13Aa48urn0qrZavryDAF4kGw43tF12 yryqk3W8WFykCjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRAJ5r3UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wUIq2oBcEXJTQAA3X Content-Type: text/plain; charset="utf-8" The MediaTek Gen3 PCIe host driver lacks the required 100 ms delay after link training completes for speeds > 5.0 GT/s, as specified in PCIe r6.0 sec 6.6.1. The driver already stores max_link_speed (from the device tree). After mtk_pcie_startup_port() successfully brings up the link, call pci_host_common_link_train_delay() to comply with the specification. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-mediatek-gen3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b0accd828589..5abddec4e9be 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -30,6 +30,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" =20 #define PCIE_BASE_CFG_REG 0x14 @@ -570,6 +571,8 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *= pcie) goto err_power_down_device; } =20 + pci_host_common_link_train_delay(pcie->max_link_speed); + return 0; =20 err_power_down_device: --=20 2.34.1 From nobody Sat Jun 13 03:31:15 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B095C3A1C9; Mon, 11 May 2026 06:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479239; cv=none; b=rG2FANMM9jnp/xHBHi02zu3jPKjkLC7sBXZlAB+fl7NtyyNQkfczkUheKilXeybtUukUDKw8L+y22IXoyJr96CWnLgQFGt6RpP4vZpAqrxoBVEBuRpE2QPESMraYtz+buVYbL8bAUxR+y4Kpk9kP/4LzXRq8zcdhlXac2Y0Kghs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778479239; c=relaxed/simple; bh=qzQqZfZSMNTqD7LsufmnEvBX9ctnkAxDw7tRsRavm7c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gqpF5vWQ00vdKDHX8IunRvT8JbAjuKDla8TeIMsZYl+ZsVcJP66yFwpLjUGrgJYu3M5Kr8eFeVRRndmOYKnu3QdKKbx+MAbl10raNmLkuB8SScwdUE00ewvHr7tcj6Tjw1BWQSGMU6AkhokH3UedwkzHTuGECEqNDP59ZpkARKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=UqaKtZWj; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="UqaKtZWj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ci VEneF3Qh8f1wr1k2uXvgD09Jme9v/azQpnKLjoB8g=; b=UqaKtZWj8XQB5l4ZDY rnoYcIWW1IqDdmCII/fiPzwLnE0mHKerC3nAYqnIFlYz638umzJRVY5fskiIQfld Xo2OqK4Hc6OITT/sfhSGpIa6yetipI+fDwJuPdObPxcOcWO3qkZesPEiERu0C8Mo BhCTkBqUCuawAgKBpJ/6bD2LY= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDn9yk8cAFqPHQVAw--.46705S9; Mon, 11 May 2026 13:59:34 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, pali@kernel.org, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper Date: Mon, 11 May 2026 13:59:23 +0800 Message-Id: <20260511055923.37117-8-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511055923.37117-1-18255117159@163.com> References: <20260511055923.37117-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn9yk8cAFqPHQVAw--.46705S9 X-Coremail-Antispam: 1Uf129KBjvdXoW7JFy7uw17AFWrCFyDAry7KFg_yoWkArg_u3 47CF9rAw45Kr9IkF12v3ySvFyYya4Iqr1jga1rK3W3JayjyFnYywn7ZFs0yr15u3W7J342 vrykCa48Cr93CjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRK0eHPUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwYIq2oBcEba-AAA3d Content-Type: text/plain; charset="utf-8" Replace the unconditional msleep(100) with the common helper pci_host_common_link_train_delay(). The helper only waits when max_link_speed > 2, as required by PCIe r6.0 sec 6.6.1. This avoids unnecessary delay for Gen1/Gen2 links while retaining the mandatory 100 ms for higher speeds. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/pcie-rzg3s-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index d86e7516dcc2..66f687304c1c 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -35,6 +35,7 @@ #include #include =20 +#include "pci-host-common.h" #include "../pci.h" =20 /* AXI registers */ @@ -1663,7 +1664,7 @@ rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, if (ret) dev_info(dev, "Failed to set max link speed\n"); =20 - msleep(PCIE_RESET_CONFIG_WAIT_MS); + pci_host_common_link_train_delay(host->max_link_speed); =20 return 0; =20 --=20 2.34.1