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Mon, 11 May 2026 06:36:29 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:46 -0400 Subject: [PATCH v2 01/10] riscv: hwprobe.rst: Document EXT_ZICFISS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-1-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 Commit 30c3099036a9 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe") added RISCV_HWPROBE_EXT_ZICFISS as bit 0 of RISCV_HWPROBE_KEY_IMA_EXT_1 but did not add a matching entry to Documentation/arch/riscv/hwprobe.rst. Add it now. Fixes: 30c3099036a9 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in h= wprobe") Signed-off-by: Guodong Xu --- v2: New patch. --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index c420a8349bc68..b1a84ac06da75 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -391,3 +391,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is support= ed, + as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) + extensions specification, ratified 2024-07. --=20 2.43.0 From nobody Sat Jun 13 00:09:33 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 803C53EF679 for ; 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Mon, 11 May 2026 06:36:36 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:36:36 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:47 -0400 Subject: [PATCH v2 02/10] riscv: hwprobe.rst: Replace tabs with spaces Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-2-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 From: Andrew Jones A handful of vendor-extension entries indent continuation lines with a tab character, while the rest of hwprobe.rst uses spaces. Replace those tabs with spaces so the file is consistently space-indented. Cosmetic update, no functional change. Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: No change. --- Documentation/arch/riscv/hwprobe.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index b1a84ac06da75..c3bb26d70c748 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -358,7 +358,7 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector v= endor extension is supported in the T-Head ISA extensions spec starting = from - commit a18c801634 ("Add T-Head VECTOR vendor extension. "). + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). =20 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbom block in bytes. @@ -371,19 +371,19 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod ve= ndor extension is supported in version 1.1 of SiFive Int8 Matrix Multip= lication - Extensions Specification. + Extensions Specification. =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq ve= ndor extension is supported in version 1.1 of SiFive Int8 Matrix Multip= lication - Instruction Extensions Specification. + Instruction Extensions Specification. =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclip= xfqf vendor extension is supported in version 1.0 of SiFive FP32-to-int= 8 Ranged - Clip Instructions Extensions Specification. + Clip Instructions Extensions Specification. =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Ac= cumulate - Instruction Extensions Specification. + Instruction Extensions Specification. =20 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbop block in bytes. --=20 2.43.0 From nobody Sat Jun 13 00:09:33 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 639B63ECBF9 for ; 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Mon, 11 May 2026 06:36:43 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:36:43 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:48 -0400 Subject: [PATCH v2 03/10] riscv: Standardize extension capitalization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-3-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu , Charlie Jenkins X-Mailer: b4 0.15.1 From: Charlie Jenkins The base extensions are often lowercase and were written as lowercase in hwcap, but other references to these extensions in the kernel are uppercase. Standardize the case to make it easier to handle macro expansion. Signed-off-by: Charlie Jenkins [Apply KVM_ISA_EXT_ARR(), fixup all KVM use.] Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu Acked-by: Anup Patel Reviewed-by: Anup Patel --- v2: - Rebased onto v7.1-rc2. - KVM_ISA_EXT_ARR() consolidation moved to its new upstream location (kvm/isa.c); host-side checks now use kvm_riscv_isa_check_host(). --- arch/riscv/include/asm/hwcap.h | 18 +++++++++--------- arch/riscv/include/asm/switch_to.h | 4 ++-- arch/riscv/kernel/cpufeature.c | 32 ++++++++++++++++---------------- arch/riscv/kernel/sys_hwprobe.c | 4 ++-- arch/riscv/kvm/isa.c | 16 ++++++++-------- arch/riscv/kvm/main.c | 2 +- arch/riscv/kvm/vcpu_fp.c | 20 ++++++++++---------- arch/riscv/kvm/vcpu_onereg.c | 6 +++--- arch/riscv/kvm/vcpu_vector.c | 10 +++++----- 9 files changed, 56 insertions(+), 56 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ef8e5f55c8dc..44bf8c7d8acc5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -10,15 +10,15 @@ =20 #include =20 -#define RISCV_ISA_EXT_a ('a' - 'a') -#define RISCV_ISA_EXT_c ('c' - 'a') -#define RISCV_ISA_EXT_d ('d' - 'a') -#define RISCV_ISA_EXT_f ('f' - 'a') -#define RISCV_ISA_EXT_h ('h' - 'a') -#define RISCV_ISA_EXT_i ('i' - 'a') -#define RISCV_ISA_EXT_m ('m' - 'a') -#define RISCV_ISA_EXT_q ('q' - 'a') -#define RISCV_ISA_EXT_v ('v' - 'a') +#define RISCV_ISA_EXT_A ('a' - 'a') +#define RISCV_ISA_EXT_C ('c' - 'a') +#define RISCV_ISA_EXT_D ('d' - 'a') +#define RISCV_ISA_EXT_F ('f' - 'a') +#define RISCV_ISA_EXT_H ('h' - 'a') +#define RISCV_ISA_EXT_I ('i' - 'a') +#define RISCV_ISA_EXT_M ('m' - 'a') +#define RISCV_ISA_EXT_Q ('q' - 'a') +#define RISCV_ISA_EXT_V ('v' - 'a') =20 /* * These macros represent the logical IDs of each multi-letter RISC-V ISA diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920c..ff35a4d04f85a 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -60,8 +60,8 @@ static inline void __switch_to_fpu(struct task_struct *pr= ev, =20 static __always_inline bool has_fpu(void) { - return riscv_has_extension_likely(RISCV_ISA_EXT_f) || - riscv_has_extension_likely(RISCV_ISA_EXT_d); + return riscv_has_extension_likely(RISCV_ISA_EXT_F) || + riscv_has_extension_likely(RISCV_ISA_EXT_D); } #else static __always_inline bool has_fpu(void) { return false; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1734f9a4c2fd7..5cf463570229d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,7 +84,7 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { - if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F)) return 0; =20 return -EPROBE_DEFER; @@ -146,7 +146,7 @@ static int riscv_ext_f_validate(const struct riscv_isa_= ext_data *data, * Due to extension ordering, d is checked before f, so no deferral * is required. */ - if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) { pr_warn_once("This kernel does not support systems with F but not D\n"); return -EINVAL; } @@ -189,7 +189,7 @@ static int riscv_ext_vector_float_validate(const struct= riscv_isa_ext_data *data * Since this function validates vector only, and v/Zve* are probed * after f/d, there's no need for a deferral here. */ - if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) return -EINVAL; =20 return 0; @@ -224,7 +224,7 @@ static int riscv_ext_zcd_validate(const struct riscv_is= a_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && - __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) return 0; =20 return -EPROBE_DEFER; @@ -237,7 +237,7 @@ static int riscv_ext_zcf_validate(const struct riscv_is= a_ext_data *data, return -EINVAL; =20 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && - __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F)) return 0; =20 return -EPROBE_DEFER; @@ -490,15 +490,15 @@ static const unsigned int riscv_c_exts[] =3D { * New entries to this struct should follow the ordering rules described a= bove. */ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { - __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), - __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), - __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts), - __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), - __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), - __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), - __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), - __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_I), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_M), + __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_A, riscv_a_exts), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_F, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q), + __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv= _ext_vector_float_validate), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), @@ -897,8 +897,8 @@ static void __init riscv_fill_hwcap_from_isa_string(uns= igned long *isa2hwcap) * marchid. */ if (acpi_disabled && boot_vendorid =3D=3D THEAD_VENDOR_ID && boot_archid= =3D=3D 0x0) { - this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_v]; - clear_bit(RISCV_ISA_EXT_v, source_isa); + this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_V]; + clear_bit(RISCV_ISA_EXT_V, source_isa); } =20 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 1659d31fd288f..f8f68ba781b45 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -88,10 +88,10 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) pair->value |=3D RISCV_HWPROBE_IMA_FD; =20 - if (riscv_isa_extension_available(NULL, c)) + if (riscv_isa_extension_available(NULL, C)) pair->value |=3D RISCV_HWPROBE_IMA_C; =20 - if (has_vector() && riscv_isa_extension_available(NULL, v)) + if (has_vector() && riscv_isa_extension_available(NULL, V)) pair->value |=3D RISCV_HWPROBE_IMA_V; =20 /* diff --git a/arch/riscv/kvm/isa.c b/arch/riscv/kvm/isa.c index 1132d909cc25c..94077117d1136 100644 --- a/arch/riscv/kvm/isa.c +++ b/arch/riscv/kvm/isa.c @@ -17,14 +17,14 @@ /* Mapping between KVM ISA Extension ID & guest ISA extension ID */ static const unsigned long kvm_isa_ext_arr[] =3D { /* Single letter extensions (alphabetically sorted) */ - [KVM_RISCV_ISA_EXT_A] =3D RISCV_ISA_EXT_a, - [KVM_RISCV_ISA_EXT_C] =3D RISCV_ISA_EXT_c, - [KVM_RISCV_ISA_EXT_D] =3D RISCV_ISA_EXT_d, - [KVM_RISCV_ISA_EXT_F] =3D RISCV_ISA_EXT_f, - [KVM_RISCV_ISA_EXT_H] =3D RISCV_ISA_EXT_h, - [KVM_RISCV_ISA_EXT_I] =3D RISCV_ISA_EXT_i, - [KVM_RISCV_ISA_EXT_M] =3D RISCV_ISA_EXT_m, - [KVM_RISCV_ISA_EXT_V] =3D RISCV_ISA_EXT_v, + KVM_ISA_EXT_ARR(A), + KVM_ISA_EXT_ARR(C), + KVM_ISA_EXT_ARR(D), + KVM_ISA_EXT_ARR(F), + KVM_ISA_EXT_ARR(H), + KVM_ISA_EXT_ARR(I), + KVM_ISA_EXT_ARR(M), + KVM_ISA_EXT_ARR(V), /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SMNPM), KVM_ISA_EXT_ARR(SMSTATEEN), diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index cb8a65273c1f0..70640701310c8 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -85,7 +85,7 @@ static int __init riscv_kvm_init(void) char slist[64]; const char *str; =20 - if (!riscv_isa_extension_available(NULL, h)) { + if (!riscv_isa_extension_available(NULL, H)) { kvm_info("hypervisor extension not available\n"); return -ENODEV; } diff --git a/arch/riscv/kvm/vcpu_fp.c b/arch/riscv/kvm/vcpu_fp.c index 6ad6df26a2fd4..bb11e6757d349 100644 --- a/arch/riscv/kvm/vcpu_fp.c +++ b/arch/riscv/kvm/vcpu_fp.c @@ -21,8 +21,8 @@ void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu) struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; =20 cntx->sstatus &=3D ~SR_FS; - if (riscv_isa_extension_available(vcpu->arch.isa, f) || - riscv_isa_extension_available(vcpu->arch.isa, d)) + if (riscv_isa_extension_available(vcpu->arch.isa, F) || + riscv_isa_extension_available(vcpu->arch.isa, D)) cntx->sstatus |=3D SR_FS_INITIAL; else cntx->sstatus |=3D SR_FS_OFF; @@ -38,9 +38,9 @@ void kvm_riscv_vcpu_guest_fp_save(struct kvm_cpu_context = *cntx, const unsigned long *isa) { if ((cntx->sstatus & SR_FS) =3D=3D SR_FS_DIRTY) { - if (riscv_isa_extension_available(isa, d)) + if (riscv_isa_extension_available(isa, D)) __kvm_riscv_fp_d_save(cntx); - else if (riscv_isa_extension_available(isa, f)) + else if (riscv_isa_extension_available(isa, F)) __kvm_riscv_fp_f_save(cntx); kvm_riscv_vcpu_fp_clean(cntx); } @@ -50,9 +50,9 @@ void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_conte= xt *cntx, const unsigned long *isa) { if ((cntx->sstatus & SR_FS) !=3D SR_FS_OFF) { - if (riscv_isa_extension_available(isa, d)) + if (riscv_isa_extension_available(isa, D)) __kvm_riscv_fp_d_restore(cntx); - else if (riscv_isa_extension_available(isa, f)) + else if (riscv_isa_extension_available(isa, F)) __kvm_riscv_fp_f_restore(cntx); kvm_riscv_vcpu_fp_clean(cntx); } @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, void *reg_val; =20 if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && - riscv_isa_extension_available(vcpu->arch.isa, f)) { + riscv_isa_extension_available(vcpu->arch.isa, F)) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) return -EINVAL; if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) @@ -102,7 +102,7 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, } else return -ENOENT; } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && - riscv_isa_extension_available(vcpu->arch.isa, d)) { + riscv_isa_extension_available(vcpu->arch.isa, D)) { if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) return -EINVAL; @@ -138,7 +138,7 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, void *reg_val; =20 if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && - riscv_isa_extension_available(vcpu->arch.isa, f)) { + riscv_isa_extension_available(vcpu->arch.isa, F)) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) return -EINVAL; if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) @@ -151,7 +151,7 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, } else return -ENOENT; } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && - riscv_isa_extension_available(vcpu->arch.isa, d)) { + riscv_isa_extension_available(vcpu->arch.isa, D)) { if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) return -EINVAL; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index bb920e8923c93..5cc7ddd4aa276 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -770,7 +770,7 @@ static inline unsigned long num_fp_f_regs(const struct = kvm_vcpu *vcpu) { const struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; =20 - if (riscv_isa_extension_available(vcpu->arch.isa, f)) + if (riscv_isa_extension_available(vcpu->arch.isa, F)) return sizeof(cntx->fp.f) / sizeof(u32); else return 0; @@ -799,7 +799,7 @@ static inline unsigned long num_fp_d_regs(const struct = kvm_vcpu *vcpu) { const struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; =20 - if (riscv_isa_extension_available(vcpu->arch.isa, d)) + if (riscv_isa_extension_available(vcpu->arch.isa, D)) return sizeof(cntx->fp.d.f) / sizeof(u64) + 1; else return 0; @@ -878,7 +878,7 @@ static inline unsigned long num_sbi_regs(struct kvm_vcp= u *vcpu) =20 static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) { - if (!riscv_isa_extension_available(vcpu->arch.isa, v)) + if (!riscv_isa_extension_available(vcpu->arch.isa, V)) return 0; =20 /* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */ diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index 62d2fb77bb9b9..f26108a4e601e 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -26,7 +26,7 @@ void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) =20 cntx->vector.vlenb =3D riscv_v_vsize / 32; =20 - if (riscv_isa_extension_available(isa, v)) { + if (riscv_isa_extension_available(isa, V)) { cntx->sstatus |=3D SR_VS_INITIAL; WARN_ON(!cntx->vector.datap); memset(cntx->vector.datap, 0, riscv_v_vsize); @@ -45,7 +45,7 @@ void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_cont= ext *cntx, unsigned long *isa) { if ((cntx->sstatus & SR_VS) =3D=3D SR_VS_DIRTY) { - if (riscv_isa_extension_available(isa, v)) + if (riscv_isa_extension_available(isa, V)) __kvm_riscv_vector_save(cntx); kvm_riscv_vcpu_vector_clean(cntx); } @@ -55,7 +55,7 @@ void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_c= ontext *cntx, unsigned long *isa) { if ((cntx->sstatus & SR_VS) !=3D SR_VS_OFF) { - if (riscv_isa_extension_available(isa, v)) + if (riscv_isa_extension_available(isa, V)) __kvm_riscv_vector_restore(cntx); kvm_riscv_vcpu_vector_clean(cntx); } @@ -154,7 +154,7 @@ int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, void *reg_addr; int rc; =20 - if (!riscv_isa_extension_available(isa, v)) + if (!riscv_isa_extension_available(isa, V)) return -ENOENT; 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Mon, 11 May 2026 06:36:51 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:36:50 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:49 -0400 Subject: [PATCH v2 04/10] riscv: Add Zicclsm to cpufeature and hwprobe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-4-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu , Jesse Taube , Andy Chiu X-Mailer: b4 0.15.1 From: Jesse Taube Zicclsm requires misaligned support for all regular load and store instructions, both scalar and vector, but not AMOs or other specialized forms of memory access, to main memory regions with both the cacheability and coherence PMAs, as defined in the profiles spec. Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance. Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins Signed-off-by: Jesse Taube [Rebased, rewrote doc text, minor commit message revisions] Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: - Rebased onto v7.1-rc2; moved ZICCLSM to IMA_EXT_1 and allocated a new bit for it --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 5 files changed, 8 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index c3bb26d70c748..05f746061f679 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -289,6 +289,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit f88abf1 ("Int= egrating load/store pair for RV32 with the main manual") of the riscv-isa-ma= nual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is support= ed, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar val= ues to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 44bf8c7d8acc5..e8f4a7dd96a93 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -112,6 +112,7 @@ #define RISCV_ISA_EXT_ZCLSD 103 #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 +#define RISCV_ISA_EXT_ZICCLSM 106 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 9139edba0aecb..6819df159c51e 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -116,6 +116,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 1) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5cf463570229d..4b4a8157277a3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -502,6 +502,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_x= linuxenvcfg_exts, riscv_cfilp_validate), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index f8f68ba781b45..9cf62266f1890 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -205,6 +205,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, * in the hart_isa bitmap, are made. */ EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); 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Mon, 11 May 2026 06:36:58 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:36:58 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:50 -0400 Subject: [PATCH v2 05/10] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-5-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 From: Andrew Jones Add Ziccamoa, Ziccif, and Za64rs to riscv_isa_ext[] so they can be parsed from devicetree/ACPI ISA strings. Ziccrse is already present in cpufeature; this patch only adds its hwprobe exposure. Expose all four extensions via hwprobe through new bits in RISCV_HWPROBE_KEY_IMA_EXT_1 (RISCV_HWPROBE_EXT_ZICCAMOA, _ZICCIF, _ZICCRSE, _ZA64RS), so userspace can probe each of these RVA23U64-mandatory extensions individually. Rationale for the validation dependencies added for Ziccamoa and Za64rs: 1) Ziccamoa depends on Zaamo. The RVA23 profile prose was updated post-ratification to spell out the Zaamo reference: commit 2b218613752d in riscv/riscv-profiles ("Improve description of Ziccamoa (#224)") reworded the rva23-profile.adoc (and other profiles that include Ziccamoa) text from "must support all atomics in A" to "must support all atomics in the Zaamo extension" [1]. 2) Za64rs depends on Zalrsc. The unprivileged ISA manual src/zars.adoc, integrated in commit ebe06adc22cd ("Integrate profiles as Volume III (#2771)"), defines Za64rs as: "The Za64rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 64 bytes in size" [2]. Link: https://github.com/riscv/riscv-profiles/commit/2b218613752d63287286b5= ae801b820cbd8cc10c [1] Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zars.a= doc [2] Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: - Rebased to v7.1-rc2. - Reworded subject and expanded commit message. - Validation added for Ziccamoa depending on Zaamo and Za64rs depending on Zalrsc. --- Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ arch/riscv/include/asm/hwcap.h | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 21 +++++++++++++++++++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ 5 files changed, 48 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 05f746061f679..73f50dc1ce7a2 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -399,3 +399,19 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is support= ed, as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) extensions specification, ratified 2024-07. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is suppo= rted, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") + + * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") + + * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is support= ed, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") + + * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e8f4a7dd96a93..0acb7a01ecc0f 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -113,6 +113,9 @@ #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 #define RISCV_ISA_EXT_ZICCLSM 106 +#define RISCV_ISA_EXT_ZICCAMOA 107 +#define RISCV_ISA_EXT_ZICCIF 108 +#define RISCV_ISA_EXT_ZA64RS 109 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 6819df159c51e..58d1e86e47ae7 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -117,6 +117,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) #define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 1) +#define RISCV_HWPROBE_EXT_ZICCAMOA (1ULL << 2) +#define RISCV_HWPROBE_EXT_ZICCIF (1ULL << 3) +#define RISCV_HWPROBE_EXT_ZICCRSE (1ULL << 4) +#define RISCV_HWPROBE_EXT_ZA64RS (1ULL << 5) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 4b4a8157277a3..46ea2cbcf881a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -90,6 +90,24 @@ static int riscv_ext_f_depends(const struct riscv_isa_ex= t_data *data, return -EPROBE_DEFER; } =20 +static int riscv_ext_zaamo_depends(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZAAMO)) + return 0; + + return -EPROBE_DEFER; +} + +static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZALRSC)) + return 0; + + return -EPROBE_DEFER; +} + static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -502,6 +520,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA, riscv_ext= _zaamo_depends), + __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF), __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_x= linuxenvcfg_exts, @@ -516,6 +536,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), + __RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS, riscv_ext_zal= rsc_depends), __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO), __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 9cf62266f1890..b15ac9adf7920 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -206,6 +206,10 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pai= r, */ EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); 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Mon, 11 May 2026 06:37:05 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:37:05 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:51 -0400 Subject: [PATCH v2 06/10] riscv: Add B to hwcap and hwprobe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-6-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 From: Andrew Jones Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs are all set. Also expose B via hwprobe (RISCV_HWPROBE_EXT_B in RISCV_HWPROBE_KEY_IMA_EXT_1) so that userspace can probe B directly, mirroring the F/D/C/V pattern where each is reported via both hwcap and hwprobe. Signed-off-by: Andrew Jones [Add B to hwprobe] Signed-off-by: Guodong Xu --- v2: - Rebased to v7.1-rc2 - Add B to hwprobe (RISCV_HWPROBE_EXT_B at IMA_EXT_1 bit 6) and document it in hwprobe.rst, so userspace can probe B directly. --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/cpufeature.c | 8 ++++++++ arch/riscv/kernel/sys_hwprobe.c | 1 + 6 files changed, 16 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 73f50dc1ce7a2..cb31fd3b12017 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -415,3 +415,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported, as defined in the RISC-V Profiles specification starting from commit b1d80660 ("Updated to ratified state.") + + * :c:macro:`RISCV_HWPROBE_EXT_B`: The B extension is supported, as defin= ed + in version 1.0 of the Bit-Manipulation ISA extensions, and implies = the + presence of the Zba, Zbb, and Zbs sub-extensions. diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0acb7a01ecc0f..58523b3a1998a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -11,6 +11,7 @@ #include =20 #define RISCV_ISA_EXT_A ('a' - 'a') +#define RISCV_ISA_EXT_B ('b' - 'a') #define RISCV_ISA_EXT_C ('c' - 'a') #define RISCV_ISA_EXT_D ('d' - 'a') #define RISCV_ISA_EXT_F ('f' - 'a') diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/= asm/hwcap.h index c52bb7bbbabe9..96b7cf854e090 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,6 +21,7 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_B (1 << ('B' - 'A')) #define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) =20 #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 58d1e86e47ae7..430dc49a82863 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -121,6 +121,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZICCIF (1ULL << 3) #define RISCV_HWPROBE_EXT_ZICCRSE (1ULL << 4) #define RISCV_HWPROBE_EXT_ZA64RS (1ULL << 5) +#define RISCV_HWPROBE_EXT_B (1ULL << 6) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 46ea2cbcf881a..81145621dc378 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -468,6 +468,12 @@ static const unsigned int riscv_c_exts[] =3D { RISCV_ISA_EXT_ZCD, }; =20 +static const unsigned int riscv_b_exts[] =3D { + RISCV_ISA_EXT_ZBA, + RISCV_ISA_EXT_ZBB, + RISCV_ISA_EXT_ZBS, +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -515,6 +521,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts), + __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts), __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv= _ext_vector_float_validate), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), @@ -1135,6 +1142,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f' - 'a'] =3D COMPAT_HWCAP_ISA_F; isa2hwcap['d' - 'a'] =3D COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] =3D COMPAT_HWCAP_ISA_C; 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Mon, 11 May 2026 06:37:13 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:37:13 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:52 -0400 Subject: [PATCH v2 07/10] riscv: Add a getter for user PMLEN support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-7-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 From: Andrew Jones Querying whether a given user PMLEN is supported is needed for RVA23U64 base detection from outside arch/riscv/kernel/process.c. Add riscv_have_user_pmlen() to expose this. Link: https://lore.kernel.org/linux-riscv/rfuwa7a3ebe76udmnwyrssjy7shkkgxnt= vhwzn6oquysj4tuyp@xzvpylcfhz53/ Signed-off-by: Andrew Jones [Guodong: replace exported booleans with getter per Andrew's suggestion] Signed-off-by: Guodong Xu --- v2: Add a getter for user PMLEN. --- arch/riscv/include/asm/processor.h | 4 ++++ arch/riscv/kernel/process.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 812517b2cec13..febf51e127f70 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -214,6 +214,10 @@ long set_tagged_addr_ctrl(struct task_struct *task, un= signed long arg); long get_tagged_addr_ctrl(struct task_struct *task); #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) + +bool riscv_have_user_pmlen(u8 len); +#else +static inline bool riscv_have_user_pmlen(u8 len) { return false; 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Mon, 11 May 2026 06:37:20 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:37:20 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:53 -0400 Subject: [PATCH v2 08/10] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-8-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 Introduce a per-hart and host-wide bitmap of conformant ISA "bases" -- named profile-class sets such as IMA and RVA23U64 -- and compute both at init time. This is the cache that subsequent consumers (hwprobe's RVA23U64 base behavior bit, /proc/cpuinfo's "isa bases" lines, etc.) read without recomputing. riscv_init_isa_bases() iterates over all possible cpus to populate each hart_isa[cpu].isa_bases, then computes the host-wide riscv_isa_bases against the AND-across-harts riscv_isa bitmap. It is registered as a subsys_initcall so it executes after core_initcall(tagged_addr_init), which probes senvcfg.PMM and populates have_user_pmlen_*. Without that ordering, riscv_have_user_pmlen(7) would still return its default false and the RVA23U64 detection path would always bail. The detection itself is encapsulated in riscv_set_isa_bases(), which takes an output bases bitmap and an input ISA bitmap. Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: - Implement riscv_init_isa_bases() that runs at system init time, after tagged_addr_init() populates have_user_pmlen_*. - Split RVA23S64 placeholder into a future patch. --- arch/riscv/include/asm/cpufeature.h | 14 ++++++ arch/riscv/kernel/cpufeature.c | 92 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 106 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 739fcc84bf7b2..facc31b2960c6 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -25,10 +25,24 @@ struct riscv_cpuinfo { unsigned long mimpid; }; =20 +enum { + RISCV_ISA_BASE_IMA, + RISCV_ISA_BASE_RVA23U64, + RISCV_NR_ISA_BASES, +}; + +/** + * struct riscv_isainfo - per-hart ISA state + * @isa: bitmap of ISA extensions this hart implements + * @isa_bases: bitmap of profile bases this hart conforms to + */ struct riscv_isainfo { DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX); + DECLARE_BITMAP(isa_bases, RISCV_NR_ISA_BASES); }; =20 +extern unsigned long riscv_isa_bases[BITS_TO_LONGS(RISCV_NR_ISA_BASES)]; + DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 extern const struct seq_operations cpuinfo_op; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 81145621dc378..6e8dd33aa3888 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -41,6 +41,9 @@ unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; =20 +/* Host ISA bases bitmap */ +DECLARE_BITMAP(riscv_isa_bases, RISCV_NR_ISA_BASES) __read_mostly; + /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 @@ -1305,3 +1308,92 @@ void __init_or_module riscv_cpufeature_patch_func(st= ruct alt_entry *begin, } } #endif + +/* + * Compute the set of profile bases (IMA, RVA23U64, ...) a hart + * conforms to, given its resolved ISA bitmap. + * + * If @isa_bitmap is NULL, the host ISA bitmap (the AND across all harts) = is + * used. + */ +static void riscv_set_isa_bases(unsigned long *bases, const unsigned long = *isa_bitmap) +{ + const unsigned long *isa =3D isa_bitmap ? isa_bitmap : riscv_isa; + DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) =3D { 0 }; + DECLARE_BITMAP(tmp, RISCV_ISA_EXT_MAX); + + /* IMA */ + set_bit(RISCV_ISA_EXT_I, ext_mask); + set_bit(RISCV_ISA_EXT_M, ext_mask); + set_bit(RISCV_ISA_EXT_A, ext_mask); + + if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX)) + return; + + set_bit(RISCV_ISA_BASE_IMA, bases); + + /* RVA23U64 */ + + /* Zic64b and Supm with PMLEN=3D7 */ + if (riscv_cbom_block_size !=3D 64 || + riscv_cbop_block_size !=3D 64 || + riscv_cboz_block_size !=3D 64 || + !riscv_have_user_pmlen(7)) + return; + + set_bit(RISCV_ISA_EXT_F, ext_mask); + set_bit(RISCV_ISA_EXT_D, ext_mask); + set_bit(RISCV_ISA_EXT_C, ext_mask); + set_bit(RISCV_ISA_EXT_B, ext_mask); + set_bit(RISCV_ISA_EXT_ZICSR, ext_mask); + set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask); + set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask); + set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask); + set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask); + set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask); + set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask); + set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask); + set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask); + set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask); + set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask); + set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask); + set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask); + set_bit(RISCV_ISA_EXT_ZKT, ext_mask); + set_bit(RISCV_ISA_EXT_V, ext_mask); + set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask); + set_bit(RISCV_ISA_EXT_ZVBB, ext_mask); + set_bit(RISCV_ISA_EXT_ZVKT, ext_mask); + set_bit(RISCV_ISA_EXT_ZIHINTNTL, ext_mask); + set_bit(RISCV_ISA_EXT_ZICOND, ext_mask); + set_bit(RISCV_ISA_EXT_ZIMOP, ext_mask); + set_bit(RISCV_ISA_EXT_ZCMOP, ext_mask); + set_bit(RISCV_ISA_EXT_ZCB, ext_mask); + set_bit(RISCV_ISA_EXT_ZFA, ext_mask); + set_bit(RISCV_ISA_EXT_ZAWRS, ext_mask); + set_bit(RISCV_ISA_EXT_SUPM, ext_mask); + + if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX)) + return; + + set_bit(RISCV_ISA_BASE_RVA23U64, bases); +} + +/* + * Populate the host ISA bases bitmap (riscv_isa_bases) and each + * hart's per-cpu isa_bases. + */ +static int __init riscv_init_isa_bases(void) +{ + int cpu; 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Mon, 11 May 2026 06:37:26 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:37:26 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:54 -0400 Subject: [PATCH v2 09/10] riscv: cpu: Output isa bases lines in cpuinfo Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-9-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 Output two new lines per processor in /proc/cpuinfo: isa bases : hart isa bases : These read directly from the cached riscv_isa_bases and hart_isa[cpu].isa_bases bitmaps populated at boot by riscv_init_isa_bases(). Example output on qemu booted with -cpu rva23s64,sv39=3Don,pmp=3Don (showing only the new lines plus their neighbors for context): processor : 0 hart : 4 isa bases : rv64ima rva23u64 isa : rv64imafdcbvh_zicbom_zicbop_... mmu : sv39 ... mimpid : 0x0 hart isa bases : rv64ima rva23u64 hart isa : rv64imafdcbvh_zicbom_zicbop_... Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: - Read from the cached riscv_isa_bases and hart_isa[cpu_id].isa_bases bitmaps populated by riscv_init_isa_bases() at init time. --- arch/riscv/kernel/cpu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3dbc8cc557dd1..31e2857dcdcf1 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -305,6 +305,26 @@ static void print_mmu(struct seq_file *f) seq_printf(f, "mmu\t\t: %s\n", sv_type); } =20 +static const char * const riscv_isa_base_names[] =3D { +#ifdef CONFIG_32BIT + [RISCV_ISA_BASE_IMA] =3D "rv32ima", +#else + [RISCV_ISA_BASE_IMA] =3D "rv64ima", +#endif + [RISCV_ISA_BASE_RVA23U64] =3D "rva23u64", +}; + +static void print_isa_bases(struct seq_file *m, const unsigned long *isa_b= ases) +{ + unsigned int i; + + for (i =3D 0; i < RISCV_NR_ISA_BASES; i++) { + if (test_bit(i, isa_bases)) + seq_printf(m, " %s", riscv_isa_base_names[i]); + } + seq_puts(m, "\n"); +} + static void *c_start(struct seq_file *m, loff_t *pos) { if (*pos =3D=3D nr_cpu_ids) @@ -336,6 +356,9 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); =20 + seq_puts(m, "isa bases\t:"); + print_isa_bases(m, riscv_isa_bases); + /* * For historical raisins, the isa: line is limited to the lowest common * denominator of extensions supported across all harts. A true list of @@ -360,6 +383,9 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); =20 + seq_puts(m, "hart isa bases\t:"); + print_isa_bases(m, hart_isa[cpu_id].isa_bases); + /* * Print the ISA extensions specific to this hart, which may show * additional extensions not present across all harts. --=20 2.43.0 From nobody Sat Jun 13 00:09:33 2026 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7E873E6389 for ; Mon, 11 May 2026 13:37:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778506657; cv=none; b=FYzWpEFTfH3UwBT/7miGKSKwaa79jPJY9xpfJJCvKXOfvhFwHpsgDx5usRdox/WAqkv9RCjQcd4spPcEAQGAxbyLwhWBm9b7Pq1n7eCLGScI2j0SkYr56V1IvsqjI4x5qUOg/ihqSdG3TxT1zo9vRGmi2K+ywdFGM3KwW1e+3z0= ARC-Message-Signature: i=1; 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Mon, 11 May 2026 06:37:35 -0700 (PDT) Received: from [127.0.1.1] ([2a12:a305:4::30f3]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367be3daafesm3034326a91.8.2026.05.11.06.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:37:34 -0700 (PDT) From: Guodong Xu Date: Mon, 11 May 2026 21:34:55 -0400 Subject: [PATCH v2 10/10] riscv: hwprobe: Introduce rva23u64 base behavior Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-rva23u64-hwprobe-v2-v2-10-21c5a544f1dc@riscstar.com> References: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> In-Reply-To: <20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Albert Ou , Alexandre Ghiti , Shuah Khan , Anup Patel , Atish Patra , Shuah Khan , Deepak Gupta , Zong Li , Christian Brauner Cc: Andrew Jones , Charlie Jenkins , Samuel Holland , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Guodong Xu X-Mailer: b4 0.15.1 Provide a hwprobe base-behavior bit so userspace can check RVA23U64 support in one call. Without it, a consumer needs five hwprobe calls and four prctl calls, which is error-prone to require of every caller. Most software treats RVA23U64 as a new base anyway, so expose it directly. Signed-off-by: Andrew Jones Signed-off-by: Guodong Xu --- v2: - Detect RVA23U64 by reading from the cached hart_isa[].isa_bases bitmap populated by riscv_init_isa_bases() at init time, sharing one source of truth with /proc/cpuinfo. --- Documentation/arch/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 ++- arch/riscv/kernel/sys_hwprobe.c | 23 +++++++++++++++---= ---- tools/testing/selftests/riscv/hwprobe/which-cpus.c | 2 +- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index cb31fd3b12017..9b901bf8bab9a 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -67,6 +67,14 @@ The following keys are defined: programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). =20 + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64`: Support for all manda= tory + extensions of RVA23U64, as defined in the RISC-V Profiles specification + starting from commit 0273f3c921b6 ("rva23/rvb23 ratified"). + + The RVA23U64 base is based upon the IMA base and therefore IMA extensi= on + keys (e.g. :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`:) may be used to pro= be + optional extensions. + * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 430dc49a82863..d940ba4f6a1e8 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -21,7 +21,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 -#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64 (1 << 1) #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index dcc102bf8f183..c43fcad737b73 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -225,6 +225,17 @@ static bool hwprobe_ext0_has(const struct cpumask *cpu= s, u64 ext) return (pair.value & ext); } =20 +static bool hwprobe_has_isa_base(const struct cpumask *cpus, unsigned int = base) +{ + int cpu; + + for_each_cpu(cpu, cpus) { + if (!test_bit(base, hart_isa[cpu].isa_bases)) + return false; + } + return true; +} + #if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS) static u64 hwprobe_misaligned(const struct cpumask *cpus) { @@ -307,14 +318,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pa= ir, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; - /* - * The kernel already assumes that the base single-letter ISA - * extensions are supported on all harts, and only supports the - * IMA base, so just cheat a bit here and tell that to - * userspace. - */ case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: - pair->value =3D RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + pair->value =3D 0; + if (hwprobe_has_isa_base(cpus, RISCV_ISA_BASE_IMA)) + pair->value |=3D RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + if (hwprobe_has_isa_base(cpus, RISCV_ISA_BASE_RVA23U64)) + pair->value |=3D RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64; break; =20 case RISCV_HWPROBE_KEY_IMA_EXT_0: diff --git a/tools/testing/selftests/riscv/hwprobe/which-cpus.c b/tools/tes= ting/selftests/riscv/hwprobe/which-cpus.c index 587feb198c049..f8c797b1d0fd9 100644 --- a/tools/testing/selftests/riscv/hwprobe/which-cpus.c +++ b/tools/testing/selftests/riscv/hwprobe/which-cpus.c @@ -105,7 +105,7 @@ int main(int argc, char **argv) pairs[0] =3D (struct riscv_hwprobe){ .key =3D RISCV_HWPROBE_KEY_BASE_BEHA= VIOR, }; rc =3D riscv_hwprobe(pairs, 1, 0, NULL, 0); assert(rc =3D=3D 0 && pairs[0].key =3D=3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR= && - pairs[0].value =3D=3D RISCV_HWPROBE_BASE_BEHAVIOR_IMA); + (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)); =20 pairs[0] =3D (struct riscv_hwprobe){ .key =3D RISCV_HWPROBE_KEY_IMA_EXT_0= , }; rc =3D riscv_hwprobe(pairs, 1, 0, NULL, 0); --=20 2.43.0