From nobody Sat Jun 13 03:08:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFB2C3DD506 for ; Mon, 11 May 2026 10:55:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778496900; cv=none; b=BjXYDw545vBa40fJN95TIlTnUAWR2JsJWxAi1SoaCUvOaVJTS751ySB9DXXCQALaFv60RS4NhVjYNPhIkNVOKnavNm9buePKV1hmaQcPbE4noa3PYlIiH1qM7H2x8UugNpZieyhOWR0WdkXkYAgHoYLHmmcmY51kx56WAP5khXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778496900; c=relaxed/simple; bh=7c/fgE9AubmOdd28+ClB5iz7GbkE6njsMZaCswO7czU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=iKHpHdEILKrkpYe9eSVJVqP1qCSEmWbXhG5hRxzrzaRWXB8VdUx00FIKg7AJFRQZuvHZyUtXJOBS/5mHupAwhF6my8Toyh0zLsvdQ4Yo9SsRUBrLQ7yZ8d5ws33rKf+ZKZeGLy/EMzbl/uO/3CTLN0p1p1H4Mg9bZkOdzjbYafg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DrC8At+S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DrC8At+S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 667B6C2BCB0; Mon, 11 May 2026 10:55:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778496900; bh=7c/fgE9AubmOdd28+ClB5iz7GbkE6njsMZaCswO7czU=; h=From:Date:Subject:To:Cc:Reply-To:From; b=DrC8At+ShEuPM6vthAZX4ENzR6IB+3rM4iCl99i+zBQTYDPbwQQ6XZLzZ9GnpHwrN boqhakWJaMmwsrM20oSJnpe7Z7wFSwm87AOzICuO0VKJA6hiK73Lvv5Zm/LP2aTiOq tacSl8vIcvWXISEWfoKZE30HDk4GhyanewUyITHw3FCZmqYVE5XkpYXXrDmDA4iAyM uodPL6NE/O9MdXT9ZwTTe3MS2w7xE7YFS3ZENrhcgSOfgZpL18o2EnVY5pSo+d3GZu H5nKqosfEaXB8EpL1LJJRZzDnl/JM9lmUA+uzKR6EDc9pAldQ7aElg5DmFDCZj7f1U zFaolUs4eHPgA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AA9CD37B9; Mon, 11 May 2026 10:55:00 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Mon, 11 May 2026 12:50:43 +0200 Subject: [PATCH] riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-p8700-wfi-v1-1-099b1d10fcf2@htecgroup.com> X-B4-Tracking: v=1; b=H4sIAIK0AWoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDE0NT3QILcwMD3fK0TF1LAwvjJMMUC/MUIyMloPqCotS0zAqwWdGxtbU AXMx1A1sAAAA= X-Change-ID: 20260415-p8700-wfi-9083b1d87d22 To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Djordje Todorovic , Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778496899; l=6792; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=mYf6QfV2es6fc3DDH6Apg44OtuXdeSmwhrWl6VF62r0=; b=gLIQCoQ+3bp8+MeVcd0BIaOLge9OjPPwuUnf5YZyoqfob79CpIb2Um2SIcgqdmUZ7MJCm7rT4 x/vHrcAxoP2BuzlHabSQvWwd/gO1BZKFqGAmYjnc+9PHFTXfrBUe6Gn X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Djordje Todorovic The MIPS P8700 has bugs with the WFI instruction. This errata uses the RISC-V alternatives framework to patch all WFI instructions with the MIPS P8700 pause opcode (0x00501013) at runtime when running on P8700 hardware. Two call sites are patched: - arch/riscv/kernel/head.S: secondary hart parking loop - arch/riscv/include/asm/processor.h: wait_for_interrupt() Signed-off-by: Djordje Todorovic Signed-off-by: Aleksa Paunovic --- This patch was tested on QEMU configured with eight P8700 harts, as well as on the MIPS Boston board, configured with a single P8700 CPU. Errata application was tested by disassembling with GDB on QEMU and inserting an illegal instruction on the Boston board. Correctness was tested with a combination of kselftests and torture tests (rcu, locktorture), along with coremark testing. --- arch/riscv/Kconfig.errata | 11 +++++++++++ arch/riscv/errata/mips/errata.c | 14 ++++++++++++++ arch/riscv/include/asm/errata_list.h | 27 ++++++++++++++++++++++++= +++ arch/riscv/include/asm/errata_list_vendors.h | 5 +++-- arch/riscv/include/asm/processor.h | 3 ++- arch/riscv/kernel/head.S | 4 +++- 6 files changed, 60 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 3c945d086c7d0266b685f9506d58b0662af071c4..cc75e6f70513d08afeedf650b14= dba83eea84632 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -44,6 +44,17 @@ config ERRATA_MIPS_P8700_PAUSE_OPCODE =20 If you are not using the P8700 processor, say n. =20 +config ERRATA_MIPS_P8700_WFI + bool "Replace WFI with mips.pause for MIPS P8700" + depends on ERRATA_MIPS && 64BIT + default n + help + The RISCV MIPS P8700 has bugs with the WFI instruction. + This errata replaces all WFI instructions with the MIPS + P8700 pause opcode to avoid these issues. + + If you are not using the P8700 processor, say n. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errat= a.c index e984a8152208c34690f89d8101571b097485c360..67b59f8c1708ea8b7a040f7939e= 111b8f30e6a75 100644 --- a/arch/riscv/errata/mips/errata.c +++ b/arch/riscv/errata/mips/errata.c @@ -23,6 +23,17 @@ static inline bool errata_probe_pause(void) return true; } =20 +static inline bool errata_probe_wfi(void) +{ + if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_WFI)) + return false; + + if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) + return false; + + return true; +} + static u32 mips_errata_probe(void) { u32 cpu_req_errata =3D 0; @@ -30,6 +41,9 @@ static u32 mips_errata_probe(void) if (errata_probe_pause()) cpu_req_errata |=3D BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE); =20 + if (errata_probe_wfi()) + cpu_req_errata |=3D BIT(ERRATA_MIPS_P8700_WFI); + return cpu_req_errata; } =20 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 6694b5ccdcf85cfe7e767ea4de981b34f2b17b04..cbe90b19556203e1462cfb345b1= 64c9061887e74 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -25,6 +25,16 @@ ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ CONFIG_ERRATA_SIFIVE_CIP_453) + +#ifdef CONFIG_ERRATA_MIPS_P8700_WFI +#define ALT_WFI \ +ALTERNATIVE("wfi; .rept 7; nop; .endr;", \ + ".rept 8; .insn 0x00501013; .endr;", MIPS_VENDOR_ID, \ + ERRATA_MIPS_P8700_WFI, CONFIG_ERRATA_MIPS_P8700_WFI) +#else +#define ALT_WFI wfi +#endif + #else /* !__ASSEMBLER__ */ =20 #define ALT_SFENCE_VMA_ASID(asid) \ @@ -53,6 +63,23 @@ asm(ALTERNATIVE( \ : /* no inputs */ \ : "memory") =20 +#ifdef CONFIG_ERRATA_MIPS_P8700_WFI +#define ALT_RISCV_WFI() \ +asm volatile(ALTERNATIVE( \ + "wfi\n" /* Original RISC-V wfi insn */ \ + __nops(7), \ + ".rept 8;" MIPS_PAUSE ".endr;\n", /* Replacement: mips.pause for P8700 *= / \ + MIPS_VENDOR_ID, /* Vendor ID to match */ \ + ERRATA_MIPS_P8700_WFI, /* patch_id */ \ + CONFIG_ERRATA_MIPS_P8700_WFI) \ + : /* no outputs */ \ + : /* no inputs */ \ + : "memory") +#else +#define ALT_RISCV_WFI() \ + __asm__ __volatile__ ("wfi") +#endif + /* * _val is marked as "will be overwritten", so need to set it to 0 * in the default case. diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/incl= ude/asm/errata_list_vendors.h index ec7eba3734371a2d8b68fbd4cbd88a8e7135a413..4505317a6b949be602f507547fc= 9cd495c923e32 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -22,8 +22,9 @@ #endif =20 #ifdef CONFIG_ERRATA_MIPS -#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0 -#define ERRATA_MIPS_NUMBER 1 +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0 +#define ERRATA_MIPS_P8700_WFI 1 +#define ERRATA_MIPS_NUMBER 2 #endif =20 #endif /* ASM_ERRATA_LIST_VENDORS_H */ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 4c3dd94d0f63844fecc32a7e2c1a184113ee49d9..ae4faed371c16ba33f31373561d= e03e89d35d04c 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #define arch_get_mmap_end(addr, len, flags) \ ({ \ @@ -176,7 +177,7 @@ extern unsigned long __get_wchan(struct task_struct *p); =20 static inline void wait_for_interrupt(void) { - __asm__ __volatile__ ("wfi"); + ALT_RISCV_WFI(); } =20 extern phys_addr_t dma32_phys_limit; diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 9c99c5ad6fe8a32e24c8ce7e0badd63469d2c387..14935e8eec2639844c45bd37db2= 9db74fee38a22 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "efi-header.S" =20 __HEAD @@ -196,7 +198,7 @@ secondary_start_sbi: * - receive an early trap, before setup_trap_vector finished * - fail in smp_callin(), as a successful one wouldn't return */ - wfi + ALT_WFI j .Lsecondary_park =20 .align 2 --- base-commit: c369299895a591d96745d6492d4888259b004a9e change-id: 20260415-p8700-wfi-9083b1d87d22 Best regards, --=20 Aleksa Paunovic