From nobody Sat Jun 13 04:19:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13DF936BCDA; Mon, 11 May 2026 02:59:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778468374; cv=none; b=ddQg11tzuOTeAweQvCY23uzmhDHhp0B99tGDpq5YkXzppFyWFDNtDc5lkEuoci23PtuU48hTWJJ3Kcsi3kaax3c+kzC8ya+YUZW+JC+JGQJ7r3ogoWuOdPhwpxBLsqjZdGIrfCEjEc6jHJwwnEoKndloHgTNMBg1wZGcYk5oi5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778468374; c=relaxed/simple; bh=UA/S9cLsNrwPIyQx/17ZpDqEZXlb8oCbwx2AeLnP4tA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tlgMomyZxhfjjQAnwscKti6nsSNDIjQcfiqJwCEFiQf5j9fRruWZAzpjrVXZKsbUIqR+B2cvgIBkTQWhewq2/BKVuEyszCPPZhQDLztMUug/SHlWIUcywZDmIl4QN2WXli2pE6G9EH65XIdVMZjpp3ws1QA9itNl3X1N80+mFPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QuhIsEQB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QuhIsEQB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2898BC2BCC7; Mon, 11 May 2026 02:59:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778468373; bh=UA/S9cLsNrwPIyQx/17ZpDqEZXlb8oCbwx2AeLnP4tA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QuhIsEQBhLGMtCcs5+wQCR28fPvTvIkMsUdiTCNUQXfs6wV8K0Y2Y8VtV6QXy/W8g 7k60BcM0DUWWJvDRRFANzg/AjvRsd/xquOZCt7o0jHvxDsesQMntmKk6EXZwntNjk6 H9IFBeoodxyqTYyqZ3K9bU4K0e1RXsBxGVqMW2OjvYDB8gHVzDzEwc+YC39hWSQ5Yi NOjxtBnKB9DruyTfPmIxWSTf1TxaPxStFVG+/9LVHxDMDUpNVnTXrpvz4mHVYJ/WSS 6UTG/5rqhViX4Opbwz8MAlC4j/QdSUK7SgsG1DGKbsKXamnN6e2xcZBubh9VQhZehW rp2fU9IuYHEQw== From: Yixun Lan Date: Mon, 11 May 2026 02:59:09 +0000 Subject: [PATCH v2 1/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org> References: <20260511-06-pci-clk-fix-v2-0-c9a5e563bab3@kernel.org> In-Reply-To: <20260511-06-pci-clk-fix-v2-0-c9a5e563bab3@kernel.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Inochi Amaoto , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2734; i=dlan@kernel.org; h=from:subject:message-id; bh=UA/S9cLsNrwPIyQx/17ZpDqEZXlb8oCbwx2AeLnP4tA=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBqAUYDNADeAp9EG+/1Pm7EgKZgd1gfP4VI92uxz s/PZNf2hyeJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCagFGAxsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+3vYw/9FsunmNwj3qzz/V6ypxizxz5gTJXnTB9Pp3PpSdt+yEmfej1n4T5AO ycBXb7QuWLxoEfLWiJHvx2idO2SH9J1e5HBNyIGVpkBj2ELf93Qahwlbh4UjNhOaXmqRs8TZtY/ uILLoKnN9c+F3C208Mv8qnHMmBxpVSlu66VhP+VjqV0MC+flUMM4wNSwTFbUa689nvN9sSwDnZh G/vx+hTqU9uA7fDcgSnxNJjKGPxdmo1FbJoSW3tWFWhllzRa44UbmB0Z3l4xv03DJE+lYEi+nxM CFHXSqJrnbAe0fbHqThpMgVnZRxT0wqJV7xV6NuAnGUpSf0piwSUaShcL+DYO5B8EMwssZX0rLz 7FE2UCjvkq8+i12AuTujox3HQR7nU6WAhEUAJvyk2JRKp89eco1Khc4VPcGzcGmcIN5Ne0+Dhg8 WjUSD/G5pkGWsaT1w6ULHskE2MOXBz88xVFoAAh2wwImt9oX2+ZzF/yusCct2J97AfNh3LNFcAF 4TQQHWwYiitrO8rfKl883FJaUJAE2UwzZwES3au3e5/8afiOXh+ui5qCTpRgi4ngeTqAcGzj2ir 1TNYJekoNhisqpxiwmXX2VHTYTDsjmvzqNNUzjDiofHALLj4vGzosPYld0aJKOSmhoO7mhOJHK9 6oRV0bU5lBp+049Qti8tdAAkmkniso= X-Developer-Key: i=dlan@kernel.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 According to SpacemiT updated docs, the PCIe master and slave clock's parent is the pll2_d6 clock, so fix it. Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") Signed-off-by: Yixun Lan --- drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index e98afd59f05c..8f0b743046ab 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents= [] =3D { }; CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, = 1, BIT(17), 0); =20 -CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); -CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); -CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); -CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); -CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); -CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); -CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); -CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); -CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); -CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); +CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); +CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); +CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); +CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); +CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); +CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); +CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); +CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); +CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); +CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); =20 static const struct clk_parent_data emac_1588_parents[] =3D { CCU_PARENT_NAME(vctcxo_24m), --=20 2.54.0 From nobody Sat Jun 13 04:19:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F52536CE1C; Mon, 11 May 2026 02:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778468377; 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a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 The offset of PCIe Clock CTRL register for port B and C controller was wrongly swapped, correct it here. Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") Signed-off-by: Yixun Lan Acked-by: Conor Dooley --- include/soc/spacemit/k3-syscon.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-sys= con.h index 0299bea065a0..a68255dd641f 100644 --- a/include/soc/spacemit/k3-syscon.h +++ b/include/soc/spacemit/k3-syscon.h @@ -168,8 +168,8 @@ #define APMU_CPU_C2_CLK_CTRL 0x394 #define APMU_CPU_C3_CLK_CTRL 0x208 #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 --=20 2.54.0 From nobody Sat Jun 13 04:19:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E72526ED46; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org> References: <20260511-06-pci-clk-fix-v2-0-c9a5e563bab3@kernel.org> In-Reply-To: <20260511-06-pci-clk-fix-v2-0-c9a5e563bab3@kernel.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Inochi Amaoto , Krzysztof Kozlowski , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=861; i=dlan@kernel.org; h=from:subject:message-id; bh=62GFDbMhrf9Hmoi1Uc8kFyF4ciHaqpBzUokKVG2CQe4=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBqAUYJTaej5SBATnnsigEQdD+rTWC3jpqtX29uv BMQCLX3BiiJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCagFGCRsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+0UhQ//etf6fkp4Z+h/0EGk6dhK2chO/s+iitT9uA/dId0n23K63Ggbgy5sa L+Gfy6C0uF4rsQTaXr89cU/kyqBYsBdTuERvk2B54BpV5KPNrOwqo+GTW8dISqEsb8+HH5qCbQk WycI8DIZMDCIYn+PRtZjl3mpghtAh1eBOGbmqslCz2XXwMudz9kV3laTxYXRNvnHe1bB+d4mec4 Ic4vqQjSRDbxV6915yHVs59UEhL7xM7KEG0i0WnJP141ViwYkMjefgeTuGIM/wYGIrrc9vHS85i qV7l+Nv76sJ4T3wNzOIxmXEfyL/+k+hRpYOSmF+dcn7jLqVQ5oqr7B+e6lC+SU0Aa5Xe31Dv0Aa A5H0YD/y0Z2/L/Ds4fVjicwLTvySZa1crzr7EYsGnEc529IEceV+0Jrj8GNRvTTn9zDI7OFDIn/ 0TcaK/nreMRYLydrANhLt25E0IrnmnKvR/Fwnem4SB2foK/r6/db/5FQxho7HOmABnWoS5KpTKQ 9NjieuDcEi+EBI8BEiU/eSN40GLbTxwCiqLdUpEREQ+XaVl03KQJs2BdnZQ+I7pxM06QCHy0Xyj WdIpsE0TTCpJX31f2O3ueDPcneybDfQyOVv92AJD3if53wBYmfSdYs2ylYDu6K/cqxiZ8w9a/6v cuA6vJUibrAnMZnMqVyQNaM208dHG4= X-Developer-Key: i=dlan@kernel.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add clock IDs of PCIe DBI (Data Bus Interface) clock. Signed-off-by: Yixun Lan Acked-by: Conor Dooley --- include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bi= ndings/clock/spacemit,k3-clocks.h index b22336f3ae40..dfae52547cda 100644 --- a/include/dt-bindings/clock/spacemit,k3-clocks.h +++ b/include/dt-bindings/clock/spacemit,k3-clocks.h @@ -380,6 +380,11 @@ #define CLK_APMU_ISIM_VCLK1 86 #define CLK_APMU_ISIM_VCLK2 87 #define CLK_APMU_ISIM_VCLK3 88 +#define CLK_APMU_PCIE_PORTA_DBI 89 +#define CLK_APMU_PCIE_PORTB_DBI 90 +#define CLK_APMU_PCIE_PORTC_DBI 91 +#define CLK_APMU_PCIE_PORTD_DBI 92 +#define CLK_APMU_PCIE_PORTE_DBI 93 =20 /* DCIU clocks */ #define CLK_DCIU_HDMA 0 --=20 2.54.0 From nobody Sat Jun 13 04:19:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96E6636CDE0; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PJMBhsXq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8AF1AC2BCB8; Mon, 11 May 2026 02:59:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778468383; bh=jgdy/jxzdPVjOoV+NbNcw3Zjs55tIwNpIANgic7Sor0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PJMBhsXqizB+MSRjPMd+BpVcrQc++1BQAdqu9gs7LYn+DgWWUIufU+mVhzO7dC8sz hPhJFSiye0hBRYc0sMKvxTlQEWdSCrRaY2y3datpSawY+yn3oK17xGbHU1fvqCMVGB MnnAxCIy7jYCkkOOQXJY3dFwMZtDGPFQ2ewg3Q7B+dkvKGXc90WaXfRnhcqbR+jnSd 0nH+EKGZkRf6O38SHkk++UHO9EIUBrpBZux0alonov8Z1XAKzAadudPSDby9xoPt09 7ZcCoqfKfTMXBFdEqh4EUuCFKGgSho7kP76IoiQxgLpSjUHYKoUwjkhIwSqOs3kZku wjXDvWG3Bay2A== From: Yixun Lan Date: Mon, 11 May 2026 02:59:12 +0000 Subject: [PATCH v2 4/4] clk: spacemit: k3: Add PCIe DBI clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add PCIe DBI (Data Bus Interface) clock which was missing, This will support PCIe driver to explicitly request and enable all clocks that needed. Signed-off-by: Yixun Lan --- drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index 8f0b743046ab..196d32194125 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, AP= MU_LCD_EDP_CTRL, 18, 1, BIT =20 CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); +CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(0), 0); CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); +CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(0), 0); CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); +CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(0), 0); CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); +CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(0), 0); CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); +CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(0), 0); =20 static const struct clk_parent_data emac_1588_parents[] =3D { CCU_PARENT_NAME(vctcxo_24m), @@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] =3D { [CLK_APMU_EDP1_PXCLK] =3D &edp1_pxclk.common.hw, [CLK_APMU_PCIE_PORTA_MSTE] =3D &pciea_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTA_SLV] =3D &pciea_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTA_DBI] =3D &pciea_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTB_MSTE] =3D &pcieb_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTB_SLV] =3D &pcieb_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTB_DBI] =3D &pcieb_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTC_MSTE] =3D &pciec_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTC_SLV] =3D &pciec_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTC_DBI] =3D &pciec_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTD_MSTE] =3D &pcied_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTD_SLV] =3D &pcied_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTD_DBI] =3D &pcied_dbi_clk.common.hw, [CLK_APMU_PCIE_PORTE_MSTE] =3D &pciee_mstr_clk.common.hw, [CLK_APMU_PCIE_PORTE_SLV] =3D &pciee_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTE_DBI] =3D &pciee_dbi_clk.common.hw, [CLK_APMU_EMAC0_BUS] =3D &emac0_bus_clk.common.hw, [CLK_APMU_EMAC0_REF] =3D &emac0_ref_clk.common.hw, [CLK_APMU_EMAC0_1588] =3D &emac0_1588_clk.common.hw, --=20 2.54.0