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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:43:46 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc , Geert Uytterhoeven Subject: [PATCH v3 01/10] ASoC: dt-bindings: renesas,fsi: add support multiple clocks Date: Sun, 10 May 2026 15:42:54 +0700 Message-ID: <20260510084303.122426-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before accessing its registers. Without this clock, any register access leads to a system hang as the FSI block sits behind the SPU bus. Update the binding to support multiple clocks to properly describe the hardware clock tree, including: - SPU bus/bridge clock (spu) for register access. - CPG DIV6 clocks (icka/b) as functional clock parents. - FSI internal dividers (diva/b) for audio clock generation. - External clock inputs (xcka/b) provided by the board. Suggested-by: Geert Uytterhoeven Signed-off-by: bui duc phuc Suggested-by tag now and will remove it in the v4 patch set. --- .../bindings/sound/renesas,fsi.yaml | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Doc= umentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..c50e7115b21a 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -38,7 +38,32 @@ properties: maxItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main FSI module clock + - description: | + SPU bus/bridge clock. On R8A7740, this clock must be enabled to = allow + register access as the FSI block is connected behind the SPU bus. + - description: CPG DIV6 functional clocks for FSI port A + - description: CPG DIV6 functional clocks for FSI port B + - description: Internal FSI dividers for port A used for audio clock= generation + - description: Internal FSI dividers for port B used for audio clock= generation + - description: External clock inputs for FSI port A provided by the = board + - description: External clock inputs for FSI port B provided by the = board + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - fck # Main FSI module clock + - spu # optional SPU bus/bridge clock + - icka # optional CPG DIV6 functional clocks for FSI port A + - ickb # optional CPG DIV6 functional clocks for FSI port B + - diva # optional Internal FSI dividers for port A used for audio = clock generation + - divb # optional Internal FSI dividers for port B used for audio = clock generation + - xcka # optional External clock inputs for FSI port A provided by= the board + - xckb # optional External clock inputs for FSI port B provided by= the board =20 power-domains: maxItems: 1 --=20 2.43.0 From nobody Sat Jun 13 04:46:05 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5014A369970 for ; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:43:51 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 02/10] arm: dts: renesas: r8a7740: Add clocks for FSI Date: Sun, 10 May 2026 15:42:55 +0700 Message-ID: <20260510084303.122426-3-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Add the SPU clock to the FSI node to ensure it is enabled before register access, preventing potential system hangs. Add missing clocks for FSI (icka/b, xcka/b). Signed-off-by: bui duc phuc --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/ren= esas/r8a7740.dtsi index d13ab86c3ab4..6f9d9bbfd159 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -393,7 +393,11 @@ sh_fsi2: sound@fe1f0000 { compatible =3D "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg =3D <0xfe1f0000 0x400>; interrupts =3D ; - clocks =3D <&mstp3_clks R8A7740_CLK_FSI>; + clocks =3D <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names =3D "fck", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains =3D <&pd_a4mp>; status =3D "disabled"; }; @@ -614,6 +618,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells =3D <0>; }; + fsib_clk: fsib@e6150090 { + compatible =3D "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg =3D <0xe6150090 4>; + clocks =3D <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:43:57 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 03/10] ASoC: renesas: fsi: Fix trigger stop ordering Date: Sun, 10 May 2026 15:42:56 +0700 Message-ID: <20260510084303.122426-4-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Reorder calls to execute fsi_stream_stop() before fsi_hw_shutdown(). This ensures that all register accesses are completed before the clock is disabled, preventing the system hang observed on r8a7740. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 8cbd7acc26f4..94ab2e490810 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1586,9 +1586,9 @@ static int fsi_dai_trigger(struct snd_pcm_substream *= substream, int cmd, ret =3D fsi_stream_transfer(io); break; case SNDRV_PCM_TRIGGER_STOP: + fsi_stream_stop(fsi, io); if (!ret) ret =3D fsi_hw_shutdown(fsi, dai->dev); - fsi_stream_stop(fsi, io); fsi_stream_quit(fsi, io); break; } --=20 2.43.0 From nobody Sat Jun 13 04:46:05 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F115C36A033 for ; Sun, 10 May 2026 08:44:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402644; cv=none; b=fYg/pjRIP/+sbXYsXWtgaFdEF0euX6Lbfx9g/WepZ4VvmIAkGvuTrMUqjmUOF60FEjkac5Bb3OdhH9gurANT5K0BHaUkiASqknFuzzhw0WzqQ5nJAzHGTSVjm8WaYwqD/EwdPUkm54nv/2Nbzf/zFMzN+jo0OXtb6SPptjPj4Mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402644; c=relaxed/simple; bh=EzZNAd1+G2Bcw6lQD7STgANBRJQkZJfEQMfEQAU1dt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TZzpFioqbHUUaOh5Ul9Fr5hKy4HjkGD+0aUA+4lTjnZmpF0AZe8GiKzcZS3+ydIL+iqYH7fbmO2xg1SRdLzfns5Xs5YbScljjt7uNMiSc49bv+zp5JPh845J/kUNXzZumRzs9JKNYHYcmmiqRLEtBvhfrHR67hn92tas7z+Q+Mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hGUQhczD; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hGUQhczD" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-2b9fcf7c91bso32773575ad.0 for ; Sun, 10 May 2026 01:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778402642; x=1779007442; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YoAF9ct07fH3np99W6VPHFamBb7fo7xQbBMbY6jH4Mc=; b=hGUQhczDNdB7euInoK9CgBYWVVASDyUEHx/ALF4J1Sr2NcFxx6Y5tiZpLX5VLCBY3u QeCDZ6J69s5dF//WP48k/9ykj1TtdoGzo2iEYqckRP6XhVYoiYhWaGdxo2T98kp0Q0qn o1l077q5C2EGgVDWoitt10UxEsW+NOeo1wwLvI69wO8Su/jS2BnnPHpTzOHopvYI4Dt2 9eWhDzR+EKsgGX8Y3CPQEu9bcnMoO4APUyTGsUvTc3J7NNa2823DoeNpq4oR0fq08i/c R/9R/uo1E8DToDWkCXrdmkisPlh95f0YweVuwCj+PGJGwvorQ2l+65Dh4uxz15fCWtEd cdZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778402642; x=1779007442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YoAF9ct07fH3np99W6VPHFamBb7fo7xQbBMbY6jH4Mc=; b=IzvKsB3GoYwy4wOwyc1eVI9jRYmZ/3RUSvRBMt+JsNp/guT7SaqceAf7SubNHmomIy RXxUn08l5Z4banyIQICy581rd1giNKCCtz7QETP2BRc380HfaSWbpWPPGgI+LLLHb31Z OWMf/hdvjGqPRV+Kz728kJcL903AEfl3Ygwvpx6H0PLMGFtEGY0IZX/ns4IXihFKtdu4 En7JUjdGZO8qhqGOUnYIAAuPDn6KrxUKQRX8qduw8fmu/0K9BvzmKbqhc9zjwSJ7vNOd gjB6EI+JX1kNpWthK43qO1Ee9mfk81qVXOhWW8ow+QYIQ49su9pw0gD71LixzQopkqLs y/gw== X-Forwarded-Encrypted: i=1; AFNElJ+wwVsLGmUd8TDHQfS29OIoC0RPwv2pUEir6p/XwvK9PbTjVk2t1M8dMZwmQq0yaq22BGxx1ogABbkTXE0=@vger.kernel.org X-Gm-Message-State: AOJu0YyXNRyAYxAIopraRe5wrvXEpSCGbYiFjGJFjXr0m6uJWaKCbhcq 0HPmBpoyBvXFWQubxaDfeoRA+GFkNHUROVFj+Twro/77Hs+keTkVV17g X-Gm-Gg: Acq92OGVW6nIfpbQuAvWY3r4xkpa8rFcXEvw9wrkM9JrD8TbIGXHa9aF+P2VJqWzU4t HERdVwEoHXDKNEw5Y5zaZh+Td8pitymHnp51XISnWgfuUAAQSsbw0jaAxDTQudte02cVyhdqzMe BL9ZK6nYVp15aOpB+3Beu9WBHcDV0Dryz76uX+z7G8JBFjxv5hV4VreMYCe3E1Br3cIVsplkN6g 0IULH6p/jLgqaM3HUltwTKm1dYfMaHKLGZPuy8luWsP4SUe5pSQ5vc2fPj0lrtYWK7zdQWvlhC0 /ZNN6Z+lSRmizc+AVSrbxj+UbSG1MFw+aIesi5BImcGK0mKpYUiodXiTk+1viioE/bWJQDYV/vU xC6WOzF6v3VPzJLk3/OrIO00IClDem3ewWD/32F3HonOnItpltKaEUJIdv0rSbQwA1u41TTqGgm xiEZ9PBI5J2jfy8CiP38Xyzcq2rMXMqpq2yHgqEUtujycqTaRMT9BvinS44w== X-Received: by 2002:a17:902:8641:b0:2ba:6ffa:bde0 with SMTP id d9443c01a7336-2ba79c20bb9mr157009065ad.19.1778402642292; Sun, 10 May 2026 01:44:02 -0700 (PDT) Received: from phuc-desktop.. ([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:02 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 04/10] ASoC: renesas: fsi: Fix register access from in-flight IRQ after shutdown Date: Sun, 10 May 2026 15:42:57 +0700 Message-ID: <20260510084303.122426-5-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Ensure that in-flight IRQ handlers do not access hardware registers after SNDRV_PCM_TRIGGER_STOP and fsi_hw_shutdown(). An IRQ handler may still be running when the SPU clock is disabled, leading to register access after clock shutdown and causing system hangs. Prevent register access in the IRQ path once the hardware has been shut down. Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 94ab2e490810..fc8428cb1ba7 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -211,6 +211,7 @@ struct fsi_stream { int sample_width; /* sample width */ int uerr_num; int oerr_num; + bool running; =20 /* * bus options @@ -255,6 +256,8 @@ struct fsi_priv { =20 u32 fmt; =20 + int running_streams; + int chan_num:16; unsigned int clk_master:1; unsigned int clk_cpg:1; @@ -460,6 +463,9 @@ static int fsi_get_current_fifo_samples(struct fsi_priv= *fsi, =20 static void fsi_count_fifo_err(struct fsi_priv *fsi) { + if (fsi->running_streams =3D=3D 0) + return; + u32 ostatus =3D fsi_reg_read(fsi, DOFF_ST); u32 istatus =3D fsi_reg_read(fsi, DIFF_ST); =20 @@ -681,6 +687,9 @@ static void fsi_irq_clear_status(struct fsi_priv *fsi) u32 data =3D 0; struct fsi_master *master =3D fsi_get_master(fsi); =20 + if (fsi->running_streams =3D=3D 0) + return; + data |=3D AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); data |=3D AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); =20 @@ -1573,10 +1582,17 @@ static int fsi_dai_trigger(struct snd_pcm_substream= *substream, int cmd, { struct fsi_priv *fsi =3D fsi_get_priv(substream); struct fsi_stream *io =3D fsi_stream_get(fsi, substream); + bool need_shutdown =3D false; int ret =3D 0; =20 switch (cmd) { case SNDRV_PCM_TRIGGER_START: + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (!io->running) { + io->running =3D true; + fsi->running_streams++; + } + } fsi_stream_init(fsi, io, substream); if (!ret) ret =3D fsi_hw_startup(fsi, io, dai->dev); @@ -1586,8 +1602,15 @@ static int fsi_dai_trigger(struct snd_pcm_substream = *substream, int cmd, ret =3D fsi_stream_transfer(io); break; case SNDRV_PCM_TRIGGER_STOP: + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (io->running) { + io->running =3D false; + if (--fsi->running_streams =3D=3D 0) + need_shutdown =3D true; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:07 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 05/10] ASoC: renesas: fsi: Move fsi_clk_init() Date: Sun, 10 May 2026 15:42:58 +0700 Message-ID: <20260510084303.122426-6-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Move fsi_clk_init() after set_rate() functions to prepare for subsequent refactoring. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 128 ++++++++++++++++++++-------------------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index fc8428cb1ba7..06ec5709216b 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -718,70 +718,6 @@ static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, i= nt enable) /* * clock function */ -static int fsi_clk_init(struct device *dev, - struct fsi_priv *fsi, - int xck, - int ick, - int div, - int (*set_rate)(struct device *dev, - struct fsi_priv *fsi)) -{ - struct fsi_clk *clock =3D &fsi->clock; - int is_porta =3D fsi_is_port_a(fsi); - - clock->xck =3D NULL; - clock->ick =3D NULL; - clock->div =3D NULL; - clock->rate =3D 0; - clock->count =3D 0; - clock->set_rate =3D set_rate; - - clock->own =3D devm_clk_get(dev, NULL); - if (IS_ERR(clock->own)) - return -EINVAL; - - /* external clock */ - if (xck) { - clock->xck =3D devm_clk_get(dev, is_porta ? "xcka" : "xckb"); - if (IS_ERR(clock->xck)) { - dev_err(dev, "can't get xck clock\n"); - return -EINVAL; - } - if (clock->xck =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support xck clock\n"); - return -EINVAL; - } - } - - /* FSIACLK/FSIBCLK */ - if (ick) { - clock->ick =3D devm_clk_get(dev, is_porta ? "icka" : "ickb"); - if (IS_ERR(clock->ick)) { - dev_err(dev, "can't get ick clock\n"); - return -EINVAL; - } - if (clock->ick =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support ick clock\n"); - return -EINVAL; - } - } - - /* FSI-DIV */ - if (div) { - clock->div =3D devm_clk_get(dev, is_porta ? "diva" : "divb"); - if (IS_ERR(clock->div)) { - dev_err(dev, "can't get div clock\n"); - return -EINVAL; - } - if (clock->div =3D=3D clock->own) { - dev_err(dev, "cpu doesn't support div clock\n"); - return -EINVAL; - } - } - - return 0; -} - #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) { @@ -1035,6 +971,70 @@ static int fsi_clk_set_rate_cpg(struct device *dev, return ret; } =20 +static int fsi_clk_init(struct device *dev, + struct fsi_priv *fsi, + int xck, + int ick, + int div, + int (*set_rate)(struct device *dev, + struct fsi_priv *fsi)) +{ + struct fsi_clk *clock =3D &fsi->clock; + int is_porta =3D fsi_is_port_a(fsi); + + clock->xck =3D NULL; + clock->ick =3D NULL; + clock->div =3D NULL; + clock->rate =3D 0; + clock->count =3D 0; + clock->set_rate =3D set_rate; + + clock->own =3D devm_clk_get(dev, NULL); + if (IS_ERR(clock->own)) + return -EINVAL; + + /* external clock */ + if (xck) { + clock->xck =3D devm_clk_get(dev, is_porta ? "xcka" : "xckb"); + if (IS_ERR(clock->xck)) { + dev_err(dev, "can't get xck clock\n"); + return -EINVAL; + } + if (clock->xck =3D=3D clock->own) { + dev_err(dev, "cpu doesn't support xck clock\n"); + return -EINVAL; + } + } + + /* FSIACLK/FSIBCLK */ + if (ick) { + clock->ick =3D devm_clk_get(dev, is_porta ? "icka" : "ickb"); + if (IS_ERR(clock->ick)) { + dev_err(dev, "can't get ick clock\n"); + return -EINVAL; + } + if (clock->ick =3D=3D clock->own) { + dev_err(dev, "cpu doesn't support ick clock\n"); + return -EINVAL; + } + } + + /* FSI-DIV */ + if (div) { + clock->div =3D devm_clk_get(dev, is_porta ? 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:11 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 06/10] ASoC: renesas: fsi: Add shared SPU clock support Date: Sun, 10 May 2026 15:42:59 +0700 Message-ID: <20260510084303.122426-7-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Add SPU clock pointer and reference count for shared FSIA/FSIB usage, and initialize it in fsi_probe(). Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 06ec5709216b..55a11f1fe8aa 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -295,7 +295,9 @@ struct fsi_master { void __iomem *base; struct fsi_priv fsia; struct fsi_priv fsib; + struct clk *clk_spu; const struct fsi_core *core; + int spu_count; spinlock_t lock; }; =20 @@ -1984,6 +1986,7 @@ static int fsi_probe(struct platform_device *pdev) =20 /* master setting */ master->core =3D core; + master->spu_count =3D 0; spin_lock_init(&master->lock); =20 /* FSI A setting */ --=20 2.43.0 From nobody Sat Jun 13 04:46:05 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C179369970 for ; Sun, 10 May 2026 08:44:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402658; cv=none; b=EWLgB2Zw5l2yimwd5bI3TWHw21aCIlxRqC+qMF/4QPIl8qu/F3Hfi+OF35wQMB10KVYazGN4VrxCvO5JWRZO2NmSvy5NO+nZgJAs5XEuq2Xe1Cm90/QS92MGPmkCzSCZdP5yFAphqCPIKnHawltNzwqbw7Zmno6wKBNOvvH35sc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402658; c=relaxed/simple; bh=S8VdUXpZ5EXRzzLHhnCbiXAzluQarMo2bEw81/CmmUk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jGIyZQ6Rs2/XweaYkS+VR6SedmV9p5g27CoL9cEX6CBF/syUAn1dlrBkXgqy6PoZf0WWf+u54EC6WeWaq0SZn1Lo0jy6mYyO4NeRq/4Okt9zJhE1x7ZNq/Jogm9sguV8ncNlHOLO357gIbWHMnrQ77Gi/KTpQcPToitOn7g6Al8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EQPY11Df; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EQPY11Df" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2b941cd869cso19604775ad.1 for ; Sun, 10 May 2026 01:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778402656; x=1779007456; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y80K+Yov+kmnyD6TTF5xlQ2F59dwPBHCmkqWrn6Hjzs=; b=EQPY11Df00IQRMasi7QQCKpZQuW1EjAAdA0rboGlySd7rUgIjv1VcnJii71Qc2K+RU /DNlCsdOByRudesfJSk9TZqyFOHAZajfZSALpCmaW6/QnXF+anhJG9tQ2Fq8LQub7pU5 gLvggLJx3fhNjQIjPsBRs5FXsYPrS1LWgDiCpJURbPqDB2qG4C4H8R6MA92FpuaVzhVJ zk0YZ5Nf+p5WT4y2Rqdwth1zEhcj1omr9x6yn1BLX0cUfN/5SgOp/TbhU8O34xHnKAFE bUeQ3GbaKXgu3q3q/NgSK7lrYZda1u82CCZX5prA6+D4sNQ/LNtW6sAjZt4RYKHryMSr iRDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778402656; x=1779007456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Y80K+Yov+kmnyD6TTF5xlQ2F59dwPBHCmkqWrn6Hjzs=; b=LNhkelCTBifDlNO14yjeobDvu2AYrv9fkb3zamO5bWSgYnJwgi3+8N2CuimbtuW4f7 SiUB1XvKzQIZSU5ycn62qiNQMkwp0yZD5yFAiTvUqrWnq42U/iW9z8DtRnCmYam3dWXd ENhStmhblwl2vB46hOBEuz3JFbxQ3ADMeFfo3DZulcYMUxSDAYcIa4Y8JNijOIOWdpGE UGQTMdltxshD8TgGvx9yZrc+ZQ/9bzXUbEbOPI6s2SQ0GshqUFWurmpuK/cqBgQgeKl9 QVCVYPOFjsl0Tvqe60aOFkV+0K3yQz3U4DzQ7VJv65Kwd96bAcC4UJWqNQl/kKaZmJ9p VaLQ== X-Forwarded-Encrypted: i=1; AFNElJ84YVC1247uiWpNZghcehItdlfVsmU29p0f1BxUbc1S3P5/QgdVrlhuXX+UNIQ8bsGf6DtN4JqL5wPM20Q=@vger.kernel.org X-Gm-Message-State: AOJu0YwwcZYWeY3K/rnT7wdZ/rEkyY2YjCz0n7o7ZpaHIBOYFlaGcuGI UeU0/8PcT7Rw6m1I7rwKovqA8FEfhzgAQn/QLO2PdxDfI8tQ1qDlATAz X-Gm-Gg: Acq92OFdabYeA86OhEgryl2g8P4Fl70zxA6lbgPazgNFOL36Scx5Mn6llPVwJa66RNe Y1MsEZJcnLCQZL0S378Yk91wNZrHRTRMWqLAVId85sFbprp26KKPeA/tz6aJbPrpMpvYPmPnAY1 TE4yAsTgcvxp3otjugZ0tVV4x597plT0mS4pjhSY5aWYV85aeMIzgBeNrim2+pmlXjdj8M13dWq dvgzR+9qPQpHUnS4Fg1cQk8ig8Y3LrF64sHVEY3k7nT76w+v51hSvqq1RVEtFxDLcua31cV/pOj qCwXGzFgjd48XVs8NqY9WHXDRQkltLqsy4NAHgl8gFwdhE2f/kAhZDFKdOT8h3lSNE8DAlkEvev ik8NyIe88Fte5+9wvox00pcC9kMawawsBPGlOaogVRf7rKQxrLcHE2L3FNW/PJyPdj4XRiayDPF dyrytSDn3pG12X+g1YG0JTqlydcCeCWYXC5YhBUSqKxgZMANDHfSdzo7qQOw== X-Received: by 2002:a17:902:e790:b0:2ba:bfc:76b5 with SMTP id d9443c01a7336-2ba78b40166mr207083955ad.4.1778402656470; Sun, 10 May 2026 01:44:16 -0700 (PDT) Received: from phuc-desktop.. ([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:16 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 07/10] ASoC: renesas: fsi: refactor clock initialization Date: Sun, 10 May 2026 15:43:00 +0700 Message-ID: <20260510084303.122426-8-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Move fsi_clk_init() to probe and use devm_clk_get_optional() for optional clocks. This allows probe to succeed even when some optional clocks are missing, while set_rate() performs strict validation to ensure all required clocks are available for hardware configuration during audio setup. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 70 ++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 55a11f1fe8aa..8c46d6806958 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -865,6 +865,11 @@ static int fsi_clk_set_rate_external(struct device *de= v, int ackmd, bpfmd; int ret =3D 0; =20 + if (!xck || !ick) { + dev_err(dev, "xck clock or ick clock is missing\n"); + return -EINVAL; + } + /* check clock rate */ xrate =3D clk_get_rate(xck); if (xrate % rate) { @@ -901,6 +906,11 @@ static int fsi_clk_set_rate_cpg(struct device *dev, int ackmd, bpfmd; int ret =3D -EINVAL; =20 + if (!ick || !div) { + dev_err(dev, "ick clock or div clock is missing\n"); + return -EINVAL; + } + if (!(12288000 % rate)) target =3D 12288000; if (!(11289600 % rate)) @@ -973,35 +983,42 @@ static int fsi_clk_set_rate_cpg(struct device *dev, return ret; } =20 -static int fsi_clk_init(struct device *dev, - struct fsi_priv *fsi, - int xck, - int ick, - int div, - int (*set_rate)(struct device *dev, - struct fsi_priv *fsi)) +static int fsi_clk_init(struct device *dev, struct fsi_priv *fsi) { struct fsi_clk *clock =3D &fsi->clock; + struct fsi_master *master =3D fsi->master; int is_porta =3D fsi_is_port_a(fsi); + int xck, ick, div; + + if (fsi->clk_cpg) { + xck =3D 0; ick =3D 1; div =3D 1; + clock->set_rate =3D fsi_clk_set_rate_cpg; + } else { + xck =3D 1; ick =3D 1; div =3D 0; + clock->set_rate =3D fsi_clk_set_rate_external; + } =20 clock->xck =3D NULL; clock->ick =3D NULL; clock->div =3D NULL; clock->rate =3D 0; clock->count =3D 0; - clock->set_rate =3D set_rate; =20 clock->own =3D devm_clk_get(dev, NULL); if (IS_ERR(clock->own)) return -EINVAL; =20 + if (!master->clk_spu) { + master->clk_spu =3D devm_clk_get_optional(dev, "spu"); + if (IS_ERR(master->clk_spu)) + return PTR_ERR(master->clk_spu); + } + /* external clock */ if (xck) { - clock->xck =3D devm_clk_get(dev, is_porta ? "xcka" : "xckb"); - if (IS_ERR(clock->xck)) { - dev_err(dev, "can't get xck clock\n"); - return -EINVAL; - } + clock->xck =3D devm_clk_get_optional(dev, is_porta ? "xcka" : "xckb"); + if (IS_ERR(clock->xck)) + return dev_err_probe(dev, PTR_ERR(clock->xck), "Can't get xck clock\n"); if (clock->xck =3D=3D clock->own) { dev_err(dev, "cpu doesn't support xck clock\n"); return -EINVAL; @@ -1010,11 +1027,9 @@ static int fsi_clk_init(struct device *dev, =20 /* FSIACLK/FSIBCLK */ if (ick) { - clock->ick =3D devm_clk_get(dev, is_porta ? "icka" : "ickb"); - if (IS_ERR(clock->ick)) { - dev_err(dev, "can't get ick clock\n"); - return -EINVAL; - } + clock->ick =3D devm_clk_get_optional(dev, is_porta ? "icka" : "ickb"); + if (IS_ERR(clock->ick)) + return dev_err_probe(dev, PTR_ERR(clock->ick), "Can't get ick clock\n"); if (clock->ick =3D=3D clock->own) { dev_err(dev, "cpu doesn't support ick clock\n"); return -EINVAL; @@ -1023,11 +1038,9 @@ static int fsi_clk_init(struct device *dev, =20 /* FSI-DIV */ if (div) { - clock->div =3D devm_clk_get(dev, is_porta ? "diva" : "divb"); - if (IS_ERR(clock->div)) { - dev_err(dev, "can't get div clock\n"); - return -EINVAL; - } + clock->div =3D devm_clk_get_optional(dev, is_porta ? "diva" : "divb"); + if (IS_ERR(clock->div)) + return dev_err_probe(dev, PTR_ERR(clock->div), "Can't get div clock\n"); if (clock->div =3D=3D clock->own) { dev_err(dev, "cpu doesn't support div clock\n"); return -EINVAL; @@ -1689,15 +1702,6 @@ static int fsi_dai_set_fmt(struct snd_soc_dai *dai, = unsigned int fmt) break; } =20 - if (fsi_is_clk_master(fsi)) { - if (fsi->clk_cpg) - fsi_clk_init(dai->dev, fsi, 0, 1, 1, - fsi_clk_set_rate_cpg); - else - fsi_clk_init(dai->dev, fsi, 1, 1, 0, - fsi_clk_set_rate_external); - } - /* set format */ if (fsi_is_spdif(fsi)) ret =3D fsi_set_fmt_spdif(fsi); @@ -1997,6 +2001,7 @@ static int fsi_probe(struct platform_device *pdev) fsi->running_streams =3D 0; fsi_port_info_init(fsi, &info.port_a); fsi_handler_init(fsi, &info.port_a); + fsi_clk_init(&pdev->dev, fsi); ret =3D fsi_stream_probe(fsi, &pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "FSIA stream probe failed\n"); @@ -2011,6 +2016,7 @@ static int fsi_probe(struct platform_device *pdev) fsi->running_streams =3D 0; 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:20 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 08/10] ASoC: renesas: fsi: add fsi_clk_prepare/unprepare() Date: Sun, 10 May 2026 15:43:01 +0700 Message-ID: <20260510084303.122426-9-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Add helper functions for preparing and unpreparing FSI clocks. These helpers centralize clock prepare/unprepare handling and will be used by subsequent patches to move clock management into sleepable contexts. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 66 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index 8c46d6806958..b93809b5da15 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -732,6 +732,72 @@ static int fsi_clk_is_valid(struct fsi_priv *fsi) fsi->clock.rate; } =20 +static int fsi_clk_prepare(struct fsi_priv *fsi) +{ + struct fsi_clk *clock =3D &fsi->clock; + struct clk *spu =3D fsi->master->clk_spu; + struct clk *xck =3D clock->xck; + struct clk *ick =3D clock->ick; + struct clk *div =3D clock->div; + int ret; + + if (!IS_ERR_OR_NULL(spu) && fsi->master->spu_count =3D=3D 0) { + ret =3D clk_prepare(spu); + if (ret) + return ret; + } + + if (!IS_ERR_OR_NULL(xck)) { + ret =3D clk_prepare(xck); + if (ret) + goto err_spu; + } + + if (!IS_ERR_OR_NULL(ick)) { + ret =3D clk_prepare(ick); + if (ret) + goto err_xck; + } + + if (!IS_ERR_OR_NULL(div)) { + ret =3D clk_prepare(div); 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:25 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 09/10] ASoC: renesas: fsi: Use clock prepare handling in startup/shutdown Date: Sun, 10 May 2026 15:43:02 +0700 Message-ID: <20260510084303.122426-10-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Use fsi_clk_prepare() and fsi_clk_unprepare() in dai_startup() and dai_shutdown(). Prepare clocks only during active audio streams to reduce unnecessary power usage, and ensure clk_prepare() and related operations run in non-atomic contexts. Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index b93809b5da15..c3ac8b30f342 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1644,9 +1644,16 @@ static int fsi_dai_startup(struct snd_pcm_substream = *substream, struct snd_soc_dai *dai) { struct fsi_priv *fsi =3D fsi_get_priv(substream); + int ret; =20 fsi_clk_invalid(fsi); =20 + if (fsi->clock.count =3D=3D 0) { + ret =3D fsi_clk_prepare(fsi); + if (ret) + return ret; + } + return 0; } =20 @@ -1655,6 +1662,8 @@ static void fsi_dai_shutdown(struct snd_pcm_substream= *substream, { struct fsi_priv *fsi =3D fsi_get_priv(substream); =20 + if (fsi->clock.count =3D=3D 0) + fsi_clk_unprepare(fsi); fsi_clk_invalid(fsi); } =20 --=20 2.43.0 From nobody Sat Jun 13 04:46:05 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BED636A033 for ; Sun, 10 May 2026 08:44:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402671; cv=none; b=DetJrQ9Cg+mFkMkE8HeGA+vdUpGVc2ylVVKAJ2NCcsFA41gK0NiMsRwsU09schVDMzljj/UFeUVjAMRvNSDmAQghQUQnUYvDe1xQu2vCvImeGzVKeqLcy0k+CqnKnqDpUHQNiq6/iMvfUhDSpaiW/Rw3bTnZqcYP5mIpZO7TJLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778402671; c=relaxed/simple; bh=hWWNXcujvCRjXLBYmvogX9Tx7LSARP+jOFk6z3oIOdg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tM8R9Q+B41mndGua2KBqgT5QAXRoamGpucuugaAMXBOBZuGC8yirs6gS1HEffZQSg/oDk8A1tEbd4W9NF6k3QKPEahEUY75w5UN+XmHNiPHS/2EYExd7Cx2h+Vr7aSF4YKYaYAGNguRL6FTHdmtTUY6XecFaj8T12AnplZMdZfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=U3OIGi9i; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="U3OIGi9i" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-2b9705613ddso20642785ad.1 for ; Sun, 10 May 2026 01:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778402669; x=1779007469; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hjT6LUaCKBBOaTLM4HecbTdAzAOftGZyuLAMAnfg8dY=; b=U3OIGi9iF2g714qjCK+4M4635sGX0DgtTBpM0EEJUpyI9Mcso0o7aULhDlLrZjyCg0 ieF9qbMHb4yRkpxpEG5DtvlGFbNwt6Ap8Vts5W9Tf7okMzgVkhCE0Kl2h3xPuF+1rJ1p TWqy1OGQ77NCxQX7tJnevZkA4Z0eHW0glaC9UDHbceCjiDIii9hMpsvakzrtD+GlI8nc KhUXQ+CAkUXscCzAA0fCqzhChZA9qp7z6uN9WbePxEZYu+6qh48VeAHsvBtg81DZk5SN zonkxqaq6/wBT+cMZxttBtjiegk+oRT6GtsJacYCtbqoschJY94UPlJIr9JepN9y6Loi 4/cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778402669; x=1779007469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hjT6LUaCKBBOaTLM4HecbTdAzAOftGZyuLAMAnfg8dY=; b=OcMp0/wvZ783/7AU2VHxeYYxHm/QTVJMvmhqTAAx/Tb7B9UhrLDlHmsZBA0o2uovhu vO31WMuvsgbd4D8E1Nk6mEY43LaOHN9oyoBcKoPMwZHQww7cZbvNeMudEQR2dqDHy0fG mMmpB/HhuBaXmEI+69K3wYEwCEP7tHsnwvaBEbS7ltk0YiAfnrzjXEn0iuMMJox0g+5W gUDLOAFe4sEtfTK9M8Iz9QbOrwybux4JHuAkEMFthstsvz6F7cuhEzTFFQQ7mDCNunUP q6AZcNZElcY0B0AEUT8f0xrrcAWDfTqG5aUGRj1D8x67ChU6HpjmpHE4IY4tX6EmfOfI 2tUQ== X-Forwarded-Encrypted: i=1; AFNElJ/ulKHeZypuyk5uYxpJTswrUgekq+Ob+OOrNf+WRkjBwblLwgpQ6rAPb+UtSOJrK/lIm4Y3VkjwC9hERag=@vger.kernel.org X-Gm-Message-State: AOJu0YzVeJiP5WnWIsBA3W/oOBKGbhTe/OcXYKka2zYC+r+F3vmblYqb zoldLtr6kqTjwJ4iu8U8DkIU26PKiRJpbOGbdsRbPqZLHv+lkzextPU+ X-Gm-Gg: Acq92OGkILDiQUkndmYGV9DNiOGw7bPWGWPKqMf90YsFzcF8OS7AcqCgzGx+acZukvF gKcDoMV8PEmsn/oZuXGUQRroCBdcCO+emn+/0gsmiQSwAcjVlOhHIpX3ngLIoS/qtCXm9IBXCiF wA6Q7LvQzRX3sE+RKXej+pOUSr0TIJ/2DtMgTHvj0KjeIT2N9VUy01KWC3wNrjDXAejbZBKKR/x qP7sCQxWjr4epBvV8OeSxjdwVll4lvL4AjQZEHBjfQQHp2WPkofLEiWQcoPQvQY7Epx46DGAzRE HpTplK94djN8wtEHbxlWbDbxLf4z+Yk09miJoZdj+VyM8q5cgyYQEy8sFsUfw7Cld1N0acx1acl O3EF77Qli0erM3uCcigrhBWQY99V/VRbxvyrFgQy98+7TVDe2whKVqs7CffUtsAv092wnFaiirc meK/zBV0C/sx1ilEQEQ5rHAfX+wgdOciCtVBu/ybO/Es399FEEY4jRAl/OCw== X-Received: by 2002:a17:903:1ab0:b0:2b2:4ffc:a7c4 with SMTP id d9443c01a7336-2ba798c0a22mr174893865ad.24.1778402669575; Sun, 10 May 2026 01:44:29 -0700 (PDT) Received: from phuc-desktop.. ([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d3ffa0sm70471005ad.25.2026.05.10.01.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 01:44:29 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com Cc: broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, bui duc phuc Subject: [PATCH v3 10/10] ASoC: renesas: fsi: Add SPU clock control in hw_startup/shutdown Date: Sun, 10 May 2026 15:43:03 +0700 Message-ID: <20260510084303.122426-11-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260510084303.122426-1-phucduc.bui@gmail.com> References: <20260510084303.122426-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Enable and disable the SPU clock in fsi_hw_startup() and fsi_hw_shutdown() to ensure the clock is active while the driver accesses hardware registers. Previously, the SPU clock was enabled by the bootloader and remained active during operation. However, after adding the SPU clock to the device tree, it is disabled automatically once the system initialization completes. As a result, register accesses may occur while the clock is disabled, which can lead to system hangs. Manage the SPU clock explicitly in the driver to ensure correct behavior. Suggested-by: Kuninori Morimoto Signed-off-by: bui duc phuc --- sound/soc/renesas/fsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/sound/soc/renesas/fsi.c b/sound/soc/renesas/fsi.c index c3ac8b30f342..5307085c0615 100644 --- a/sound/soc/renesas/fsi.c +++ b/sound/soc/renesas/fsi.c @@ -1579,6 +1579,19 @@ static int fsi_hw_startup(struct fsi_priv *fsi, struct device *dev) { u32 data =3D 0; + int ret; + + /* enable spu clock */ + if (fsi->master->clk_spu) { + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (fsi->master->spu_count =3D=3D 0) { + ret =3D clk_enable(fsi->master->clk_spu); + if (ret < 0) + return ret; + } + fsi->master->spu_count++; + } + } =20 /* clock setting */ if (fsi_is_clk_master(fsi)) @@ -1636,6 +1649,12 @@ static int fsi_hw_shutdown(struct fsi_priv *fsi, /* stop master clock */ if (fsi_is_clk_master(fsi)) return fsi_clk_disable(dev, fsi); + if (fsi->master->clk_spu) { + scoped_guard(spinlock_irqsave, &fsi->master->lock) { + if (--fsi->master->spu_count =3D=3D 0) + clk_disable(fsi->master->clk_spu); + } + } =20 return 0; } --=20 2.43.0